1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
26 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Mangler.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixup.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/TargetRegistry.h"
40 using namespace llvm;
41 
42 namespace {
43 
44 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
45 class X86MCInstLower {
46   MCContext &Ctx;
47   const MachineFunction &MF;
48   const TargetMachine &TM;
49   const MCAsmInfo &MAI;
50   X86AsmPrinter &AsmPrinter;
51 public:
52   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
53 
54   Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
55                                           const MachineOperand &MO) const;
56   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
57 
58   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
59   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
60 
61 private:
62   MachineModuleInfoMachO &getMachOMMI() const;
63   Mangler *getMang() const {
64     return AsmPrinter.Mang;
65   }
66 };
67 
68 } // end anonymous namespace
69 
70 // Emit a minimal sequence of nops spanning NumBytes bytes.
71 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
72                      const MCSubtargetInfo &STI);
73 
74 namespace llvm {
75    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
76      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
77 
78   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
79 
80   void
81   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
82     MF = &F;
83     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
84         *MF->getSubtarget().getInstrInfo(),
85         *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
86   }
87 
88   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
89                                                    const MCSubtargetInfo &STI) {
90     if (InShadow) {
91       SmallString<256> Code;
92       SmallVector<MCFixup, 4> Fixups;
93       raw_svector_ostream VecOS(Code);
94       CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
95       CurrentShadowSize += Code.size();
96       if (CurrentShadowSize >= RequiredShadowSize)
97         InShadow = false; // The shadow is big enough. Stop counting.
98     }
99   }
100 
101   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
102     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
103     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
104       InShadow = false;
105       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
106                MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
107     }
108   }
109 
110   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
111     OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
112     SMShadowTracker.count(Inst, getSubtargetInfo());
113   }
114 } // end llvm namespace
115 
116 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
117                                X86AsmPrinter &asmprinter)
118     : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
119       AsmPrinter(asmprinter) {}
120 
121 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
122   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
123 }
124 
125 
126 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
127 /// operand to an MCSymbol.
128 MCSymbol *X86MCInstLower::
129 GetSymbolFromOperand(const MachineOperand &MO) const {
130   const DataLayout &DL = MF.getDataLayout();
131   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
132 
133   MCSymbol *Sym = nullptr;
134   SmallString<128> Name;
135   StringRef Suffix;
136 
137   switch (MO.getTargetFlags()) {
138   case X86II::MO_DLLIMPORT:
139     // Handle dllimport linkage.
140     Name += "__imp_";
141     break;
142   case X86II::MO_DARWIN_STUB:
143     Suffix = "$stub";
144     break;
145   case X86II::MO_DARWIN_NONLAZY:
146   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
147   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
148     Suffix = "$non_lazy_ptr";
149     break;
150   }
151 
152   if (!Suffix.empty())
153     Name += DL.getPrivateGlobalPrefix();
154 
155   unsigned PrefixLen = Name.size();
156 
157   if (MO.isGlobal()) {
158     const GlobalValue *GV = MO.getGlobal();
159     AsmPrinter.getNameWithPrefix(Name, GV);
160   } else if (MO.isSymbol()) {
161     Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
162   } else if (MO.isMBB()) {
163     assert(Suffix.empty());
164     Sym = MO.getMBB()->getSymbol();
165   }
166   unsigned OrigLen = Name.size() - PrefixLen;
167 
168   Name += Suffix;
169   if (!Sym)
170     Sym = Ctx.getOrCreateSymbol(Name);
171 
172   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
173 
174   // If the target flags on the operand changes the name of the symbol, do that
175   // before we return the symbol.
176   switch (MO.getTargetFlags()) {
177   default: break;
178   case X86II::MO_DARWIN_NONLAZY:
179   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
180     MachineModuleInfoImpl::StubValueTy &StubSym =
181       getMachOMMI().getGVStubEntry(Sym);
182     if (!StubSym.getPointer()) {
183       assert(MO.isGlobal() && "Extern symbol not handled yet");
184       StubSym =
185         MachineModuleInfoImpl::
186         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
187                     !MO.getGlobal()->hasInternalLinkage());
188     }
189     break;
190   }
191   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
192     MachineModuleInfoImpl::StubValueTy &StubSym =
193       getMachOMMI().getHiddenGVStubEntry(Sym);
194     if (!StubSym.getPointer()) {
195       assert(MO.isGlobal() && "Extern symbol not handled yet");
196       StubSym =
197         MachineModuleInfoImpl::
198         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
199                     !MO.getGlobal()->hasInternalLinkage());
200     }
201     break;
202   }
203   case X86II::MO_DARWIN_STUB: {
204     MachineModuleInfoImpl::StubValueTy &StubSym =
205       getMachOMMI().getFnStubEntry(Sym);
206     if (StubSym.getPointer())
207       return Sym;
208 
209     if (MO.isGlobal()) {
210       StubSym =
211         MachineModuleInfoImpl::
212         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
213                     !MO.getGlobal()->hasInternalLinkage());
214     } else {
215       StubSym =
216         MachineModuleInfoImpl::
217         StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
218     }
219     break;
220   }
221   }
222 
223   return Sym;
224 }
225 
226 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
227                                              MCSymbol *Sym) const {
228   // FIXME: We would like an efficient form for this, so we don't have to do a
229   // lot of extra uniquing.
230   const MCExpr *Expr = nullptr;
231   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
232 
233   switch (MO.getTargetFlags()) {
234   default: llvm_unreachable("Unknown target flag on GV operand");
235   case X86II::MO_NO_FLAG:    // No flag.
236   // These affect the name of the symbol, not any suffix.
237   case X86II::MO_DARWIN_NONLAZY:
238   case X86II::MO_DLLIMPORT:
239   case X86II::MO_DARWIN_STUB:
240     break;
241 
242   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
243   case X86II::MO_TLVP_PIC_BASE:
244     Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
245     // Subtract the pic base.
246     Expr = MCBinaryExpr::createSub(Expr,
247                                   MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
248                                                            Ctx),
249                                    Ctx);
250     break;
251   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
252   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
253   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
254   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
255   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
256   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
257   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
258   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
259   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
260   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
261   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
262   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
263   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
264   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
265   case X86II::MO_PIC_BASE_OFFSET:
266   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
267   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
268     Expr = MCSymbolRefExpr::create(Sym, Ctx);
269     // Subtract the pic base.
270     Expr = MCBinaryExpr::createSub(Expr,
271                             MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
272                                    Ctx);
273     if (MO.isJTI()) {
274       assert(MAI.doesSetDirectiveSuppressesReloc());
275       // If .set directive is supported, use it to reduce the number of
276       // relocations the assembler will generate for differences between
277       // local labels. This is only safe when the symbols are in the same
278       // section so we are restricting it to jumptable references.
279       MCSymbol *Label = Ctx.createTempSymbol();
280       AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
281       Expr = MCSymbolRefExpr::create(Label, Ctx);
282     }
283     break;
284   }
285 
286   if (!Expr)
287     Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
288 
289   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
290     Expr = MCBinaryExpr::createAdd(Expr,
291                                    MCConstantExpr::create(MO.getOffset(), Ctx),
292                                    Ctx);
293   return MCOperand::createExpr(Expr);
294 }
295 
296 
297 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
298 /// a short fixed-register form.
299 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
300   unsigned ImmOp = Inst.getNumOperands() - 1;
301   assert(Inst.getOperand(0).isReg() &&
302          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
303          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
304            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
305           Inst.getNumOperands() == 2) && "Unexpected instruction!");
306 
307   // Check whether the destination register can be fixed.
308   unsigned Reg = Inst.getOperand(0).getReg();
309   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
310     return;
311 
312   // If so, rewrite the instruction.
313   MCOperand Saved = Inst.getOperand(ImmOp);
314   Inst = MCInst();
315   Inst.setOpcode(Opcode);
316   Inst.addOperand(Saved);
317 }
318 
319 /// \brief If a movsx instruction has a shorter encoding for the used register
320 /// simplify the instruction to use it instead.
321 static void SimplifyMOVSX(MCInst &Inst) {
322   unsigned NewOpcode = 0;
323   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
324   switch (Inst.getOpcode()) {
325   default:
326     llvm_unreachable("Unexpected instruction!");
327   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
328     if (Op0 == X86::AX && Op1 == X86::AL)
329       NewOpcode = X86::CBW;
330     break;
331   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
332     if (Op0 == X86::EAX && Op1 == X86::AX)
333       NewOpcode = X86::CWDE;
334     break;
335   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
336     if (Op0 == X86::RAX && Op1 == X86::EAX)
337       NewOpcode = X86::CDQE;
338     break;
339   }
340 
341   if (NewOpcode != 0) {
342     Inst = MCInst();
343     Inst.setOpcode(NewOpcode);
344   }
345 }
346 
347 /// \brief Simplify things like MOV32rm to MOV32o32a.
348 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
349                                   unsigned Opcode) {
350   // Don't make these simplifications in 64-bit mode; other assemblers don't
351   // perform them because they make the code larger.
352   if (Printer.getSubtarget().is64Bit())
353     return;
354 
355   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
356   unsigned AddrBase = IsStore;
357   unsigned RegOp = IsStore ? 0 : 5;
358   unsigned AddrOp = AddrBase + 3;
359   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
360          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
361          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
362          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
363          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
364          (Inst.getOperand(AddrOp).isExpr() ||
365           Inst.getOperand(AddrOp).isImm()) &&
366          "Unexpected instruction!");
367 
368   // Check whether the destination register can be fixed.
369   unsigned Reg = Inst.getOperand(RegOp).getReg();
370   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
371     return;
372 
373   // Check whether this is an absolute address.
374   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
375   // to do this here.
376   bool Absolute = true;
377   if (Inst.getOperand(AddrOp).isExpr()) {
378     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
379     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
380       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
381         Absolute = false;
382   }
383 
384   if (Absolute &&
385       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
386        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
387        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
388     return;
389 
390   // If so, rewrite the instruction.
391   MCOperand Saved = Inst.getOperand(AddrOp);
392   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
393   Inst = MCInst();
394   Inst.setOpcode(Opcode);
395   Inst.addOperand(Saved);
396   Inst.addOperand(Seg);
397 }
398 
399 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
400   return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
401 }
402 
403 Optional<MCOperand>
404 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
405                                     const MachineOperand &MO) const {
406   switch (MO.getType()) {
407   default:
408     MI->dump();
409     llvm_unreachable("unknown operand type");
410   case MachineOperand::MO_Register:
411     // Ignore all implicit register operands.
412     if (MO.isImplicit())
413       return None;
414     return MCOperand::createReg(MO.getReg());
415   case MachineOperand::MO_Immediate:
416     return MCOperand::createImm(MO.getImm());
417   case MachineOperand::MO_MachineBasicBlock:
418   case MachineOperand::MO_GlobalAddress:
419   case MachineOperand::MO_ExternalSymbol:
420     return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
421   case MachineOperand::MO_MCSymbol:
422     return LowerSymbolOperand(MO, MO.getMCSymbol());
423   case MachineOperand::MO_JumpTableIndex:
424     return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
425   case MachineOperand::MO_ConstantPoolIndex:
426     return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
427   case MachineOperand::MO_BlockAddress:
428     return LowerSymbolOperand(
429         MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
430   case MachineOperand::MO_RegisterMask:
431     // Ignore call clobbers.
432     return None;
433   }
434 }
435 
436 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
437   OutMI.setOpcode(MI->getOpcode());
438 
439   for (const MachineOperand &MO : MI->operands())
440     if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
441       OutMI.addOperand(MaybeMCOp.getValue());
442 
443   // Handle a few special cases to eliminate operand modifiers.
444 ReSimplify:
445   switch (OutMI.getOpcode()) {
446   case X86::LEA64_32r:
447   case X86::LEA64r:
448   case X86::LEA16r:
449   case X86::LEA32r:
450     // LEA should have a segment register, but it must be empty.
451     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
452            "Unexpected # of LEA operands");
453     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
454            "LEA has segment specified!");
455     break;
456 
457   case X86::MOV32ri64:
458     OutMI.setOpcode(X86::MOV32ri);
459     break;
460 
461   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
462   // if one of the registers is extended, but other isn't.
463   case X86::VMOVAPDrr:
464   case X86::VMOVAPDYrr:
465   case X86::VMOVAPSrr:
466   case X86::VMOVAPSYrr:
467   case X86::VMOVDQArr:
468   case X86::VMOVDQAYrr:
469   case X86::VMOVDQUrr:
470   case X86::VMOVDQUYrr:
471   case X86::VMOVUPDrr:
472   case X86::VMOVUPDYrr:
473   case X86::VMOVUPSrr:
474   case X86::VMOVUPSYrr: {
475     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
476         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
477       unsigned NewOpc;
478       switch (OutMI.getOpcode()) {
479       default: llvm_unreachable("Invalid opcode");
480       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
481       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
482       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
483       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
484       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
485       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
486       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
487       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
488       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
489       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
490       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
491       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
492       }
493       OutMI.setOpcode(NewOpc);
494     }
495     break;
496   }
497   case X86::VMOVSDrr:
498   case X86::VMOVSSrr: {
499     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
500         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
501       unsigned NewOpc;
502       switch (OutMI.getOpcode()) {
503       default: llvm_unreachable("Invalid opcode");
504       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
505       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
506       }
507       OutMI.setOpcode(NewOpc);
508     }
509     break;
510   }
511 
512   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
513   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
514   // off all but the first operand (the callee).  FIXME: Change isel.
515   case X86::TAILJMPr64:
516   case X86::TAILJMPr64_REX:
517   case X86::CALL64r:
518   case X86::CALL64pcrel32: {
519     unsigned Opcode = OutMI.getOpcode();
520     MCOperand Saved = OutMI.getOperand(0);
521     OutMI = MCInst();
522     OutMI.setOpcode(Opcode);
523     OutMI.addOperand(Saved);
524     break;
525   }
526 
527   case X86::EH_RETURN:
528   case X86::EH_RETURN64: {
529     OutMI = MCInst();
530     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
531     break;
532   }
533 
534   case X86::CLEANUPRET: {
535     // Replace CATCHRET with the appropriate RET.
536     OutMI = MCInst();
537     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
538     break;
539   }
540 
541   case X86::CATCHRET: {
542     // Replace CATCHRET with the appropriate RET.
543     const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
544     unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
545     OutMI = MCInst();
546     OutMI.setOpcode(getRetOpcode(Subtarget));
547     OutMI.addOperand(MCOperand::createReg(ReturnReg));
548     break;
549   }
550 
551   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
552   case X86::TAILJMPr:
553   case X86::TAILJMPd:
554   case X86::TAILJMPd64: {
555     unsigned Opcode;
556     switch (OutMI.getOpcode()) {
557     default: llvm_unreachable("Invalid opcode");
558     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
559     case X86::TAILJMPd:
560     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
561     }
562 
563     MCOperand Saved = OutMI.getOperand(0);
564     OutMI = MCInst();
565     OutMI.setOpcode(Opcode);
566     OutMI.addOperand(Saved);
567     break;
568   }
569 
570   case X86::DEC16r:
571   case X86::DEC32r:
572   case X86::INC16r:
573   case X86::INC32r:
574     // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
575     if (!AsmPrinter.getSubtarget().is64Bit()) {
576       unsigned Opcode;
577       switch (OutMI.getOpcode()) {
578       default: llvm_unreachable("Invalid opcode");
579       case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
580       case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
581       case X86::INC16r: Opcode = X86::INC16r_alt; break;
582       case X86::INC32r: Opcode = X86::INC32r_alt; break;
583       }
584       OutMI.setOpcode(Opcode);
585     }
586     break;
587 
588   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
589   // this with an ugly goto in case the resultant OR uses EAX and needs the
590   // short form.
591   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
592   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
593   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
594   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
595   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
596   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
597   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
598   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
599   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
600 
601   // Atomic load and store require a separate pseudo-inst because Acquire
602   // implies mayStore and Release implies mayLoad; fix these to regular MOV
603   // instructions here
604   case X86::ACQUIRE_MOV8rm:    OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
605   case X86::ACQUIRE_MOV16rm:   OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
606   case X86::ACQUIRE_MOV32rm:   OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
607   case X86::ACQUIRE_MOV64rm:   OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
608   case X86::RELEASE_MOV8mr:    OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
609   case X86::RELEASE_MOV16mr:   OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
610   case X86::RELEASE_MOV32mr:   OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
611   case X86::RELEASE_MOV64mr:   OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
612   case X86::RELEASE_MOV8mi:    OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
613   case X86::RELEASE_MOV16mi:   OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
614   case X86::RELEASE_MOV32mi:   OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
615   case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
616   case X86::RELEASE_ADD8mi:    OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
617   case X86::RELEASE_ADD8mr:    OutMI.setOpcode(X86::ADD8mr); goto ReSimplify;
618   case X86::RELEASE_ADD32mi:   OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
619   case X86::RELEASE_ADD32mr:   OutMI.setOpcode(X86::ADD32mr); goto ReSimplify;
620   case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
621   case X86::RELEASE_ADD64mr:   OutMI.setOpcode(X86::ADD64mr); goto ReSimplify;
622   case X86::RELEASE_AND8mi:    OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
623   case X86::RELEASE_AND8mr:    OutMI.setOpcode(X86::AND8mr); goto ReSimplify;
624   case X86::RELEASE_AND32mi:   OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
625   case X86::RELEASE_AND32mr:   OutMI.setOpcode(X86::AND32mr); goto ReSimplify;
626   case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
627   case X86::RELEASE_AND64mr:   OutMI.setOpcode(X86::AND64mr); goto ReSimplify;
628   case X86::RELEASE_OR8mi:     OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
629   case X86::RELEASE_OR8mr:     OutMI.setOpcode(X86::OR8mr); goto ReSimplify;
630   case X86::RELEASE_OR32mi:    OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
631   case X86::RELEASE_OR32mr:    OutMI.setOpcode(X86::OR32mr); goto ReSimplify;
632   case X86::RELEASE_OR64mi32:  OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
633   case X86::RELEASE_OR64mr:    OutMI.setOpcode(X86::OR64mr); goto ReSimplify;
634   case X86::RELEASE_XOR8mi:    OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
635   case X86::RELEASE_XOR8mr:    OutMI.setOpcode(X86::XOR8mr); goto ReSimplify;
636   case X86::RELEASE_XOR32mi:   OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
637   case X86::RELEASE_XOR32mr:   OutMI.setOpcode(X86::XOR32mr); goto ReSimplify;
638   case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
639   case X86::RELEASE_XOR64mr:   OutMI.setOpcode(X86::XOR64mr); goto ReSimplify;
640   case X86::RELEASE_INC8m:     OutMI.setOpcode(X86::INC8m); goto ReSimplify;
641   case X86::RELEASE_INC16m:    OutMI.setOpcode(X86::INC16m); goto ReSimplify;
642   case X86::RELEASE_INC32m:    OutMI.setOpcode(X86::INC32m); goto ReSimplify;
643   case X86::RELEASE_INC64m:    OutMI.setOpcode(X86::INC64m); goto ReSimplify;
644   case X86::RELEASE_DEC8m:     OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
645   case X86::RELEASE_DEC16m:    OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
646   case X86::RELEASE_DEC32m:    OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
647   case X86::RELEASE_DEC64m:    OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
648 
649   // We don't currently select the correct instruction form for instructions
650   // which have a short %eax, etc. form. Handle this by custom lowering, for
651   // now.
652   //
653   // Note, we are currently not handling the following instructions:
654   // MOV64ao8, MOV64o8a
655   // XCHG16ar, XCHG32ar, XCHG64ar
656   case X86::MOV8mr_NOREX:
657   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
658   case X86::MOV8rm_NOREX:
659   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
660   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
661   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
662   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
663   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
664 
665   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
666   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
667   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
668   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
669   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
670   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
671   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
672   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
673   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
674   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
675   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
676   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
677   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
678   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
679   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
680   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
681   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
682   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
683   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
684   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
685   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
686   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
687   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
688   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
689   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
690   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
691   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
692   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
693   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
694   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
695   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
696   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
697   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
698   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
699   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
700   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
701 
702   // Try to shrink some forms of movsx.
703   case X86::MOVSX16rr8:
704   case X86::MOVSX32rr16:
705   case X86::MOVSX64rr32:
706     SimplifyMOVSX(OutMI);
707     break;
708   }
709 }
710 
711 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
712                                  const MachineInstr &MI) {
713 
714   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
715                   MI.getOpcode() == X86::TLS_base_addr64;
716 
717   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
718 
719   MCContext &context = OutStreamer->getContext();
720 
721   if (needsPadding)
722     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
723 
724   MCSymbolRefExpr::VariantKind SRVK;
725   switch (MI.getOpcode()) {
726     case X86::TLS_addr32:
727     case X86::TLS_addr64:
728       SRVK = MCSymbolRefExpr::VK_TLSGD;
729       break;
730     case X86::TLS_base_addr32:
731       SRVK = MCSymbolRefExpr::VK_TLSLDM;
732       break;
733     case X86::TLS_base_addr64:
734       SRVK = MCSymbolRefExpr::VK_TLSLD;
735       break;
736     default:
737       llvm_unreachable("unexpected opcode");
738   }
739 
740   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
741   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
742 
743   MCInst LEA;
744   if (is64Bits) {
745     LEA.setOpcode(X86::LEA64r);
746     LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
747     LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
748     LEA.addOperand(MCOperand::createImm(1));        // scale
749     LEA.addOperand(MCOperand::createReg(0));        // index
750     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
751     LEA.addOperand(MCOperand::createReg(0));        // seg
752   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
753     LEA.setOpcode(X86::LEA32r);
754     LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
755     LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
756     LEA.addOperand(MCOperand::createImm(1));        // scale
757     LEA.addOperand(MCOperand::createReg(0));        // index
758     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
759     LEA.addOperand(MCOperand::createReg(0));        // seg
760   } else {
761     LEA.setOpcode(X86::LEA32r);
762     LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
763     LEA.addOperand(MCOperand::createReg(0));        // base
764     LEA.addOperand(MCOperand::createImm(1));        // scale
765     LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
766     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
767     LEA.addOperand(MCOperand::createReg(0));        // seg
768   }
769   EmitAndCountInstruction(LEA);
770 
771   if (needsPadding) {
772     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
773     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
774     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
775   }
776 
777   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
778   MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
779   const MCSymbolRefExpr *tlsRef =
780     MCSymbolRefExpr::create(tlsGetAddr,
781                             MCSymbolRefExpr::VK_PLT,
782                             context);
783 
784   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
785                                                  : X86::CALLpcrel32)
786                             .addExpr(tlsRef));
787 }
788 
789 /// \brief Emit the optimal amount of multi-byte nops on X86.
790 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
791   // This works only for 64bit. For 32bit we have to do additional checking if
792   // the CPU supports multi-byte nops.
793   assert(Is64Bit && "EmitNops only supports X86-64");
794   while (NumBytes) {
795     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
796     Opc = IndexReg = Displacement = SegmentReg = 0;
797     BaseReg = X86::RAX; ScaleVal = 1;
798     switch (NumBytes) {
799     case  0: llvm_unreachable("Zero nops?"); break;
800     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
801     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
802     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
803     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
804     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
805              IndexReg = X86::RAX; break;
806     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
807              IndexReg = X86::RAX; break;
808     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
809     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
810              IndexReg = X86::RAX; break;
811     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
812              IndexReg = X86::RAX; break;
813     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
814              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
815     }
816 
817     unsigned NumPrefixes = std::min(NumBytes, 5U);
818     NumBytes -= NumPrefixes;
819     for (unsigned i = 0; i != NumPrefixes; ++i)
820       OS.EmitBytes("\x66");
821 
822     switch (Opc) {
823     default: llvm_unreachable("Unexpected opcode"); break;
824     case X86::NOOP:
825       OS.EmitInstruction(MCInstBuilder(Opc), STI);
826       break;
827     case X86::XCHG16ar:
828       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
829       break;
830     case X86::NOOPL:
831     case X86::NOOPW:
832       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
833                          .addImm(ScaleVal).addReg(IndexReg)
834                          .addImm(Displacement).addReg(SegmentReg), STI);
835       break;
836     }
837   } // while (NumBytes)
838 }
839 
840 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
841                                     X86MCInstLower &MCIL) {
842   assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
843 
844   StatepointOpers SOpers(&MI);
845   if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
846     EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
847              getSubtargetInfo());
848   } else {
849     // Lower call target and choose correct opcode
850     const MachineOperand &CallTarget = SOpers.getCallTarget();
851     MCOperand CallTargetMCOp;
852     unsigned CallOpcode;
853     switch (CallTarget.getType()) {
854     case MachineOperand::MO_GlobalAddress:
855     case MachineOperand::MO_ExternalSymbol:
856       CallTargetMCOp = MCIL.LowerSymbolOperand(
857           CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
858       CallOpcode = X86::CALL64pcrel32;
859       // Currently, we only support relative addressing with statepoints.
860       // Otherwise, we'll need a scratch register to hold the target
861       // address.  You'll fail asserts during load & relocation if this
862       // symbol is to far away. (TODO: support non-relative addressing)
863       break;
864     case MachineOperand::MO_Immediate:
865       CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
866       CallOpcode = X86::CALL64pcrel32;
867       // Currently, we only support relative addressing with statepoints.
868       // Otherwise, we'll need a scratch register to hold the target
869       // immediate.  You'll fail asserts during load & relocation if this
870       // address is to far away. (TODO: support non-relative addressing)
871       break;
872     case MachineOperand::MO_Register:
873       CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
874       CallOpcode = X86::CALL64r;
875       break;
876     default:
877       llvm_unreachable("Unsupported operand type in statepoint call target");
878       break;
879     }
880 
881     // Emit call
882     MCInst CallInst;
883     CallInst.setOpcode(CallOpcode);
884     CallInst.addOperand(CallTargetMCOp);
885     OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
886   }
887 
888   // Record our statepoint node in the same section used by STACKMAP
889   // and PATCHPOINT
890   SM.recordStatepoint(MI);
891 }
892 
893 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI,
894                                        X86MCInstLower &MCIL) {
895   // FAULTING_LOAD_OP <def>, <handler label>, <load opcode>, <load operands>
896 
897   unsigned LoadDefRegister = MI.getOperand(0).getReg();
898   MCSymbol *HandlerLabel = MI.getOperand(1).getMCSymbol();
899   unsigned LoadOpcode = MI.getOperand(2).getImm();
900   unsigned LoadOperandsBeginIdx = 3;
901 
902   FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel);
903 
904   MCInst LoadMI;
905   LoadMI.setOpcode(LoadOpcode);
906 
907   if (LoadDefRegister != X86::NoRegister)
908     LoadMI.addOperand(MCOperand::createReg(LoadDefRegister));
909 
910   for (auto I = MI.operands_begin() + LoadOperandsBeginIdx,
911             E = MI.operands_end();
912        I != E; ++I)
913     if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I))
914       LoadMI.addOperand(MaybeOperand.getValue());
915 
916   OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo());
917 }
918 
919 // Lower a stackmap of the form:
920 // <id>, <shadowBytes>, ...
921 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
922   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
923   SM.recordStackMap(MI);
924   unsigned NumShadowBytes = MI.getOperand(1).getImm();
925   SMShadowTracker.reset(NumShadowBytes);
926 }
927 
928 // Lower a patchpoint of the form:
929 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
930 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
931                                     X86MCInstLower &MCIL) {
932   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
933 
934   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
935 
936   SM.recordPatchPoint(MI);
937 
938   PatchPointOpers opers(&MI);
939   unsigned ScratchIdx = opers.getNextScratchIdx();
940   unsigned EncodedBytes = 0;
941   const MachineOperand &CalleeMO =
942     opers.getMetaOper(PatchPointOpers::TargetPos);
943 
944   // Check for null target. If target is non-null (i.e. is non-zero or is
945   // symbolic) then emit a call.
946   if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
947     MCOperand CalleeMCOp;
948     switch (CalleeMO.getType()) {
949     default:
950       /// FIXME: Add a verifier check for bad callee types.
951       llvm_unreachable("Unrecognized callee operand type.");
952     case MachineOperand::MO_Immediate:
953       if (CalleeMO.getImm())
954         CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
955       break;
956     case MachineOperand::MO_ExternalSymbol:
957     case MachineOperand::MO_GlobalAddress:
958       CalleeMCOp =
959         MCIL.LowerSymbolOperand(CalleeMO,
960                                 MCIL.GetSymbolFromOperand(CalleeMO));
961       break;
962     }
963 
964     // Emit MOV to materialize the target address and the CALL to target.
965     // This is encoded with 12-13 bytes, depending on which register is used.
966     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
967     if (X86II::isX86_64ExtendedReg(ScratchReg))
968       EncodedBytes = 13;
969     else
970       EncodedBytes = 12;
971 
972     EmitAndCountInstruction(
973         MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
974     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
975   }
976 
977   // Emit padding.
978   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
979   assert(NumBytes >= EncodedBytes &&
980          "Patchpoint can't request size less than the length of a call.");
981 
982   EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
983            getSubtargetInfo());
984 }
985 
986 // Returns instruction preceding MBBI in MachineFunction.
987 // If MBBI is the first instruction of the first basic block, returns null.
988 static MachineBasicBlock::const_iterator
989 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
990   const MachineBasicBlock *MBB = MBBI->getParent();
991   while (MBBI == MBB->begin()) {
992     if (MBB == MBB->getParent()->begin())
993       return nullptr;
994     MBB = MBB->getPrevNode();
995     MBBI = MBB->end();
996   }
997   return --MBBI;
998 }
999 
1000 static const Constant *getConstantFromPool(const MachineInstr &MI,
1001                                            const MachineOperand &Op) {
1002   if (!Op.isCPI())
1003     return nullptr;
1004 
1005   ArrayRef<MachineConstantPoolEntry> Constants =
1006       MI.getParent()->getParent()->getConstantPool()->getConstants();
1007   const MachineConstantPoolEntry &ConstantEntry =
1008       Constants[Op.getIndex()];
1009 
1010   // Bail if this is a machine constant pool entry, we won't be able to dig out
1011   // anything useful.
1012   if (ConstantEntry.isMachineConstantPoolEntry())
1013     return nullptr;
1014 
1015   auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
1016   assert((!C || ConstantEntry.getType() == C->getType()) &&
1017          "Expected a constant of the same type!");
1018   return C;
1019 }
1020 
1021 static std::string getShuffleComment(const MachineOperand &DstOp,
1022                                      const MachineOperand &SrcOp,
1023                                      ArrayRef<int> Mask) {
1024   std::string Comment;
1025 
1026   // Compute the name for a register. This is really goofy because we have
1027   // multiple instruction printers that could (in theory) use different
1028   // names. Fortunately most people use the ATT style (outside of Windows)
1029   // and they actually agree on register naming here. Ultimately, this is
1030   // a comment, and so its OK if it isn't perfect.
1031   auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1032     return X86ATTInstPrinter::getRegisterName(RegNum);
1033   };
1034 
1035   StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1036   StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
1037 
1038   raw_string_ostream CS(Comment);
1039   CS << DstName << " = ";
1040   bool NeedComma = false;
1041   bool InSrc = false;
1042   for (int M : Mask) {
1043     // Wrap up any prior entry...
1044     if (M == SM_SentinelZero && InSrc) {
1045       InSrc = false;
1046       CS << "]";
1047     }
1048     if (NeedComma)
1049       CS << ",";
1050     else
1051       NeedComma = true;
1052 
1053     // Print this shuffle...
1054     if (M == SM_SentinelZero) {
1055       CS << "zero";
1056     } else {
1057       if (!InSrc) {
1058         InSrc = true;
1059         CS << SrcName << "[";
1060       }
1061       if (M == SM_SentinelUndef)
1062         CS << "u";
1063       else
1064         CS << M;
1065     }
1066   }
1067   if (InSrc)
1068     CS << "]";
1069   CS.flush();
1070 
1071   return Comment;
1072 }
1073 
1074 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1075   X86MCInstLower MCInstLowering(*MF, *this);
1076   const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1077 
1078   switch (MI->getOpcode()) {
1079   case TargetOpcode::DBG_VALUE:
1080     llvm_unreachable("Should be handled target independently");
1081 
1082   // Emit nothing here but a comment if we can.
1083   case X86::Int_MemBarrier:
1084     OutStreamer->emitRawComment("MEMBARRIER");
1085     return;
1086 
1087 
1088   case X86::EH_RETURN:
1089   case X86::EH_RETURN64: {
1090     // Lower these as normal, but add some comments.
1091     unsigned Reg = MI->getOperand(0).getReg();
1092     OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1093                             X86ATTInstPrinter::getRegisterName(Reg));
1094     break;
1095   }
1096   case X86::CLEANUPRET: {
1097     // Lower these as normal, but add some comments.
1098     OutStreamer->AddComment("CLEANUPRET");
1099     break;
1100   }
1101 
1102   case X86::CATCHRET: {
1103     // Lower these as normal, but add some comments.
1104     OutStreamer->AddComment("CATCHRET");
1105     break;
1106   }
1107 
1108   case X86::TAILJMPr:
1109   case X86::TAILJMPm:
1110   case X86::TAILJMPd:
1111   case X86::TAILJMPr64:
1112   case X86::TAILJMPm64:
1113   case X86::TAILJMPd64:
1114   case X86::TAILJMPr64_REX:
1115   case X86::TAILJMPm64_REX:
1116   case X86::TAILJMPd64_REX:
1117     // Lower these as normal, but add some comments.
1118     OutStreamer->AddComment("TAILCALL");
1119     break;
1120 
1121   case X86::TLS_addr32:
1122   case X86::TLS_addr64:
1123   case X86::TLS_base_addr32:
1124   case X86::TLS_base_addr64:
1125     return LowerTlsAddr(MCInstLowering, *MI);
1126 
1127   case X86::MOVPC32r: {
1128     // This is a pseudo op for a two instruction sequence with a label, which
1129     // looks like:
1130     //     call "L1$pb"
1131     // "L1$pb":
1132     //     popl %esi
1133 
1134     // Emit the call.
1135     MCSymbol *PICBase = MF->getPICBaseSymbol();
1136     // FIXME: We would like an efficient form for this, so we don't have to do a
1137     // lot of extra uniquing.
1138     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1139       .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1140 
1141     // Emit the label.
1142     OutStreamer->EmitLabel(PICBase);
1143 
1144     // popl $reg
1145     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1146                             .addReg(MI->getOperand(0).getReg()));
1147     return;
1148   }
1149 
1150   case X86::ADD32ri: {
1151     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1152     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1153       break;
1154 
1155     // Okay, we have something like:
1156     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1157 
1158     // For this, we want to print something like:
1159     //   MYGLOBAL + (. - PICBASE)
1160     // However, we can't generate a ".", so just emit a new label here and refer
1161     // to it.
1162     MCSymbol *DotSym = OutContext.createTempSymbol();
1163     OutStreamer->EmitLabel(DotSym);
1164 
1165     // Now that we have emitted the label, lower the complex operand expression.
1166     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1167 
1168     const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1169     const MCExpr *PICBase =
1170       MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1171     DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1172 
1173     DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
1174                                       DotExpr, OutContext);
1175 
1176     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1177       .addReg(MI->getOperand(0).getReg())
1178       .addReg(MI->getOperand(1).getReg())
1179       .addExpr(DotExpr));
1180     return;
1181   }
1182   case TargetOpcode::STATEPOINT:
1183     return LowerSTATEPOINT(*MI, MCInstLowering);
1184 
1185   case TargetOpcode::FAULTING_LOAD_OP:
1186     return LowerFAULTING_LOAD_OP(*MI, MCInstLowering);
1187 
1188   case TargetOpcode::STACKMAP:
1189     return LowerSTACKMAP(*MI);
1190 
1191   case TargetOpcode::PATCHPOINT:
1192     return LowerPATCHPOINT(*MI, MCInstLowering);
1193 
1194   case X86::MORESTACK_RET:
1195     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1196     return;
1197 
1198   case X86::MORESTACK_RET_RESTORE_R10:
1199     // Return, then restore R10.
1200     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1201     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1202                             .addReg(X86::R10)
1203                             .addReg(X86::RAX));
1204     return;
1205 
1206   case X86::SEH_PushReg:
1207     OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1208     return;
1209 
1210   case X86::SEH_SaveReg:
1211     OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1212                                    MI->getOperand(1).getImm());
1213     return;
1214 
1215   case X86::SEH_SaveXMM:
1216     OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1217                                    MI->getOperand(1).getImm());
1218     return;
1219 
1220   case X86::SEH_StackAlloc:
1221     OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1222     return;
1223 
1224   case X86::SEH_SetFrame:
1225     OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1226                                     MI->getOperand(1).getImm());
1227     return;
1228 
1229   case X86::SEH_PushFrame:
1230     OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1231     return;
1232 
1233   case X86::SEH_EndPrologue:
1234     OutStreamer->EmitWinCFIEndProlog();
1235     return;
1236 
1237   case X86::SEH_Epilogue: {
1238     MachineBasicBlock::const_iterator MBBI(MI);
1239     // Check if preceded by a call and emit nop if so.
1240     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1241       // Conservatively assume that pseudo instructions don't emit code and keep
1242       // looking for a call. We may emit an unnecessary nop in some cases.
1243       if (!MBBI->isPseudo()) {
1244         if (MBBI->isCall())
1245           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1246         break;
1247       }
1248     }
1249     return;
1250   }
1251 
1252     // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1253     // a constant shuffle mask. We won't be able to do this at the MC layer
1254     // because the mask isn't an immediate.
1255   case X86::PSHUFBrm:
1256   case X86::VPSHUFBrm:
1257   case X86::VPSHUFBYrm: {
1258     if (!OutStreamer->isVerboseAsm())
1259       break;
1260     assert(MI->getNumOperands() > 5 &&
1261            "We should always have at least 5 operands!");
1262     const MachineOperand &DstOp = MI->getOperand(0);
1263     const MachineOperand &SrcOp = MI->getOperand(1);
1264     const MachineOperand &MaskOp = MI->getOperand(5);
1265 
1266     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1267       SmallVector<int, 16> Mask;
1268       DecodePSHUFBMask(C, Mask);
1269       if (!Mask.empty())
1270         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1271     }
1272     break;
1273   }
1274   case X86::VPERMILPSrm:
1275   case X86::VPERMILPDrm:
1276   case X86::VPERMILPSYrm:
1277   case X86::VPERMILPDYrm: {
1278     if (!OutStreamer->isVerboseAsm())
1279       break;
1280     assert(MI->getNumOperands() > 5 &&
1281            "We should always have at least 5 operands!");
1282     const MachineOperand &DstOp = MI->getOperand(0);
1283     const MachineOperand &SrcOp = MI->getOperand(1);
1284     const MachineOperand &MaskOp = MI->getOperand(5);
1285 
1286     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1287       SmallVector<int, 16> Mask;
1288       DecodeVPERMILPMask(C, Mask);
1289       if (!Mask.empty())
1290         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1291     }
1292     break;
1293   }
1294 
1295 #define MOV_CASE(Prefix, Suffix)        \
1296   case X86::Prefix##MOVAPD##Suffix##rm: \
1297   case X86::Prefix##MOVAPS##Suffix##rm: \
1298   case X86::Prefix##MOVUPD##Suffix##rm: \
1299   case X86::Prefix##MOVUPS##Suffix##rm: \
1300   case X86::Prefix##MOVDQA##Suffix##rm: \
1301   case X86::Prefix##MOVDQU##Suffix##rm:
1302 
1303 #define MOV_AVX512_CASE(Suffix)         \
1304   case X86::VMOVDQA64##Suffix##rm:      \
1305   case X86::VMOVDQA32##Suffix##rm:      \
1306   case X86::VMOVDQU64##Suffix##rm:      \
1307   case X86::VMOVDQU32##Suffix##rm:      \
1308   case X86::VMOVDQU16##Suffix##rm:      \
1309   case X86::VMOVDQU8##Suffix##rm:       \
1310   case X86::VMOVAPS##Suffix##rm:        \
1311   case X86::VMOVAPD##Suffix##rm:        \
1312   case X86::VMOVUPS##Suffix##rm:        \
1313   case X86::VMOVUPD##Suffix##rm:
1314 
1315 #define CASE_ALL_MOV_RM()               \
1316   MOV_CASE(, )   /* SSE */              \
1317   MOV_CASE(V, )  /* AVX-128 */          \
1318   MOV_CASE(V, Y) /* AVX-256 */          \
1319   MOV_AVX512_CASE(Z)                    \
1320   MOV_AVX512_CASE(Z256)                 \
1321   MOV_AVX512_CASE(Z128)
1322 
1323   // For loads from a constant pool to a vector register, print the constant
1324   // loaded.
1325   CASE_ALL_MOV_RM()
1326     if (!OutStreamer->isVerboseAsm())
1327       break;
1328     if (MI->getNumOperands() > 4)
1329     if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1330       std::string Comment;
1331       raw_string_ostream CS(Comment);
1332       const MachineOperand &DstOp = MI->getOperand(0);
1333       CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1334       if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1335         CS << "[";
1336         for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1337           if (i != 0)
1338             CS << ",";
1339           if (CDS->getElementType()->isIntegerTy())
1340             CS << CDS->getElementAsInteger(i);
1341           else if (CDS->getElementType()->isFloatTy())
1342             CS << CDS->getElementAsFloat(i);
1343           else if (CDS->getElementType()->isDoubleTy())
1344             CS << CDS->getElementAsDouble(i);
1345           else
1346             CS << "?";
1347         }
1348         CS << "]";
1349         OutStreamer->AddComment(CS.str());
1350       } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1351         CS << "<";
1352         for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1353           if (i != 0)
1354             CS << ",";
1355           Constant *COp = CV->getOperand(i);
1356           if (isa<UndefValue>(COp)) {
1357             CS << "u";
1358           } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1359             CS << CI->getZExtValue();
1360           } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1361             SmallString<32> Str;
1362             CF->getValueAPF().toString(Str);
1363             CS << Str;
1364           } else {
1365             CS << "?";
1366           }
1367         }
1368         CS << ">";
1369         OutStreamer->AddComment(CS.str());
1370       }
1371     }
1372     break;
1373   }
1374 
1375   MCInst TmpInst;
1376   MCInstLowering.Lower(MI, TmpInst);
1377 
1378   // Stackmap shadows cannot include branch targets, so we can count the bytes
1379   // in a call towards the shadow, but must ensure that the no thread returns
1380   // in to the stackmap shadow.  The only way to achieve this is if the call
1381   // is at the end of the shadow.
1382   if (MI->isCall()) {
1383     // Count then size of the call towards the shadow
1384     SMShadowTracker.count(TmpInst, getSubtargetInfo());
1385     // Then flush the shadow so that we fill with nops before the call, not
1386     // after it.
1387     SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1388     // Then emit the call
1389     OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1390     return;
1391   }
1392 
1393   EmitAndCountInstruction(TmpInst);
1394 }
1395