1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower X86 MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86AsmPrinter.h" 16 #include "X86RegisterInfo.h" 17 #include "X86ShuffleDecodeConstantPool.h" 18 #include "InstPrinter/X86ATTInstPrinter.h" 19 #include "MCTargetDesc/X86BaseInfo.h" 20 #include "Utils/X86ShuffleDecode.h" 21 #include "llvm/ADT/Optional.h" 22 #include "llvm/ADT/SmallString.h" 23 #include "llvm/ADT/iterator_range.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineConstantPool.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 28 #include "llvm/CodeGen/StackMaps.h" 29 #include "llvm/IR/DataLayout.h" 30 #include "llvm/IR/GlobalValue.h" 31 #include "llvm/IR/Mangler.h" 32 #include "llvm/MC/MCAsmInfo.h" 33 #include "llvm/MC/MCCodeEmitter.h" 34 #include "llvm/MC/MCContext.h" 35 #include "llvm/MC/MCExpr.h" 36 #include "llvm/MC/MCFixup.h" 37 #include "llvm/MC/MCInst.h" 38 #include "llvm/MC/MCInstBuilder.h" 39 #include "llvm/MC/MCSection.h" 40 #include "llvm/MC/MCStreamer.h" 41 #include "llvm/MC/MCSymbol.h" 42 #include "llvm/MC/MCSymbolELF.h" 43 #include "llvm/MC/MCSectionELF.h" 44 #include "llvm/Support/TargetRegistry.h" 45 #include "llvm/Support/ELF.h" 46 #include "llvm/Target/TargetLoweringObjectFile.h" 47 48 using namespace llvm; 49 50 namespace { 51 52 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 53 class X86MCInstLower { 54 MCContext &Ctx; 55 const MachineFunction &MF; 56 const TargetMachine &TM; 57 const MCAsmInfo &MAI; 58 X86AsmPrinter &AsmPrinter; 59 public: 60 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter); 61 62 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI, 63 const MachineOperand &MO) const; 64 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 65 66 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 67 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 68 69 private: 70 MachineModuleInfoMachO &getMachOMMI() const; 71 }; 72 73 } // end anonymous namespace 74 75 // Emit a minimal sequence of nops spanning NumBytes bytes. 76 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 77 const MCSubtargetInfo &STI); 78 79 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst, 80 const MCSubtargetInfo &STI, 81 MCCodeEmitter *CodeEmitter) { 82 if (InShadow) { 83 SmallString<256> Code; 84 SmallVector<MCFixup, 4> Fixups; 85 raw_svector_ostream VecOS(Code); 86 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI); 87 CurrentShadowSize += Code.size(); 88 if (CurrentShadowSize >= RequiredShadowSize) 89 InShadow = false; // The shadow is big enough. Stop counting. 90 } 91 } 92 93 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding( 94 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { 95 if (InShadow && CurrentShadowSize < RequiredShadowSize) { 96 InShadow = false; 97 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize, 98 MF->getSubtarget<X86Subtarget>().is64Bit(), STI); 99 } 100 } 101 102 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) { 103 OutStreamer->EmitInstruction(Inst, getSubtargetInfo()); 104 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get()); 105 } 106 107 X86MCInstLower::X86MCInstLower(const MachineFunction &mf, 108 X86AsmPrinter &asmprinter) 109 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()), 110 AsmPrinter(asmprinter) {} 111 112 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 113 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 114 } 115 116 117 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 118 /// operand to an MCSymbol. 119 MCSymbol *X86MCInstLower:: 120 GetSymbolFromOperand(const MachineOperand &MO) const { 121 const DataLayout &DL = MF.getDataLayout(); 122 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"); 123 124 MCSymbol *Sym = nullptr; 125 SmallString<128> Name; 126 StringRef Suffix; 127 128 switch (MO.getTargetFlags()) { 129 case X86II::MO_DLLIMPORT: 130 // Handle dllimport linkage. 131 Name += "__imp_"; 132 break; 133 case X86II::MO_DARWIN_NONLAZY: 134 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 135 Suffix = "$non_lazy_ptr"; 136 break; 137 } 138 139 if (!Suffix.empty()) 140 Name += DL.getPrivateGlobalPrefix(); 141 142 if (MO.isGlobal()) { 143 const GlobalValue *GV = MO.getGlobal(); 144 AsmPrinter.getNameWithPrefix(Name, GV); 145 } else if (MO.isSymbol()) { 146 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL); 147 } else if (MO.isMBB()) { 148 assert(Suffix.empty()); 149 Sym = MO.getMBB()->getSymbol(); 150 } 151 152 Name += Suffix; 153 if (!Sym) 154 Sym = Ctx.getOrCreateSymbol(Name); 155 156 // If the target flags on the operand changes the name of the symbol, do that 157 // before we return the symbol. 158 switch (MO.getTargetFlags()) { 159 default: break; 160 case X86II::MO_DARWIN_NONLAZY: 161 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 162 MachineModuleInfoImpl::StubValueTy &StubSym = 163 getMachOMMI().getGVStubEntry(Sym); 164 if (!StubSym.getPointer()) { 165 assert(MO.isGlobal() && "Extern symbol not handled yet"); 166 StubSym = 167 MachineModuleInfoImpl:: 168 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 169 !MO.getGlobal()->hasInternalLinkage()); 170 } 171 break; 172 } 173 } 174 175 return Sym; 176 } 177 178 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 179 MCSymbol *Sym) const { 180 // FIXME: We would like an efficient form for this, so we don't have to do a 181 // lot of extra uniquing. 182 const MCExpr *Expr = nullptr; 183 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 184 185 switch (MO.getTargetFlags()) { 186 default: llvm_unreachable("Unknown target flag on GV operand"); 187 case X86II::MO_NO_FLAG: // No flag. 188 // These affect the name of the symbol, not any suffix. 189 case X86II::MO_DARWIN_NONLAZY: 190 case X86II::MO_DLLIMPORT: 191 break; 192 193 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; 194 case X86II::MO_TLVP_PIC_BASE: 195 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 196 // Subtract the pic base. 197 Expr = MCBinaryExpr::createSub(Expr, 198 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), 199 Ctx), 200 Ctx); 201 break; 202 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break; 203 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 204 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break; 205 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break; 206 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 207 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 208 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 209 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break; 210 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 211 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break; 212 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 213 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 214 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 215 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 216 case X86II::MO_PIC_BASE_OFFSET: 217 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 218 Expr = MCSymbolRefExpr::create(Sym, Ctx); 219 // Subtract the pic base. 220 Expr = MCBinaryExpr::createSub(Expr, 221 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), 222 Ctx); 223 if (MO.isJTI()) { 224 assert(MAI.doesSetDirectiveSuppressReloc()); 225 // If .set directive is supported, use it to reduce the number of 226 // relocations the assembler will generate for differences between 227 // local labels. This is only safe when the symbols are in the same 228 // section so we are restricting it to jumptable references. 229 MCSymbol *Label = Ctx.createTempSymbol(); 230 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr); 231 Expr = MCSymbolRefExpr::create(Label, Ctx); 232 } 233 break; 234 } 235 236 if (!Expr) 237 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx); 238 239 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 240 Expr = MCBinaryExpr::createAdd(Expr, 241 MCConstantExpr::create(MO.getOffset(), Ctx), 242 Ctx); 243 return MCOperand::createExpr(Expr); 244 } 245 246 247 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 248 /// a short fixed-register form. 249 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 250 unsigned ImmOp = Inst.getNumOperands() - 1; 251 assert(Inst.getOperand(0).isReg() && 252 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 253 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 254 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 255 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 256 257 // Check whether the destination register can be fixed. 258 unsigned Reg = Inst.getOperand(0).getReg(); 259 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 260 return; 261 262 // If so, rewrite the instruction. 263 MCOperand Saved = Inst.getOperand(ImmOp); 264 Inst = MCInst(); 265 Inst.setOpcode(Opcode); 266 Inst.addOperand(Saved); 267 } 268 269 /// \brief If a movsx instruction has a shorter encoding for the used register 270 /// simplify the instruction to use it instead. 271 static void SimplifyMOVSX(MCInst &Inst) { 272 unsigned NewOpcode = 0; 273 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 274 switch (Inst.getOpcode()) { 275 default: 276 llvm_unreachable("Unexpected instruction!"); 277 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 278 if (Op0 == X86::AX && Op1 == X86::AL) 279 NewOpcode = X86::CBW; 280 break; 281 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 282 if (Op0 == X86::EAX && Op1 == X86::AX) 283 NewOpcode = X86::CWDE; 284 break; 285 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 286 if (Op0 == X86::RAX && Op1 == X86::EAX) 287 NewOpcode = X86::CDQE; 288 break; 289 } 290 291 if (NewOpcode != 0) { 292 Inst = MCInst(); 293 Inst.setOpcode(NewOpcode); 294 } 295 } 296 297 /// \brief Simplify things like MOV32rm to MOV32o32a. 298 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 299 unsigned Opcode) { 300 // Don't make these simplifications in 64-bit mode; other assemblers don't 301 // perform them because they make the code larger. 302 if (Printer.getSubtarget().is64Bit()) 303 return; 304 305 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 306 unsigned AddrBase = IsStore; 307 unsigned RegOp = IsStore ? 0 : 5; 308 unsigned AddrOp = AddrBase + 3; 309 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 310 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && 311 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && 312 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && 313 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && 314 (Inst.getOperand(AddrOp).isExpr() || 315 Inst.getOperand(AddrOp).isImm()) && 316 "Unexpected instruction!"); 317 318 // Check whether the destination register can be fixed. 319 unsigned Reg = Inst.getOperand(RegOp).getReg(); 320 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 321 return; 322 323 // Check whether this is an absolute address. 324 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 325 // to do this here. 326 bool Absolute = true; 327 if (Inst.getOperand(AddrOp).isExpr()) { 328 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 329 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 330 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 331 Absolute = false; 332 } 333 334 if (Absolute && 335 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || 336 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || 337 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) 338 return; 339 340 // If so, rewrite the instruction. 341 MCOperand Saved = Inst.getOperand(AddrOp); 342 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); 343 Inst = MCInst(); 344 Inst.setOpcode(Opcode); 345 Inst.addOperand(Saved); 346 Inst.addOperand(Seg); 347 } 348 349 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { 350 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 351 } 352 353 Optional<MCOperand> 354 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI, 355 const MachineOperand &MO) const { 356 switch (MO.getType()) { 357 default: 358 MI->dump(); 359 llvm_unreachable("unknown operand type"); 360 case MachineOperand::MO_Register: 361 // Ignore all implicit register operands. 362 if (MO.isImplicit()) 363 return None; 364 return MCOperand::createReg(MO.getReg()); 365 case MachineOperand::MO_Immediate: 366 return MCOperand::createImm(MO.getImm()); 367 case MachineOperand::MO_MachineBasicBlock: 368 case MachineOperand::MO_GlobalAddress: 369 case MachineOperand::MO_ExternalSymbol: 370 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 371 case MachineOperand::MO_MCSymbol: 372 return LowerSymbolOperand(MO, MO.getMCSymbol()); 373 case MachineOperand::MO_JumpTableIndex: 374 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 375 case MachineOperand::MO_ConstantPoolIndex: 376 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 377 case MachineOperand::MO_BlockAddress: 378 return LowerSymbolOperand( 379 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 380 case MachineOperand::MO_RegisterMask: 381 // Ignore call clobbers. 382 return None; 383 } 384 } 385 386 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 387 OutMI.setOpcode(MI->getOpcode()); 388 389 for (const MachineOperand &MO : MI->operands()) 390 if (auto MaybeMCOp = LowerMachineOperand(MI, MO)) 391 OutMI.addOperand(MaybeMCOp.getValue()); 392 393 // Handle a few special cases to eliminate operand modifiers. 394 ReSimplify: 395 switch (OutMI.getOpcode()) { 396 case X86::LEA64_32r: 397 case X86::LEA64r: 398 case X86::LEA16r: 399 case X86::LEA32r: 400 // LEA should have a segment register, but it must be empty. 401 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && 402 "Unexpected # of LEA operands"); 403 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && 404 "LEA has segment specified!"); 405 break; 406 407 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 408 // if one of the registers is extended, but other isn't. 409 case X86::VMOVZPQILo2PQIrr: 410 case X86::VMOVAPDrr: 411 case X86::VMOVAPDYrr: 412 case X86::VMOVAPSrr: 413 case X86::VMOVAPSYrr: 414 case X86::VMOVDQArr: 415 case X86::VMOVDQAYrr: 416 case X86::VMOVDQUrr: 417 case X86::VMOVDQUYrr: 418 case X86::VMOVUPDrr: 419 case X86::VMOVUPDYrr: 420 case X86::VMOVUPSrr: 421 case X86::VMOVUPSYrr: { 422 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 423 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 424 unsigned NewOpc; 425 switch (OutMI.getOpcode()) { 426 default: llvm_unreachable("Invalid opcode"); 427 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; 428 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 429 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 430 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 431 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 432 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 433 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 434 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 435 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 436 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 437 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 438 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 439 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 440 } 441 OutMI.setOpcode(NewOpc); 442 } 443 break; 444 } 445 case X86::VMOVSDrr: 446 case X86::VMOVSSrr: { 447 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 448 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 449 unsigned NewOpc; 450 switch (OutMI.getOpcode()) { 451 default: llvm_unreachable("Invalid opcode"); 452 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 453 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 454 } 455 OutMI.setOpcode(NewOpc); 456 } 457 break; 458 } 459 460 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 461 // inputs modeled as normal uses instead of implicit uses. As such, truncate 462 // off all but the first operand (the callee). FIXME: Change isel. 463 case X86::TAILJMPr64: 464 case X86::TAILJMPr64_REX: 465 case X86::CALL64r: 466 case X86::CALL64pcrel32: { 467 unsigned Opcode = OutMI.getOpcode(); 468 MCOperand Saved = OutMI.getOperand(0); 469 OutMI = MCInst(); 470 OutMI.setOpcode(Opcode); 471 OutMI.addOperand(Saved); 472 break; 473 } 474 475 case X86::EH_RETURN: 476 case X86::EH_RETURN64: { 477 OutMI = MCInst(); 478 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 479 break; 480 } 481 482 case X86::CLEANUPRET: { 483 // Replace CATCHRET with the appropriate RET. 484 OutMI = MCInst(); 485 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 486 break; 487 } 488 489 case X86::CATCHRET: { 490 // Replace CATCHRET with the appropriate RET. 491 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); 492 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 493 OutMI = MCInst(); 494 OutMI.setOpcode(getRetOpcode(Subtarget)); 495 OutMI.addOperand(MCOperand::createReg(ReturnReg)); 496 break; 497 } 498 499 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump instruction. 500 { unsigned Opcode; 501 case X86::TAILJMPr: Opcode = X86::JMP32r; goto SetTailJmpOpcode; 502 case X86::TAILJMPd: 503 case X86::TAILJMPd64: Opcode = X86::JMP_1; goto SetTailJmpOpcode; 504 case X86::TAILJMPd_CC: 505 case X86::TAILJMPd64_CC: 506 Opcode = X86::GetCondBranchFromCond( 507 static_cast<X86::CondCode>(MI->getOperand(1).getImm())); 508 goto SetTailJmpOpcode; 509 510 SetTailJmpOpcode: 511 MCOperand Saved = OutMI.getOperand(0); 512 OutMI = MCInst(); 513 OutMI.setOpcode(Opcode); 514 OutMI.addOperand(Saved); 515 break; 516 } 517 518 case X86::DEC16r: 519 case X86::DEC32r: 520 case X86::INC16r: 521 case X86::INC32r: 522 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions. 523 if (!AsmPrinter.getSubtarget().is64Bit()) { 524 unsigned Opcode; 525 switch (OutMI.getOpcode()) { 526 default: llvm_unreachable("Invalid opcode"); 527 case X86::DEC16r: Opcode = X86::DEC16r_alt; break; 528 case X86::DEC32r: Opcode = X86::DEC32r_alt; break; 529 case X86::INC16r: Opcode = X86::INC16r_alt; break; 530 case X86::INC32r: Opcode = X86::INC32r_alt; break; 531 } 532 OutMI.setOpcode(Opcode); 533 } 534 break; 535 536 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 537 // this with an ugly goto in case the resultant OR uses EAX and needs the 538 // short form. 539 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 540 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 541 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 542 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 543 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 544 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 545 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 546 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 547 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 548 549 // Atomic load and store require a separate pseudo-inst because Acquire 550 // implies mayStore and Release implies mayLoad; fix these to regular MOV 551 // instructions here 552 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; 553 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; 554 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; 555 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; 556 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; 557 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; 558 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; 559 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; 560 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify; 561 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify; 562 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify; 563 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify; 564 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify; 565 case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify; 566 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify; 567 case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify; 568 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify; 569 case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify; 570 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify; 571 case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify; 572 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify; 573 case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify; 574 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify; 575 case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify; 576 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify; 577 case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify; 578 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify; 579 case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify; 580 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify; 581 case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify; 582 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify; 583 case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify; 584 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify; 585 case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify; 586 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify; 587 case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify; 588 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify; 589 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify; 590 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify; 591 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify; 592 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify; 593 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify; 594 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify; 595 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify; 596 597 // We don't currently select the correct instruction form for instructions 598 // which have a short %eax, etc. form. Handle this by custom lowering, for 599 // now. 600 // 601 // Note, we are currently not handling the following instructions: 602 // MOV64ao8, MOV64o8a 603 // XCHG16ar, XCHG32ar, XCHG64ar 604 case X86::MOV8mr_NOREX: 605 case X86::MOV8mr: 606 case X86::MOV8rm_NOREX: 607 case X86::MOV8rm: 608 case X86::MOV16mr: 609 case X86::MOV16rm: 610 case X86::MOV32mr: 611 case X86::MOV32rm: { 612 unsigned NewOpc; 613 switch (OutMI.getOpcode()) { 614 default: llvm_unreachable("Invalid opcode"); 615 case X86::MOV8mr_NOREX: 616 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; 617 case X86::MOV8rm_NOREX: 618 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; 619 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; 620 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; 621 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break; 622 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break; 623 } 624 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc); 625 break; 626 } 627 628 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32: 629 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32: 630 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32: 631 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32: 632 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32: 633 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32: 634 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32: 635 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32: 636 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: { 637 unsigned NewOpc; 638 switch (OutMI.getOpcode()) { 639 default: llvm_unreachable("Invalid opcode"); 640 case X86::ADC8ri: NewOpc = X86::ADC8i8; break; 641 case X86::ADC16ri: NewOpc = X86::ADC16i16; break; 642 case X86::ADC32ri: NewOpc = X86::ADC32i32; break; 643 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break; 644 case X86::ADD8ri: NewOpc = X86::ADD8i8; break; 645 case X86::ADD16ri: NewOpc = X86::ADD16i16; break; 646 case X86::ADD32ri: NewOpc = X86::ADD32i32; break; 647 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break; 648 case X86::AND8ri: NewOpc = X86::AND8i8; break; 649 case X86::AND16ri: NewOpc = X86::AND16i16; break; 650 case X86::AND32ri: NewOpc = X86::AND32i32; break; 651 case X86::AND64ri32: NewOpc = X86::AND64i32; break; 652 case X86::CMP8ri: NewOpc = X86::CMP8i8; break; 653 case X86::CMP16ri: NewOpc = X86::CMP16i16; break; 654 case X86::CMP32ri: NewOpc = X86::CMP32i32; break; 655 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break; 656 case X86::OR8ri: NewOpc = X86::OR8i8; break; 657 case X86::OR16ri: NewOpc = X86::OR16i16; break; 658 case X86::OR32ri: NewOpc = X86::OR32i32; break; 659 case X86::OR64ri32: NewOpc = X86::OR64i32; break; 660 case X86::SBB8ri: NewOpc = X86::SBB8i8; break; 661 case X86::SBB16ri: NewOpc = X86::SBB16i16; break; 662 case X86::SBB32ri: NewOpc = X86::SBB32i32; break; 663 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break; 664 case X86::SUB8ri: NewOpc = X86::SUB8i8; break; 665 case X86::SUB16ri: NewOpc = X86::SUB16i16; break; 666 case X86::SUB32ri: NewOpc = X86::SUB32i32; break; 667 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break; 668 case X86::TEST8ri: NewOpc = X86::TEST8i8; break; 669 case X86::TEST16ri: NewOpc = X86::TEST16i16; break; 670 case X86::TEST32ri: NewOpc = X86::TEST32i32; break; 671 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break; 672 case X86::XOR8ri: NewOpc = X86::XOR8i8; break; 673 case X86::XOR16ri: NewOpc = X86::XOR16i16; break; 674 case X86::XOR32ri: NewOpc = X86::XOR32i32; break; 675 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break; 676 } 677 SimplifyShortImmForm(OutMI, NewOpc); 678 break; 679 } 680 681 // Try to shrink some forms of movsx. 682 case X86::MOVSX16rr8: 683 case X86::MOVSX32rr16: 684 case X86::MOVSX64rr32: 685 SimplifyMOVSX(OutMI); 686 break; 687 } 688 } 689 690 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering, 691 const MachineInstr &MI) { 692 693 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || 694 MI.getOpcode() == X86::TLS_base_addr64; 695 696 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; 697 698 MCContext &context = OutStreamer->getContext(); 699 700 if (needsPadding) 701 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 702 703 MCSymbolRefExpr::VariantKind SRVK; 704 switch (MI.getOpcode()) { 705 case X86::TLS_addr32: 706 case X86::TLS_addr64: 707 SRVK = MCSymbolRefExpr::VK_TLSGD; 708 break; 709 case X86::TLS_base_addr32: 710 SRVK = MCSymbolRefExpr::VK_TLSLDM; 711 break; 712 case X86::TLS_base_addr64: 713 SRVK = MCSymbolRefExpr::VK_TLSLD; 714 break; 715 default: 716 llvm_unreachable("unexpected opcode"); 717 } 718 719 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 720 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context); 721 722 MCInst LEA; 723 if (is64Bits) { 724 LEA.setOpcode(X86::LEA64r); 725 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest 726 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base 727 LEA.addOperand(MCOperand::createImm(1)); // scale 728 LEA.addOperand(MCOperand::createReg(0)); // index 729 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 730 LEA.addOperand(MCOperand::createReg(0)); // seg 731 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) { 732 LEA.setOpcode(X86::LEA32r); 733 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 734 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base 735 LEA.addOperand(MCOperand::createImm(1)); // scale 736 LEA.addOperand(MCOperand::createReg(0)); // index 737 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 738 LEA.addOperand(MCOperand::createReg(0)); // seg 739 } else { 740 LEA.setOpcode(X86::LEA32r); 741 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 742 LEA.addOperand(MCOperand::createReg(0)); // base 743 LEA.addOperand(MCOperand::createImm(1)); // scale 744 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index 745 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 746 LEA.addOperand(MCOperand::createReg(0)); // seg 747 } 748 EmitAndCountInstruction(LEA); 749 750 if (needsPadding) { 751 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 752 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 753 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX)); 754 } 755 756 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 757 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name); 758 const MCSymbolRefExpr *tlsRef = 759 MCSymbolRefExpr::create(tlsGetAddr, 760 MCSymbolRefExpr::VK_PLT, 761 context); 762 763 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 764 : X86::CALLpcrel32) 765 .addExpr(tlsRef)); 766 } 767 768 /// \brief Emit the largest nop instruction smaller than or equal to \p NumBytes 769 /// bytes. Return the size of nop emitted. 770 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 771 const MCSubtargetInfo &STI) { 772 // This works only for 64bit. For 32bit we have to do additional checking if 773 // the CPU supports multi-byte nops. 774 assert(Is64Bit && "EmitNops only supports X86-64"); 775 776 unsigned NopSize; 777 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; 778 Opc = IndexReg = Displacement = SegmentReg = 0; 779 BaseReg = X86::RAX; 780 ScaleVal = 1; 781 switch (NumBytes) { 782 case 0: llvm_unreachable("Zero nops?"); break; 783 case 1: NopSize = 1; Opc = X86::NOOP; break; 784 case 2: NopSize = 2; Opc = X86::XCHG16ar; break; 785 case 3: NopSize = 3; Opc = X86::NOOPL; break; 786 case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8; break; 787 case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8; 788 IndexReg = X86::RAX; break; 789 case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8; 790 IndexReg = X86::RAX; break; 791 case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512; break; 792 case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512; 793 IndexReg = X86::RAX; break; 794 case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512; 795 IndexReg = X86::RAX; break; 796 default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512; 797 IndexReg = X86::RAX; SegmentReg = X86::CS; break; 798 } 799 800 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U); 801 NopSize += NumPrefixes; 802 for (unsigned i = 0; i != NumPrefixes; ++i) 803 OS.EmitBytes("\x66"); 804 805 switch (Opc) { 806 default: 807 llvm_unreachable("Unexpected opcode"); 808 break; 809 case X86::NOOP: 810 OS.EmitInstruction(MCInstBuilder(Opc), STI); 811 break; 812 case X86::XCHG16ar: 813 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); 814 break; 815 case X86::NOOPL: 816 case X86::NOOPW: 817 OS.EmitInstruction(MCInstBuilder(Opc) 818 .addReg(BaseReg) 819 .addImm(ScaleVal) 820 .addReg(IndexReg) 821 .addImm(Displacement) 822 .addReg(SegmentReg), 823 STI); 824 break; 825 } 826 assert(NopSize <= NumBytes && "We overemitted?"); 827 return NopSize; 828 } 829 830 /// \brief Emit the optimal amount of multi-byte nops on X86. 831 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 832 const MCSubtargetInfo &STI) { 833 unsigned NopsToEmit = NumBytes; 834 (void)NopsToEmit; 835 while (NumBytes) { 836 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI); 837 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!"); 838 } 839 } 840 841 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI, 842 X86MCInstLower &MCIL) { 843 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); 844 845 StatepointOpers SOpers(&MI); 846 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) { 847 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(), 848 getSubtargetInfo()); 849 } else { 850 // Lower call target and choose correct opcode 851 const MachineOperand &CallTarget = SOpers.getCallTarget(); 852 MCOperand CallTargetMCOp; 853 unsigned CallOpcode; 854 switch (CallTarget.getType()) { 855 case MachineOperand::MO_GlobalAddress: 856 case MachineOperand::MO_ExternalSymbol: 857 CallTargetMCOp = MCIL.LowerSymbolOperand( 858 CallTarget, MCIL.GetSymbolFromOperand(CallTarget)); 859 CallOpcode = X86::CALL64pcrel32; 860 // Currently, we only support relative addressing with statepoints. 861 // Otherwise, we'll need a scratch register to hold the target 862 // address. You'll fail asserts during load & relocation if this 863 // symbol is to far away. (TODO: support non-relative addressing) 864 break; 865 case MachineOperand::MO_Immediate: 866 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); 867 CallOpcode = X86::CALL64pcrel32; 868 // Currently, we only support relative addressing with statepoints. 869 // Otherwise, we'll need a scratch register to hold the target 870 // immediate. You'll fail asserts during load & relocation if this 871 // address is to far away. (TODO: support non-relative addressing) 872 break; 873 case MachineOperand::MO_Register: 874 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); 875 CallOpcode = X86::CALL64r; 876 break; 877 default: 878 llvm_unreachable("Unsupported operand type in statepoint call target"); 879 break; 880 } 881 882 // Emit call 883 MCInst CallInst; 884 CallInst.setOpcode(CallOpcode); 885 CallInst.addOperand(CallTargetMCOp); 886 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo()); 887 } 888 889 // Record our statepoint node in the same section used by STACKMAP 890 // and PATCHPOINT 891 SM.recordStatepoint(MI); 892 } 893 894 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI, 895 X86MCInstLower &MCIL) { 896 // FAULTING_LOAD_OP <def>, <MBB handler>, <load opcode>, <load operands> 897 898 unsigned LoadDefRegister = MI.getOperand(0).getReg(); 899 MCSymbol *HandlerLabel = MI.getOperand(1).getMBB()->getSymbol(); 900 unsigned LoadOpcode = MI.getOperand(2).getImm(); 901 unsigned LoadOperandsBeginIdx = 3; 902 903 FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel); 904 905 MCInst LoadMI; 906 LoadMI.setOpcode(LoadOpcode); 907 908 if (LoadDefRegister != X86::NoRegister) 909 LoadMI.addOperand(MCOperand::createReg(LoadDefRegister)); 910 911 for (auto I = MI.operands_begin() + LoadOperandsBeginIdx, 912 E = MI.operands_end(); 913 I != E; ++I) 914 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I)) 915 LoadMI.addOperand(MaybeOperand.getValue()); 916 917 OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo()); 918 } 919 920 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, 921 X86MCInstLower &MCIL) { 922 // PATCHABLE_OP minsize, opcode, operands 923 924 unsigned MinSize = MI.getOperand(0).getImm(); 925 unsigned Opcode = MI.getOperand(1).getImm(); 926 927 MCInst MCI; 928 MCI.setOpcode(Opcode); 929 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end())) 930 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 931 MCI.addOperand(MaybeOperand.getValue()); 932 933 SmallString<256> Code; 934 SmallVector<MCFixup, 4> Fixups; 935 raw_svector_ostream VecOS(Code); 936 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo()); 937 938 if (Code.size() < MinSize) { 939 if (MinSize == 2 && Opcode == X86::PUSH64r) { 940 // This is an optimization that lets us get away without emitting a nop in 941 // many cases. 942 // 943 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two 944 // bytes too, so the check on MinSize is important. 945 MCI.setOpcode(X86::PUSH64rmr); 946 } else { 947 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(), 948 getSubtargetInfo()); 949 assert(NopSize == MinSize && "Could not implement MinSize!"); 950 (void) NopSize; 951 } 952 } 953 954 OutStreamer->EmitInstruction(MCI, getSubtargetInfo()); 955 } 956 957 // Lower a stackmap of the form: 958 // <id>, <shadowBytes>, ... 959 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { 960 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 961 SM.recordStackMap(MI); 962 unsigned NumShadowBytes = MI.getOperand(1).getImm(); 963 SMShadowTracker.reset(NumShadowBytes); 964 } 965 966 // Lower a patchpoint of the form: 967 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ... 968 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI, 969 X86MCInstLower &MCIL) { 970 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); 971 972 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 973 974 SM.recordPatchPoint(MI); 975 976 PatchPointOpers opers(&MI); 977 unsigned ScratchIdx = opers.getNextScratchIdx(); 978 unsigned EncodedBytes = 0; 979 const MachineOperand &CalleeMO = opers.getCallTarget(); 980 981 // Check for null target. If target is non-null (i.e. is non-zero or is 982 // symbolic) then emit a call. 983 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) { 984 MCOperand CalleeMCOp; 985 switch (CalleeMO.getType()) { 986 default: 987 /// FIXME: Add a verifier check for bad callee types. 988 llvm_unreachable("Unrecognized callee operand type."); 989 case MachineOperand::MO_Immediate: 990 if (CalleeMO.getImm()) 991 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm()); 992 break; 993 case MachineOperand::MO_ExternalSymbol: 994 case MachineOperand::MO_GlobalAddress: 995 CalleeMCOp = 996 MCIL.LowerSymbolOperand(CalleeMO, 997 MCIL.GetSymbolFromOperand(CalleeMO)); 998 break; 999 } 1000 1001 // Emit MOV to materialize the target address and the CALL to target. 1002 // This is encoded with 12-13 bytes, depending on which register is used. 1003 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg(); 1004 if (X86II::isX86_64ExtendedReg(ScratchReg)) 1005 EncodedBytes = 13; 1006 else 1007 EncodedBytes = 12; 1008 1009 EmitAndCountInstruction( 1010 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); 1011 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); 1012 } 1013 1014 // Emit padding. 1015 unsigned NumBytes = opers.getNumPatchBytes(); 1016 assert(NumBytes >= EncodedBytes && 1017 "Patchpoint can't request size less than the length of a call."); 1018 1019 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(), 1020 getSubtargetInfo()); 1021 } 1022 1023 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI, 1024 X86MCInstLower &MCIL) { 1025 // We want to emit the following pattern: 1026 // 1027 // .p2align 1, ... 1028 // .Lxray_sled_N: 1029 // jmp .tmpN 1030 // # 9 bytes worth of noops 1031 // .tmpN 1032 // 1033 // We need the 9 bytes because at runtime, we'd be patching over the full 11 1034 // bytes with the following pattern: 1035 // 1036 // mov %r10, <function id, 32-bit> // 6 bytes 1037 // call <relative offset, 32-bits> // 5 bytes 1038 // 1039 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1040 OutStreamer->EmitCodeAlignment(2); 1041 OutStreamer->EmitLabel(CurSled); 1042 auto Target = OutContext.createTempSymbol(); 1043 1044 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1045 // an operand (computed as an offset from the jmp instruction). 1046 // FIXME: Find another less hacky way do force the relative jump. 1047 OutStreamer->EmitBytes("\xeb\x09"); 1048 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1049 OutStreamer->EmitLabel(Target); 1050 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER); 1051 } 1052 1053 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI, 1054 X86MCInstLower &MCIL) { 1055 // Since PATCHABLE_RET takes the opcode of the return statement as an 1056 // argument, we use that to emit the correct form of the RET that we want. 1057 // i.e. when we see this: 1058 // 1059 // PATCHABLE_RET X86::RET ... 1060 // 1061 // We should emit the RET followed by sleds. 1062 // 1063 // .p2align 1, ... 1064 // .Lxray_sled_N: 1065 // ret # or equivalent instruction 1066 // # 10 bytes worth of noops 1067 // 1068 // This just makes sure that the alignment for the next instruction is 2. 1069 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1070 OutStreamer->EmitCodeAlignment(2); 1071 OutStreamer->EmitLabel(CurSled); 1072 unsigned OpCode = MI.getOperand(0).getImm(); 1073 MCInst Ret; 1074 Ret.setOpcode(OpCode); 1075 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1076 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1077 Ret.addOperand(MaybeOperand.getValue()); 1078 OutStreamer->EmitInstruction(Ret, getSubtargetInfo()); 1079 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo()); 1080 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT); 1081 } 1082 1083 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL) { 1084 // Like PATCHABLE_RET, we have the actual instruction in the operands to this 1085 // instruction so we lower that particular instruction and its operands. 1086 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how 1087 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to 1088 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual 1089 // tail call much like how we have it in PATCHABLE_RET. 1090 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1091 OutStreamer->EmitCodeAlignment(2); 1092 OutStreamer->EmitLabel(CurSled); 1093 auto Target = OutContext.createTempSymbol(); 1094 1095 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1096 // an operand (computed as an offset from the jmp instruction). 1097 // FIXME: Find another less hacky way do force the relative jump. 1098 OutStreamer->EmitBytes("\xeb\x09"); 1099 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1100 OutStreamer->EmitLabel(Target); 1101 recordSled(CurSled, MI, SledKind::TAIL_CALL); 1102 1103 unsigned OpCode = MI.getOperand(0).getImm(); 1104 MCInst TC; 1105 TC.setOpcode(OpCode); 1106 1107 // Before emitting the instruction, add a comment to indicate that this is 1108 // indeed a tail call. 1109 OutStreamer->AddComment("TAILCALL"); 1110 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1111 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1112 TC.addOperand(MaybeOperand.getValue()); 1113 OutStreamer->EmitInstruction(TC, getSubtargetInfo()); 1114 } 1115 1116 void X86AsmPrinter::EmitXRayTable() { 1117 if (Sleds.empty()) 1118 return; 1119 if (Subtarget->isTargetELF()) { 1120 auto PrevSection = OutStreamer->getCurrentSectionOnly(); 1121 auto Fn = MF->getFunction(); 1122 MCSection *Section = nullptr; 1123 if (Fn->hasComdat()) { 1124 Section = OutContext.getELFSection("xray_instr_map", ELF::SHT_PROGBITS, 1125 ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, 1126 Fn->getComdat()->getName()); 1127 } else { 1128 Section = OutContext.getELFSection("xray_instr_map", ELF::SHT_PROGBITS, 1129 ELF::SHF_ALLOC); 1130 } 1131 1132 // Before we switch over, we force a reference to a label inside the 1133 // xray_instr_map section. Since EmitXRayTable() is always called just 1134 // before the function's end, we assume that this is happening after the 1135 // last return instruction. 1136 // 1137 // We then align the reference to 16 byte boundaries, which we determined 1138 // experimentally to be beneficial to avoid causing decoder stalls. 1139 MCSymbol *Tmp = OutContext.createTempSymbol("xray_synthetic_", true); 1140 OutStreamer->EmitCodeAlignment(16); 1141 OutStreamer->EmitSymbolValue(Tmp, 8, false); 1142 OutStreamer->SwitchSection(Section); 1143 OutStreamer->EmitLabel(Tmp); 1144 for (const auto &Sled : Sleds) { 1145 OutStreamer->EmitSymbolValue(Sled.Sled, 8); 1146 OutStreamer->EmitSymbolValue(CurrentFnSym, 8); 1147 auto Kind = static_cast<uint8_t>(Sled.Kind); 1148 OutStreamer->EmitBytes( 1149 StringRef(reinterpret_cast<const char *>(&Kind), 1)); 1150 OutStreamer->EmitBytes( 1151 StringRef(reinterpret_cast<const char *>(&Sled.AlwaysInstrument), 1)); 1152 OutStreamer->EmitZeros(14); 1153 } 1154 OutStreamer->SwitchSection(PrevSection); 1155 } 1156 Sleds.clear(); 1157 } 1158 1159 // Returns instruction preceding MBBI in MachineFunction. 1160 // If MBBI is the first instruction of the first basic block, returns null. 1161 static MachineBasicBlock::const_iterator 1162 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) { 1163 const MachineBasicBlock *MBB = MBBI->getParent(); 1164 while (MBBI == MBB->begin()) { 1165 if (MBB == &MBB->getParent()->front()) 1166 return MachineBasicBlock::const_iterator(); 1167 MBB = MBB->getPrevNode(); 1168 MBBI = MBB->end(); 1169 } 1170 return --MBBI; 1171 } 1172 1173 static const Constant *getConstantFromPool(const MachineInstr &MI, 1174 const MachineOperand &Op) { 1175 if (!Op.isCPI()) 1176 return nullptr; 1177 1178 ArrayRef<MachineConstantPoolEntry> Constants = 1179 MI.getParent()->getParent()->getConstantPool()->getConstants(); 1180 const MachineConstantPoolEntry &ConstantEntry = 1181 Constants[Op.getIndex()]; 1182 1183 // Bail if this is a machine constant pool entry, we won't be able to dig out 1184 // anything useful. 1185 if (ConstantEntry.isMachineConstantPoolEntry()) 1186 return nullptr; 1187 1188 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal); 1189 assert((!C || ConstantEntry.getType() == C->getType()) && 1190 "Expected a constant of the same type!"); 1191 return C; 1192 } 1193 1194 static std::string getShuffleComment(const MachineInstr *MI, 1195 unsigned SrcOp1Idx, 1196 unsigned SrcOp2Idx, 1197 ArrayRef<int> Mask) { 1198 std::string Comment; 1199 1200 // Compute the name for a register. This is really goofy because we have 1201 // multiple instruction printers that could (in theory) use different 1202 // names. Fortunately most people use the ATT style (outside of Windows) 1203 // and they actually agree on register naming here. Ultimately, this is 1204 // a comment, and so its OK if it isn't perfect. 1205 auto GetRegisterName = [](unsigned RegNum) -> StringRef { 1206 return X86ATTInstPrinter::getRegisterName(RegNum); 1207 }; 1208 1209 const MachineOperand &DstOp = MI->getOperand(0); 1210 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); 1211 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); 1212 1213 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; 1214 StringRef Src1Name = 1215 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; 1216 StringRef Src2Name = 1217 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; 1218 1219 // One source operand, fix the mask to print all elements in one span. 1220 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end()); 1221 if (Src1Name == Src2Name) 1222 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) 1223 if (ShuffleMask[i] >= e) 1224 ShuffleMask[i] -= e; 1225 1226 raw_string_ostream CS(Comment); 1227 CS << DstName; 1228 1229 // Handle AVX512 MASK/MASXZ write mask comments. 1230 // MASK: zmmX {%kY} 1231 // MASKZ: zmmX {%kY} {z} 1232 if (SrcOp1Idx > 1) { 1233 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask"); 1234 1235 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1); 1236 if (WriteMaskOp.isReg()) { 1237 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}"; 1238 1239 if (SrcOp1Idx == 2) { 1240 CS << " {z}"; 1241 } 1242 } 1243 } 1244 1245 CS << " = "; 1246 1247 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) { 1248 if (i != 0) 1249 CS << ","; 1250 if (ShuffleMask[i] == SM_SentinelZero) { 1251 CS << "zero"; 1252 continue; 1253 } 1254 1255 // Otherwise, it must come from src1 or src2. Print the span of elements 1256 // that comes from this src. 1257 bool isSrc1 = ShuffleMask[i] < (int)e; 1258 CS << (isSrc1 ? Src1Name : Src2Name) << '['; 1259 1260 bool IsFirst = true; 1261 while (i != e && ShuffleMask[i] != SM_SentinelZero && 1262 (ShuffleMask[i] < (int)e) == isSrc1) { 1263 if (!IsFirst) 1264 CS << ','; 1265 else 1266 IsFirst = false; 1267 if (ShuffleMask[i] == SM_SentinelUndef) 1268 CS << "u"; 1269 else 1270 CS << ShuffleMask[i] % (int)e; 1271 ++i; 1272 } 1273 CS << ']'; 1274 --i; // For loop increments element #. 1275 } 1276 CS.flush(); 1277 1278 return Comment; 1279 } 1280 1281 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 1282 X86MCInstLower MCInstLowering(*MF, *this); 1283 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo(); 1284 1285 switch (MI->getOpcode()) { 1286 case TargetOpcode::DBG_VALUE: 1287 llvm_unreachable("Should be handled target independently"); 1288 1289 // Emit nothing here but a comment if we can. 1290 case X86::Int_MemBarrier: 1291 OutStreamer->emitRawComment("MEMBARRIER"); 1292 return; 1293 1294 1295 case X86::EH_RETURN: 1296 case X86::EH_RETURN64: { 1297 // Lower these as normal, but add some comments. 1298 unsigned Reg = MI->getOperand(0).getReg(); 1299 OutStreamer->AddComment(StringRef("eh_return, addr: %") + 1300 X86ATTInstPrinter::getRegisterName(Reg)); 1301 break; 1302 } 1303 case X86::CLEANUPRET: { 1304 // Lower these as normal, but add some comments. 1305 OutStreamer->AddComment("CLEANUPRET"); 1306 break; 1307 } 1308 1309 case X86::CATCHRET: { 1310 // Lower these as normal, but add some comments. 1311 OutStreamer->AddComment("CATCHRET"); 1312 break; 1313 } 1314 1315 case X86::TAILJMPr: 1316 case X86::TAILJMPm: 1317 case X86::TAILJMPd: 1318 case X86::TAILJMPd_CC: 1319 case X86::TAILJMPr64: 1320 case X86::TAILJMPm64: 1321 case X86::TAILJMPd64: 1322 case X86::TAILJMPd64_CC: 1323 case X86::TAILJMPr64_REX: 1324 case X86::TAILJMPm64_REX: 1325 // Lower these as normal, but add some comments. 1326 OutStreamer->AddComment("TAILCALL"); 1327 break; 1328 1329 case X86::TLS_addr32: 1330 case X86::TLS_addr64: 1331 case X86::TLS_base_addr32: 1332 case X86::TLS_base_addr64: 1333 return LowerTlsAddr(MCInstLowering, *MI); 1334 1335 case X86::MOVPC32r: { 1336 // This is a pseudo op for a two instruction sequence with a label, which 1337 // looks like: 1338 // call "L1$pb" 1339 // "L1$pb": 1340 // popl %esi 1341 1342 // Emit the call. 1343 MCSymbol *PICBase = MF->getPICBaseSymbol(); 1344 // FIXME: We would like an efficient form for this, so we don't have to do a 1345 // lot of extra uniquing. 1346 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32) 1347 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext))); 1348 1349 const X86FrameLowering* FrameLowering = 1350 MF->getSubtarget<X86Subtarget>().getFrameLowering(); 1351 bool hasFP = FrameLowering->hasFP(*MF); 1352 1353 // TODO: This is needed only if we require precise CFA. 1354 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() && 1355 !OutStreamer->getDwarfFrameInfos().back().End; 1356 1357 int stackGrowth = -RI->getSlotSize(); 1358 1359 if (HasActiveDwarfFrame && !hasFP) { 1360 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth); 1361 } 1362 1363 // Emit the label. 1364 OutStreamer->EmitLabel(PICBase); 1365 1366 // popl $reg 1367 EmitAndCountInstruction(MCInstBuilder(X86::POP32r) 1368 .addReg(MI->getOperand(0).getReg())); 1369 1370 if (HasActiveDwarfFrame && !hasFP) { 1371 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth); 1372 } 1373 return; 1374 } 1375 1376 case X86::ADD32ri: { 1377 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 1378 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 1379 break; 1380 1381 // Okay, we have something like: 1382 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 1383 1384 // For this, we want to print something like: 1385 // MYGLOBAL + (. - PICBASE) 1386 // However, we can't generate a ".", so just emit a new label here and refer 1387 // to it. 1388 MCSymbol *DotSym = OutContext.createTempSymbol(); 1389 OutStreamer->EmitLabel(DotSym); 1390 1391 // Now that we have emitted the label, lower the complex operand expression. 1392 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 1393 1394 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext); 1395 const MCExpr *PICBase = 1396 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext); 1397 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext); 1398 1399 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext), 1400 DotExpr, OutContext); 1401 1402 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri) 1403 .addReg(MI->getOperand(0).getReg()) 1404 .addReg(MI->getOperand(1).getReg()) 1405 .addExpr(DotExpr)); 1406 return; 1407 } 1408 case TargetOpcode::STATEPOINT: 1409 return LowerSTATEPOINT(*MI, MCInstLowering); 1410 1411 case TargetOpcode::FAULTING_LOAD_OP: 1412 return LowerFAULTING_LOAD_OP(*MI, MCInstLowering); 1413 1414 case TargetOpcode::PATCHABLE_OP: 1415 return LowerPATCHABLE_OP(*MI, MCInstLowering); 1416 1417 case TargetOpcode::STACKMAP: 1418 return LowerSTACKMAP(*MI); 1419 1420 case TargetOpcode::PATCHPOINT: 1421 return LowerPATCHPOINT(*MI, MCInstLowering); 1422 1423 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: 1424 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering); 1425 1426 case TargetOpcode::PATCHABLE_RET: 1427 return LowerPATCHABLE_RET(*MI, MCInstLowering); 1428 1429 case TargetOpcode::PATCHABLE_TAIL_CALL: 1430 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering); 1431 1432 case X86::MORESTACK_RET: 1433 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1434 return; 1435 1436 case X86::MORESTACK_RET_RESTORE_R10: 1437 // Return, then restore R10. 1438 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1439 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr) 1440 .addReg(X86::R10) 1441 .addReg(X86::RAX)); 1442 return; 1443 1444 case X86::SEH_PushReg: 1445 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1446 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm())); 1447 return; 1448 1449 case X86::SEH_SaveReg: 1450 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1451 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1452 MI->getOperand(1).getImm()); 1453 return; 1454 1455 case X86::SEH_SaveXMM: 1456 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1457 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1458 MI->getOperand(1).getImm()); 1459 return; 1460 1461 case X86::SEH_StackAlloc: 1462 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1463 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm()); 1464 return; 1465 1466 case X86::SEH_SetFrame: 1467 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1468 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1469 MI->getOperand(1).getImm()); 1470 return; 1471 1472 case X86::SEH_PushFrame: 1473 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1474 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm()); 1475 return; 1476 1477 case X86::SEH_EndPrologue: 1478 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1479 OutStreamer->EmitWinCFIEndProlog(); 1480 return; 1481 1482 case X86::SEH_Epilogue: { 1483 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1484 MachineBasicBlock::const_iterator MBBI(MI); 1485 // Check if preceded by a call and emit nop if so. 1486 for (MBBI = PrevCrossBBInst(MBBI); 1487 MBBI != MachineBasicBlock::const_iterator(); 1488 MBBI = PrevCrossBBInst(MBBI)) { 1489 // Conservatively assume that pseudo instructions don't emit code and keep 1490 // looking for a call. We may emit an unnecessary nop in some cases. 1491 if (!MBBI->isPseudo()) { 1492 if (MBBI->isCall()) 1493 EmitAndCountInstruction(MCInstBuilder(X86::NOOP)); 1494 break; 1495 } 1496 } 1497 return; 1498 } 1499 1500 // Lower PSHUFB and VPERMILP normally but add a comment if we can find 1501 // a constant shuffle mask. We won't be able to do this at the MC layer 1502 // because the mask isn't an immediate. 1503 case X86::PSHUFBrm: 1504 case X86::VPSHUFBrm: 1505 case X86::VPSHUFBYrm: 1506 case X86::VPSHUFBZ128rm: 1507 case X86::VPSHUFBZ128rmk: 1508 case X86::VPSHUFBZ128rmkz: 1509 case X86::VPSHUFBZ256rm: 1510 case X86::VPSHUFBZ256rmk: 1511 case X86::VPSHUFBZ256rmkz: 1512 case X86::VPSHUFBZrm: 1513 case X86::VPSHUFBZrmk: 1514 case X86::VPSHUFBZrmkz: { 1515 if (!OutStreamer->isVerboseAsm()) 1516 break; 1517 unsigned SrcIdx, MaskIdx; 1518 switch (MI->getOpcode()) { 1519 default: llvm_unreachable("Invalid opcode"); 1520 case X86::PSHUFBrm: 1521 case X86::VPSHUFBrm: 1522 case X86::VPSHUFBYrm: 1523 case X86::VPSHUFBZ128rm: 1524 case X86::VPSHUFBZ256rm: 1525 case X86::VPSHUFBZrm: 1526 SrcIdx = 1; MaskIdx = 5; break; 1527 case X86::VPSHUFBZ128rmkz: 1528 case X86::VPSHUFBZ256rmkz: 1529 case X86::VPSHUFBZrmkz: 1530 SrcIdx = 2; MaskIdx = 6; break; 1531 case X86::VPSHUFBZ128rmk: 1532 case X86::VPSHUFBZ256rmk: 1533 case X86::VPSHUFBZrmk: 1534 SrcIdx = 3; MaskIdx = 7; break; 1535 } 1536 1537 assert(MI->getNumOperands() >= 6 && 1538 "We should always have at least 6 operands!"); 1539 1540 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 1541 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1542 SmallVector<int, 16> Mask; 1543 DecodePSHUFBMask(C, Mask); 1544 if (!Mask.empty()) 1545 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 1546 } 1547 break; 1548 } 1549 1550 case X86::VPERMILPSrm: 1551 case X86::VPERMILPSYrm: 1552 case X86::VPERMILPSZ128rm: 1553 case X86::VPERMILPSZ128rmk: 1554 case X86::VPERMILPSZ128rmkz: 1555 case X86::VPERMILPSZ256rm: 1556 case X86::VPERMILPSZ256rmk: 1557 case X86::VPERMILPSZ256rmkz: 1558 case X86::VPERMILPSZrm: 1559 case X86::VPERMILPSZrmk: 1560 case X86::VPERMILPSZrmkz: 1561 case X86::VPERMILPDrm: 1562 case X86::VPERMILPDYrm: 1563 case X86::VPERMILPDZ128rm: 1564 case X86::VPERMILPDZ128rmk: 1565 case X86::VPERMILPDZ128rmkz: 1566 case X86::VPERMILPDZ256rm: 1567 case X86::VPERMILPDZ256rmk: 1568 case X86::VPERMILPDZ256rmkz: 1569 case X86::VPERMILPDZrm: 1570 case X86::VPERMILPDZrmk: 1571 case X86::VPERMILPDZrmkz: { 1572 if (!OutStreamer->isVerboseAsm()) 1573 break; 1574 unsigned SrcIdx, MaskIdx; 1575 unsigned ElSize; 1576 switch (MI->getOpcode()) { 1577 default: llvm_unreachable("Invalid opcode"); 1578 case X86::VPERMILPSrm: 1579 case X86::VPERMILPSYrm: 1580 case X86::VPERMILPSZ128rm: 1581 case X86::VPERMILPSZ256rm: 1582 case X86::VPERMILPSZrm: 1583 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; 1584 case X86::VPERMILPSZ128rmkz: 1585 case X86::VPERMILPSZ256rmkz: 1586 case X86::VPERMILPSZrmkz: 1587 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; 1588 case X86::VPERMILPSZ128rmk: 1589 case X86::VPERMILPSZ256rmk: 1590 case X86::VPERMILPSZrmk: 1591 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; 1592 case X86::VPERMILPDrm: 1593 case X86::VPERMILPDYrm: 1594 case X86::VPERMILPDZ128rm: 1595 case X86::VPERMILPDZ256rm: 1596 case X86::VPERMILPDZrm: 1597 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; 1598 case X86::VPERMILPDZ128rmkz: 1599 case X86::VPERMILPDZ256rmkz: 1600 case X86::VPERMILPDZrmkz: 1601 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break; 1602 case X86::VPERMILPDZ128rmk: 1603 case X86::VPERMILPDZ256rmk: 1604 case X86::VPERMILPDZrmk: 1605 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break; 1606 } 1607 1608 assert(MI->getNumOperands() >= 6 && 1609 "We should always have at least 6 operands!"); 1610 1611 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 1612 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1613 SmallVector<int, 16> Mask; 1614 DecodeVPERMILPMask(C, ElSize, Mask); 1615 if (!Mask.empty()) 1616 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 1617 } 1618 break; 1619 } 1620 1621 case X86::VPERMIL2PDrm: 1622 case X86::VPERMIL2PSrm: 1623 case X86::VPERMIL2PDrmY: 1624 case X86::VPERMIL2PSrmY: { 1625 if (!OutStreamer->isVerboseAsm()) 1626 break; 1627 assert(MI->getNumOperands() >= 8 && 1628 "We should always have at least 8 operands!"); 1629 1630 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); 1631 if (!CtrlOp.isImm()) 1632 break; 1633 1634 unsigned ElSize; 1635 switch (MI->getOpcode()) { 1636 default: llvm_unreachable("Invalid opcode"); 1637 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSrmY: ElSize = 32; break; 1638 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDrmY: ElSize = 64; break; 1639 } 1640 1641 const MachineOperand &MaskOp = MI->getOperand(6); 1642 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1643 SmallVector<int, 16> Mask; 1644 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask); 1645 if (!Mask.empty()) 1646 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 1647 } 1648 break; 1649 } 1650 1651 case X86::VPPERMrrm: { 1652 if (!OutStreamer->isVerboseAsm()) 1653 break; 1654 assert(MI->getNumOperands() >= 7 && 1655 "We should always have at least 7 operands!"); 1656 1657 const MachineOperand &MaskOp = MI->getOperand(6); 1658 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1659 SmallVector<int, 16> Mask; 1660 DecodeVPPERMMask(C, Mask); 1661 if (!Mask.empty()) 1662 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 1663 } 1664 break; 1665 } 1666 1667 #define MOV_CASE(Prefix, Suffix) \ 1668 case X86::Prefix##MOVAPD##Suffix##rm: \ 1669 case X86::Prefix##MOVAPS##Suffix##rm: \ 1670 case X86::Prefix##MOVUPD##Suffix##rm: \ 1671 case X86::Prefix##MOVUPS##Suffix##rm: \ 1672 case X86::Prefix##MOVDQA##Suffix##rm: \ 1673 case X86::Prefix##MOVDQU##Suffix##rm: 1674 1675 #define MOV_AVX512_CASE(Suffix) \ 1676 case X86::VMOVDQA64##Suffix##rm: \ 1677 case X86::VMOVDQA32##Suffix##rm: \ 1678 case X86::VMOVDQU64##Suffix##rm: \ 1679 case X86::VMOVDQU32##Suffix##rm: \ 1680 case X86::VMOVDQU16##Suffix##rm: \ 1681 case X86::VMOVDQU8##Suffix##rm: \ 1682 case X86::VMOVAPS##Suffix##rm: \ 1683 case X86::VMOVAPD##Suffix##rm: \ 1684 case X86::VMOVUPS##Suffix##rm: \ 1685 case X86::VMOVUPD##Suffix##rm: 1686 1687 #define CASE_ALL_MOV_RM() \ 1688 MOV_CASE(, ) /* SSE */ \ 1689 MOV_CASE(V, ) /* AVX-128 */ \ 1690 MOV_CASE(V, Y) /* AVX-256 */ \ 1691 MOV_AVX512_CASE(Z) \ 1692 MOV_AVX512_CASE(Z256) \ 1693 MOV_AVX512_CASE(Z128) 1694 1695 // For loads from a constant pool to a vector register, print the constant 1696 // loaded. 1697 CASE_ALL_MOV_RM() 1698 if (!OutStreamer->isVerboseAsm()) 1699 break; 1700 if (MI->getNumOperands() > 4) 1701 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 1702 std::string Comment; 1703 raw_string_ostream CS(Comment); 1704 const MachineOperand &DstOp = MI->getOperand(0); 1705 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 1706 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) { 1707 CS << "["; 1708 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) { 1709 if (i != 0) 1710 CS << ","; 1711 if (CDS->getElementType()->isIntegerTy()) 1712 CS << CDS->getElementAsInteger(i); 1713 else if (CDS->getElementType()->isFloatTy()) 1714 CS << CDS->getElementAsFloat(i); 1715 else if (CDS->getElementType()->isDoubleTy()) 1716 CS << CDS->getElementAsDouble(i); 1717 else 1718 CS << "?"; 1719 } 1720 CS << "]"; 1721 OutStreamer->AddComment(CS.str()); 1722 } else if (auto *CV = dyn_cast<ConstantVector>(C)) { 1723 CS << "<"; 1724 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) { 1725 if (i != 0) 1726 CS << ","; 1727 Constant *COp = CV->getOperand(i); 1728 if (isa<UndefValue>(COp)) { 1729 CS << "u"; 1730 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) { 1731 if (CI->getBitWidth() <= 64) { 1732 CS << CI->getZExtValue(); 1733 } else { 1734 // print multi-word constant as (w0,w1) 1735 const auto &Val = CI->getValue(); 1736 CS << "("; 1737 for (int i = 0, N = Val.getNumWords(); i < N; ++i) { 1738 if (i > 0) 1739 CS << ","; 1740 CS << Val.getRawData()[i]; 1741 } 1742 CS << ")"; 1743 } 1744 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) { 1745 SmallString<32> Str; 1746 CF->getValueAPF().toString(Str); 1747 CS << Str; 1748 } else { 1749 CS << "?"; 1750 } 1751 } 1752 CS << ">"; 1753 OutStreamer->AddComment(CS.str()); 1754 } 1755 } 1756 break; 1757 } 1758 1759 MCInst TmpInst; 1760 MCInstLowering.Lower(MI, TmpInst); 1761 1762 // Stackmap shadows cannot include branch targets, so we can count the bytes 1763 // in a call towards the shadow, but must ensure that the no thread returns 1764 // in to the stackmap shadow. The only way to achieve this is if the call 1765 // is at the end of the shadow. 1766 if (MI->isCall()) { 1767 // Count then size of the call towards the shadow 1768 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get()); 1769 // Then flush the shadow so that we fill with nops before the call, not 1770 // after it. 1771 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 1772 // Then emit the call 1773 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo()); 1774 return; 1775 } 1776 1777 EmitAndCountInstruction(TmpInst); 1778 } 1779