1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower X86 MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86AsmPrinter.h" 16 #include "X86RegisterInfo.h" 17 #include "X86ShuffleDecodeConstantPool.h" 18 #include "InstPrinter/X86ATTInstPrinter.h" 19 #include "MCTargetDesc/X86BaseInfo.h" 20 #include "Utils/X86ShuffleDecode.h" 21 #include "llvm/ADT/Optional.h" 22 #include "llvm/ADT/SmallString.h" 23 #include "llvm/ADT/iterator_range.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineConstantPool.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 28 #include "llvm/CodeGen/StackMaps.h" 29 #include "llvm/IR/DataLayout.h" 30 #include "llvm/IR/GlobalValue.h" 31 #include "llvm/IR/Mangler.h" 32 #include "llvm/MC/MCAsmInfo.h" 33 #include "llvm/MC/MCCodeEmitter.h" 34 #include "llvm/MC/MCContext.h" 35 #include "llvm/MC/MCExpr.h" 36 #include "llvm/MC/MCFixup.h" 37 #include "llvm/MC/MCInst.h" 38 #include "llvm/MC/MCInstBuilder.h" 39 #include "llvm/MC/MCSection.h" 40 #include "llvm/MC/MCStreamer.h" 41 #include "llvm/MC/MCSymbol.h" 42 #include "llvm/MC/MCSymbolELF.h" 43 #include "llvm/MC/MCSectionELF.h" 44 #include "llvm/MC/MCSectionMachO.h" 45 #include "llvm/Support/TargetRegistry.h" 46 #include "llvm/Support/ELF.h" 47 #include "llvm/Target/TargetLoweringObjectFile.h" 48 49 using namespace llvm; 50 51 namespace { 52 53 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 54 class X86MCInstLower { 55 MCContext &Ctx; 56 const MachineFunction &MF; 57 const TargetMachine &TM; 58 const MCAsmInfo &MAI; 59 X86AsmPrinter &AsmPrinter; 60 public: 61 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter); 62 63 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI, 64 const MachineOperand &MO) const; 65 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 66 67 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 68 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 69 70 private: 71 MachineModuleInfoMachO &getMachOMMI() const; 72 }; 73 74 } // end anonymous namespace 75 76 // Emit a minimal sequence of nops spanning NumBytes bytes. 77 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 78 const MCSubtargetInfo &STI); 79 80 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst, 81 const MCSubtargetInfo &STI, 82 MCCodeEmitter *CodeEmitter) { 83 if (InShadow) { 84 SmallString<256> Code; 85 SmallVector<MCFixup, 4> Fixups; 86 raw_svector_ostream VecOS(Code); 87 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI); 88 CurrentShadowSize += Code.size(); 89 if (CurrentShadowSize >= RequiredShadowSize) 90 InShadow = false; // The shadow is big enough. Stop counting. 91 } 92 } 93 94 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding( 95 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { 96 if (InShadow && CurrentShadowSize < RequiredShadowSize) { 97 InShadow = false; 98 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize, 99 MF->getSubtarget<X86Subtarget>().is64Bit(), STI); 100 } 101 } 102 103 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) { 104 OutStreamer->EmitInstruction(Inst, getSubtargetInfo()); 105 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get()); 106 } 107 108 X86MCInstLower::X86MCInstLower(const MachineFunction &mf, 109 X86AsmPrinter &asmprinter) 110 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()), 111 AsmPrinter(asmprinter) {} 112 113 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 114 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 115 } 116 117 118 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 119 /// operand to an MCSymbol. 120 MCSymbol *X86MCInstLower:: 121 GetSymbolFromOperand(const MachineOperand &MO) const { 122 const DataLayout &DL = MF.getDataLayout(); 123 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"); 124 125 MCSymbol *Sym = nullptr; 126 SmallString<128> Name; 127 StringRef Suffix; 128 129 switch (MO.getTargetFlags()) { 130 case X86II::MO_DLLIMPORT: 131 // Handle dllimport linkage. 132 Name += "__imp_"; 133 break; 134 case X86II::MO_DARWIN_NONLAZY: 135 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 136 Suffix = "$non_lazy_ptr"; 137 break; 138 } 139 140 if (!Suffix.empty()) 141 Name += DL.getPrivateGlobalPrefix(); 142 143 if (MO.isGlobal()) { 144 const GlobalValue *GV = MO.getGlobal(); 145 AsmPrinter.getNameWithPrefix(Name, GV); 146 } else if (MO.isSymbol()) { 147 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL); 148 } else if (MO.isMBB()) { 149 assert(Suffix.empty()); 150 Sym = MO.getMBB()->getSymbol(); 151 } 152 153 Name += Suffix; 154 if (!Sym) 155 Sym = Ctx.getOrCreateSymbol(Name); 156 157 // If the target flags on the operand changes the name of the symbol, do that 158 // before we return the symbol. 159 switch (MO.getTargetFlags()) { 160 default: break; 161 case X86II::MO_DARWIN_NONLAZY: 162 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 163 MachineModuleInfoImpl::StubValueTy &StubSym = 164 getMachOMMI().getGVStubEntry(Sym); 165 if (!StubSym.getPointer()) { 166 assert(MO.isGlobal() && "Extern symbol not handled yet"); 167 StubSym = 168 MachineModuleInfoImpl:: 169 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 170 !MO.getGlobal()->hasInternalLinkage()); 171 } 172 break; 173 } 174 } 175 176 return Sym; 177 } 178 179 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 180 MCSymbol *Sym) const { 181 // FIXME: We would like an efficient form for this, so we don't have to do a 182 // lot of extra uniquing. 183 const MCExpr *Expr = nullptr; 184 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 185 186 switch (MO.getTargetFlags()) { 187 default: llvm_unreachable("Unknown target flag on GV operand"); 188 case X86II::MO_NO_FLAG: // No flag. 189 // These affect the name of the symbol, not any suffix. 190 case X86II::MO_DARWIN_NONLAZY: 191 case X86II::MO_DLLIMPORT: 192 break; 193 194 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; 195 case X86II::MO_TLVP_PIC_BASE: 196 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 197 // Subtract the pic base. 198 Expr = MCBinaryExpr::createSub(Expr, 199 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), 200 Ctx), 201 Ctx); 202 break; 203 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break; 204 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 205 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break; 206 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break; 207 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 208 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 209 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 210 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break; 211 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 212 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break; 213 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 214 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 215 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 216 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 217 case X86II::MO_PIC_BASE_OFFSET: 218 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 219 Expr = MCSymbolRefExpr::create(Sym, Ctx); 220 // Subtract the pic base. 221 Expr = MCBinaryExpr::createSub(Expr, 222 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), 223 Ctx); 224 if (MO.isJTI()) { 225 assert(MAI.doesSetDirectiveSuppressReloc()); 226 // If .set directive is supported, use it to reduce the number of 227 // relocations the assembler will generate for differences between 228 // local labels. This is only safe when the symbols are in the same 229 // section so we are restricting it to jumptable references. 230 MCSymbol *Label = Ctx.createTempSymbol(); 231 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr); 232 Expr = MCSymbolRefExpr::create(Label, Ctx); 233 } 234 break; 235 } 236 237 if (!Expr) 238 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx); 239 240 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 241 Expr = MCBinaryExpr::createAdd(Expr, 242 MCConstantExpr::create(MO.getOffset(), Ctx), 243 Ctx); 244 return MCOperand::createExpr(Expr); 245 } 246 247 248 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 249 /// a short fixed-register form. 250 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 251 unsigned ImmOp = Inst.getNumOperands() - 1; 252 assert(Inst.getOperand(0).isReg() && 253 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 254 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 255 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 256 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 257 258 // Check whether the destination register can be fixed. 259 unsigned Reg = Inst.getOperand(0).getReg(); 260 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 261 return; 262 263 // If so, rewrite the instruction. 264 MCOperand Saved = Inst.getOperand(ImmOp); 265 Inst = MCInst(); 266 Inst.setOpcode(Opcode); 267 Inst.addOperand(Saved); 268 } 269 270 /// \brief If a movsx instruction has a shorter encoding for the used register 271 /// simplify the instruction to use it instead. 272 static void SimplifyMOVSX(MCInst &Inst) { 273 unsigned NewOpcode = 0; 274 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 275 switch (Inst.getOpcode()) { 276 default: 277 llvm_unreachable("Unexpected instruction!"); 278 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 279 if (Op0 == X86::AX && Op1 == X86::AL) 280 NewOpcode = X86::CBW; 281 break; 282 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 283 if (Op0 == X86::EAX && Op1 == X86::AX) 284 NewOpcode = X86::CWDE; 285 break; 286 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 287 if (Op0 == X86::RAX && Op1 == X86::EAX) 288 NewOpcode = X86::CDQE; 289 break; 290 } 291 292 if (NewOpcode != 0) { 293 Inst = MCInst(); 294 Inst.setOpcode(NewOpcode); 295 } 296 } 297 298 /// \brief Simplify things like MOV32rm to MOV32o32a. 299 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 300 unsigned Opcode) { 301 // Don't make these simplifications in 64-bit mode; other assemblers don't 302 // perform them because they make the code larger. 303 if (Printer.getSubtarget().is64Bit()) 304 return; 305 306 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 307 unsigned AddrBase = IsStore; 308 unsigned RegOp = IsStore ? 0 : 5; 309 unsigned AddrOp = AddrBase + 3; 310 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 311 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && 312 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && 313 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && 314 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && 315 (Inst.getOperand(AddrOp).isExpr() || 316 Inst.getOperand(AddrOp).isImm()) && 317 "Unexpected instruction!"); 318 319 // Check whether the destination register can be fixed. 320 unsigned Reg = Inst.getOperand(RegOp).getReg(); 321 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 322 return; 323 324 // Check whether this is an absolute address. 325 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 326 // to do this here. 327 bool Absolute = true; 328 if (Inst.getOperand(AddrOp).isExpr()) { 329 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 330 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 331 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 332 Absolute = false; 333 } 334 335 if (Absolute && 336 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || 337 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || 338 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) 339 return; 340 341 // If so, rewrite the instruction. 342 MCOperand Saved = Inst.getOperand(AddrOp); 343 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); 344 Inst = MCInst(); 345 Inst.setOpcode(Opcode); 346 Inst.addOperand(Saved); 347 Inst.addOperand(Seg); 348 } 349 350 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { 351 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 352 } 353 354 Optional<MCOperand> 355 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI, 356 const MachineOperand &MO) const { 357 switch (MO.getType()) { 358 default: 359 MI->dump(); 360 llvm_unreachable("unknown operand type"); 361 case MachineOperand::MO_Register: 362 // Ignore all implicit register operands. 363 if (MO.isImplicit()) 364 return None; 365 return MCOperand::createReg(MO.getReg()); 366 case MachineOperand::MO_Immediate: 367 return MCOperand::createImm(MO.getImm()); 368 case MachineOperand::MO_MachineBasicBlock: 369 case MachineOperand::MO_GlobalAddress: 370 case MachineOperand::MO_ExternalSymbol: 371 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 372 case MachineOperand::MO_MCSymbol: 373 return LowerSymbolOperand(MO, MO.getMCSymbol()); 374 case MachineOperand::MO_JumpTableIndex: 375 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 376 case MachineOperand::MO_ConstantPoolIndex: 377 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 378 case MachineOperand::MO_BlockAddress: 379 return LowerSymbolOperand( 380 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 381 case MachineOperand::MO_RegisterMask: 382 // Ignore call clobbers. 383 return None; 384 } 385 } 386 387 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 388 OutMI.setOpcode(MI->getOpcode()); 389 390 for (const MachineOperand &MO : MI->operands()) 391 if (auto MaybeMCOp = LowerMachineOperand(MI, MO)) 392 OutMI.addOperand(MaybeMCOp.getValue()); 393 394 // Handle a few special cases to eliminate operand modifiers. 395 ReSimplify: 396 switch (OutMI.getOpcode()) { 397 case X86::LEA64_32r: 398 case X86::LEA64r: 399 case X86::LEA16r: 400 case X86::LEA32r: 401 // LEA should have a segment register, but it must be empty. 402 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && 403 "Unexpected # of LEA operands"); 404 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && 405 "LEA has segment specified!"); 406 break; 407 408 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 409 // if one of the registers is extended, but other isn't. 410 case X86::VMOVZPQILo2PQIrr: 411 case X86::VMOVAPDrr: 412 case X86::VMOVAPDYrr: 413 case X86::VMOVAPSrr: 414 case X86::VMOVAPSYrr: 415 case X86::VMOVDQArr: 416 case X86::VMOVDQAYrr: 417 case X86::VMOVDQUrr: 418 case X86::VMOVDQUYrr: 419 case X86::VMOVUPDrr: 420 case X86::VMOVUPDYrr: 421 case X86::VMOVUPSrr: 422 case X86::VMOVUPSYrr: { 423 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 424 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 425 unsigned NewOpc; 426 switch (OutMI.getOpcode()) { 427 default: llvm_unreachable("Invalid opcode"); 428 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; 429 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 430 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 431 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 432 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 433 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 434 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 435 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 436 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 437 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 438 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 439 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 440 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 441 } 442 OutMI.setOpcode(NewOpc); 443 } 444 break; 445 } 446 case X86::VMOVSDrr: 447 case X86::VMOVSSrr: { 448 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 449 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 450 unsigned NewOpc; 451 switch (OutMI.getOpcode()) { 452 default: llvm_unreachable("Invalid opcode"); 453 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 454 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 455 } 456 OutMI.setOpcode(NewOpc); 457 } 458 break; 459 } 460 461 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 462 // inputs modeled as normal uses instead of implicit uses. As such, truncate 463 // off all but the first operand (the callee). FIXME: Change isel. 464 case X86::TAILJMPr64: 465 case X86::TAILJMPr64_REX: 466 case X86::CALL64r: 467 case X86::CALL64pcrel32: { 468 unsigned Opcode = OutMI.getOpcode(); 469 MCOperand Saved = OutMI.getOperand(0); 470 OutMI = MCInst(); 471 OutMI.setOpcode(Opcode); 472 OutMI.addOperand(Saved); 473 break; 474 } 475 476 case X86::EH_RETURN: 477 case X86::EH_RETURN64: { 478 OutMI = MCInst(); 479 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 480 break; 481 } 482 483 case X86::CLEANUPRET: { 484 // Replace CATCHRET with the appropriate RET. 485 OutMI = MCInst(); 486 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 487 break; 488 } 489 490 case X86::CATCHRET: { 491 // Replace CATCHRET with the appropriate RET. 492 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); 493 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 494 OutMI = MCInst(); 495 OutMI.setOpcode(getRetOpcode(Subtarget)); 496 OutMI.addOperand(MCOperand::createReg(ReturnReg)); 497 break; 498 } 499 500 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump instruction. 501 { unsigned Opcode; 502 case X86::TAILJMPr: Opcode = X86::JMP32r; goto SetTailJmpOpcode; 503 case X86::TAILJMPd: 504 case X86::TAILJMPd64: Opcode = X86::JMP_1; goto SetTailJmpOpcode; 505 case X86::TAILJMPd_CC: 506 case X86::TAILJMPd64_CC: 507 Opcode = X86::GetCondBranchFromCond( 508 static_cast<X86::CondCode>(MI->getOperand(1).getImm())); 509 goto SetTailJmpOpcode; 510 511 SetTailJmpOpcode: 512 MCOperand Saved = OutMI.getOperand(0); 513 OutMI = MCInst(); 514 OutMI.setOpcode(Opcode); 515 OutMI.addOperand(Saved); 516 break; 517 } 518 519 case X86::DEC16r: 520 case X86::DEC32r: 521 case X86::INC16r: 522 case X86::INC32r: 523 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions. 524 if (!AsmPrinter.getSubtarget().is64Bit()) { 525 unsigned Opcode; 526 switch (OutMI.getOpcode()) { 527 default: llvm_unreachable("Invalid opcode"); 528 case X86::DEC16r: Opcode = X86::DEC16r_alt; break; 529 case X86::DEC32r: Opcode = X86::DEC32r_alt; break; 530 case X86::INC16r: Opcode = X86::INC16r_alt; break; 531 case X86::INC32r: Opcode = X86::INC32r_alt; break; 532 } 533 OutMI.setOpcode(Opcode); 534 } 535 break; 536 537 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 538 // this with an ugly goto in case the resultant OR uses EAX and needs the 539 // short form. 540 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 541 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 542 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 543 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 544 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 545 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 546 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 547 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 548 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 549 550 // Atomic load and store require a separate pseudo-inst because Acquire 551 // implies mayStore and Release implies mayLoad; fix these to regular MOV 552 // instructions here 553 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; 554 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; 555 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; 556 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; 557 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; 558 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; 559 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; 560 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; 561 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify; 562 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify; 563 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify; 564 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify; 565 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify; 566 case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify; 567 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify; 568 case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify; 569 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify; 570 case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify; 571 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify; 572 case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify; 573 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify; 574 case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify; 575 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify; 576 case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify; 577 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify; 578 case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify; 579 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify; 580 case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify; 581 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify; 582 case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify; 583 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify; 584 case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify; 585 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify; 586 case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify; 587 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify; 588 case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify; 589 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify; 590 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify; 591 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify; 592 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify; 593 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify; 594 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify; 595 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify; 596 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify; 597 598 // We don't currently select the correct instruction form for instructions 599 // which have a short %eax, etc. form. Handle this by custom lowering, for 600 // now. 601 // 602 // Note, we are currently not handling the following instructions: 603 // MOV64ao8, MOV64o8a 604 // XCHG16ar, XCHG32ar, XCHG64ar 605 case X86::MOV8mr_NOREX: 606 case X86::MOV8mr: 607 case X86::MOV8rm_NOREX: 608 case X86::MOV8rm: 609 case X86::MOV16mr: 610 case X86::MOV16rm: 611 case X86::MOV32mr: 612 case X86::MOV32rm: { 613 unsigned NewOpc; 614 switch (OutMI.getOpcode()) { 615 default: llvm_unreachable("Invalid opcode"); 616 case X86::MOV8mr_NOREX: 617 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; 618 case X86::MOV8rm_NOREX: 619 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; 620 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; 621 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; 622 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break; 623 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break; 624 } 625 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc); 626 break; 627 } 628 629 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32: 630 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32: 631 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32: 632 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32: 633 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32: 634 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32: 635 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32: 636 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32: 637 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: { 638 unsigned NewOpc; 639 switch (OutMI.getOpcode()) { 640 default: llvm_unreachable("Invalid opcode"); 641 case X86::ADC8ri: NewOpc = X86::ADC8i8; break; 642 case X86::ADC16ri: NewOpc = X86::ADC16i16; break; 643 case X86::ADC32ri: NewOpc = X86::ADC32i32; break; 644 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break; 645 case X86::ADD8ri: NewOpc = X86::ADD8i8; break; 646 case X86::ADD16ri: NewOpc = X86::ADD16i16; break; 647 case X86::ADD32ri: NewOpc = X86::ADD32i32; break; 648 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break; 649 case X86::AND8ri: NewOpc = X86::AND8i8; break; 650 case X86::AND16ri: NewOpc = X86::AND16i16; break; 651 case X86::AND32ri: NewOpc = X86::AND32i32; break; 652 case X86::AND64ri32: NewOpc = X86::AND64i32; break; 653 case X86::CMP8ri: NewOpc = X86::CMP8i8; break; 654 case X86::CMP16ri: NewOpc = X86::CMP16i16; break; 655 case X86::CMP32ri: NewOpc = X86::CMP32i32; break; 656 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break; 657 case X86::OR8ri: NewOpc = X86::OR8i8; break; 658 case X86::OR16ri: NewOpc = X86::OR16i16; break; 659 case X86::OR32ri: NewOpc = X86::OR32i32; break; 660 case X86::OR64ri32: NewOpc = X86::OR64i32; break; 661 case X86::SBB8ri: NewOpc = X86::SBB8i8; break; 662 case X86::SBB16ri: NewOpc = X86::SBB16i16; break; 663 case X86::SBB32ri: NewOpc = X86::SBB32i32; break; 664 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break; 665 case X86::SUB8ri: NewOpc = X86::SUB8i8; break; 666 case X86::SUB16ri: NewOpc = X86::SUB16i16; break; 667 case X86::SUB32ri: NewOpc = X86::SUB32i32; break; 668 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break; 669 case X86::TEST8ri: NewOpc = X86::TEST8i8; break; 670 case X86::TEST16ri: NewOpc = X86::TEST16i16; break; 671 case X86::TEST32ri: NewOpc = X86::TEST32i32; break; 672 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break; 673 case X86::XOR8ri: NewOpc = X86::XOR8i8; break; 674 case X86::XOR16ri: NewOpc = X86::XOR16i16; break; 675 case X86::XOR32ri: NewOpc = X86::XOR32i32; break; 676 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break; 677 } 678 SimplifyShortImmForm(OutMI, NewOpc); 679 break; 680 } 681 682 // Try to shrink some forms of movsx. 683 case X86::MOVSX16rr8: 684 case X86::MOVSX32rr16: 685 case X86::MOVSX64rr32: 686 SimplifyMOVSX(OutMI); 687 break; 688 } 689 } 690 691 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering, 692 const MachineInstr &MI) { 693 694 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || 695 MI.getOpcode() == X86::TLS_base_addr64; 696 697 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; 698 699 MCContext &context = OutStreamer->getContext(); 700 701 if (needsPadding) 702 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 703 704 MCSymbolRefExpr::VariantKind SRVK; 705 switch (MI.getOpcode()) { 706 case X86::TLS_addr32: 707 case X86::TLS_addr64: 708 SRVK = MCSymbolRefExpr::VK_TLSGD; 709 break; 710 case X86::TLS_base_addr32: 711 SRVK = MCSymbolRefExpr::VK_TLSLDM; 712 break; 713 case X86::TLS_base_addr64: 714 SRVK = MCSymbolRefExpr::VK_TLSLD; 715 break; 716 default: 717 llvm_unreachable("unexpected opcode"); 718 } 719 720 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 721 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context); 722 723 MCInst LEA; 724 if (is64Bits) { 725 LEA.setOpcode(X86::LEA64r); 726 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest 727 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base 728 LEA.addOperand(MCOperand::createImm(1)); // scale 729 LEA.addOperand(MCOperand::createReg(0)); // index 730 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 731 LEA.addOperand(MCOperand::createReg(0)); // seg 732 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) { 733 LEA.setOpcode(X86::LEA32r); 734 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 735 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base 736 LEA.addOperand(MCOperand::createImm(1)); // scale 737 LEA.addOperand(MCOperand::createReg(0)); // index 738 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 739 LEA.addOperand(MCOperand::createReg(0)); // seg 740 } else { 741 LEA.setOpcode(X86::LEA32r); 742 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 743 LEA.addOperand(MCOperand::createReg(0)); // base 744 LEA.addOperand(MCOperand::createImm(1)); // scale 745 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index 746 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 747 LEA.addOperand(MCOperand::createReg(0)); // seg 748 } 749 EmitAndCountInstruction(LEA); 750 751 if (needsPadding) { 752 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 753 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 754 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX)); 755 } 756 757 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 758 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name); 759 const MCSymbolRefExpr *tlsRef = 760 MCSymbolRefExpr::create(tlsGetAddr, 761 MCSymbolRefExpr::VK_PLT, 762 context); 763 764 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 765 : X86::CALLpcrel32) 766 .addExpr(tlsRef)); 767 } 768 769 /// \brief Emit the largest nop instruction smaller than or equal to \p NumBytes 770 /// bytes. Return the size of nop emitted. 771 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 772 const MCSubtargetInfo &STI) { 773 // This works only for 64bit. For 32bit we have to do additional checking if 774 // the CPU supports multi-byte nops. 775 assert(Is64Bit && "EmitNops only supports X86-64"); 776 777 unsigned NopSize; 778 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; 779 Opc = IndexReg = Displacement = SegmentReg = 0; 780 BaseReg = X86::RAX; 781 ScaleVal = 1; 782 switch (NumBytes) { 783 case 0: llvm_unreachable("Zero nops?"); break; 784 case 1: NopSize = 1; Opc = X86::NOOP; break; 785 case 2: NopSize = 2; Opc = X86::XCHG16ar; break; 786 case 3: NopSize = 3; Opc = X86::NOOPL; break; 787 case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8; break; 788 case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8; 789 IndexReg = X86::RAX; break; 790 case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8; 791 IndexReg = X86::RAX; break; 792 case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512; break; 793 case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512; 794 IndexReg = X86::RAX; break; 795 case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512; 796 IndexReg = X86::RAX; break; 797 default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512; 798 IndexReg = X86::RAX; SegmentReg = X86::CS; break; 799 } 800 801 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U); 802 NopSize += NumPrefixes; 803 for (unsigned i = 0; i != NumPrefixes; ++i) 804 OS.EmitBytes("\x66"); 805 806 switch (Opc) { 807 default: 808 llvm_unreachable("Unexpected opcode"); 809 break; 810 case X86::NOOP: 811 OS.EmitInstruction(MCInstBuilder(Opc), STI); 812 break; 813 case X86::XCHG16ar: 814 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); 815 break; 816 case X86::NOOPL: 817 case X86::NOOPW: 818 OS.EmitInstruction(MCInstBuilder(Opc) 819 .addReg(BaseReg) 820 .addImm(ScaleVal) 821 .addReg(IndexReg) 822 .addImm(Displacement) 823 .addReg(SegmentReg), 824 STI); 825 break; 826 } 827 assert(NopSize <= NumBytes && "We overemitted?"); 828 return NopSize; 829 } 830 831 /// \brief Emit the optimal amount of multi-byte nops on X86. 832 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 833 const MCSubtargetInfo &STI) { 834 unsigned NopsToEmit = NumBytes; 835 (void)NopsToEmit; 836 while (NumBytes) { 837 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI); 838 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!"); 839 } 840 } 841 842 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI, 843 X86MCInstLower &MCIL) { 844 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); 845 846 StatepointOpers SOpers(&MI); 847 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) { 848 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(), 849 getSubtargetInfo()); 850 } else { 851 // Lower call target and choose correct opcode 852 const MachineOperand &CallTarget = SOpers.getCallTarget(); 853 MCOperand CallTargetMCOp; 854 unsigned CallOpcode; 855 switch (CallTarget.getType()) { 856 case MachineOperand::MO_GlobalAddress: 857 case MachineOperand::MO_ExternalSymbol: 858 CallTargetMCOp = MCIL.LowerSymbolOperand( 859 CallTarget, MCIL.GetSymbolFromOperand(CallTarget)); 860 CallOpcode = X86::CALL64pcrel32; 861 // Currently, we only support relative addressing with statepoints. 862 // Otherwise, we'll need a scratch register to hold the target 863 // address. You'll fail asserts during load & relocation if this 864 // symbol is to far away. (TODO: support non-relative addressing) 865 break; 866 case MachineOperand::MO_Immediate: 867 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); 868 CallOpcode = X86::CALL64pcrel32; 869 // Currently, we only support relative addressing with statepoints. 870 // Otherwise, we'll need a scratch register to hold the target 871 // immediate. You'll fail asserts during load & relocation if this 872 // address is to far away. (TODO: support non-relative addressing) 873 break; 874 case MachineOperand::MO_Register: 875 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); 876 CallOpcode = X86::CALL64r; 877 break; 878 default: 879 llvm_unreachable("Unsupported operand type in statepoint call target"); 880 break; 881 } 882 883 // Emit call 884 MCInst CallInst; 885 CallInst.setOpcode(CallOpcode); 886 CallInst.addOperand(CallTargetMCOp); 887 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo()); 888 } 889 890 // Record our statepoint node in the same section used by STACKMAP 891 // and PATCHPOINT 892 SM.recordStatepoint(MI); 893 } 894 895 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI, 896 X86MCInstLower &MCIL) { 897 // FAULTING_LOAD_OP <def>, <MBB handler>, <load opcode>, <load operands> 898 899 unsigned LoadDefRegister = MI.getOperand(0).getReg(); 900 MCSymbol *HandlerLabel = MI.getOperand(1).getMBB()->getSymbol(); 901 unsigned LoadOpcode = MI.getOperand(2).getImm(); 902 unsigned LoadOperandsBeginIdx = 3; 903 904 FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel); 905 906 MCInst LoadMI; 907 LoadMI.setOpcode(LoadOpcode); 908 909 if (LoadDefRegister != X86::NoRegister) 910 LoadMI.addOperand(MCOperand::createReg(LoadDefRegister)); 911 912 for (auto I = MI.operands_begin() + LoadOperandsBeginIdx, 913 E = MI.operands_end(); 914 I != E; ++I) 915 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I)) 916 LoadMI.addOperand(MaybeOperand.getValue()); 917 918 OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo()); 919 } 920 921 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, 922 X86MCInstLower &MCIL) { 923 // PATCHABLE_OP minsize, opcode, operands 924 925 unsigned MinSize = MI.getOperand(0).getImm(); 926 unsigned Opcode = MI.getOperand(1).getImm(); 927 928 MCInst MCI; 929 MCI.setOpcode(Opcode); 930 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end())) 931 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 932 MCI.addOperand(MaybeOperand.getValue()); 933 934 SmallString<256> Code; 935 SmallVector<MCFixup, 4> Fixups; 936 raw_svector_ostream VecOS(Code); 937 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo()); 938 939 if (Code.size() < MinSize) { 940 if (MinSize == 2 && Opcode == X86::PUSH64r) { 941 // This is an optimization that lets us get away without emitting a nop in 942 // many cases. 943 // 944 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two 945 // bytes too, so the check on MinSize is important. 946 MCI.setOpcode(X86::PUSH64rmr); 947 } else { 948 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(), 949 getSubtargetInfo()); 950 assert(NopSize == MinSize && "Could not implement MinSize!"); 951 (void) NopSize; 952 } 953 } 954 955 OutStreamer->EmitInstruction(MCI, getSubtargetInfo()); 956 } 957 958 // Lower a stackmap of the form: 959 // <id>, <shadowBytes>, ... 960 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { 961 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 962 SM.recordStackMap(MI); 963 unsigned NumShadowBytes = MI.getOperand(1).getImm(); 964 SMShadowTracker.reset(NumShadowBytes); 965 } 966 967 // Lower a patchpoint of the form: 968 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ... 969 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI, 970 X86MCInstLower &MCIL) { 971 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); 972 973 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 974 975 SM.recordPatchPoint(MI); 976 977 PatchPointOpers opers(&MI); 978 unsigned ScratchIdx = opers.getNextScratchIdx(); 979 unsigned EncodedBytes = 0; 980 const MachineOperand &CalleeMO = opers.getCallTarget(); 981 982 // Check for null target. If target is non-null (i.e. is non-zero or is 983 // symbolic) then emit a call. 984 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) { 985 MCOperand CalleeMCOp; 986 switch (CalleeMO.getType()) { 987 default: 988 /// FIXME: Add a verifier check for bad callee types. 989 llvm_unreachable("Unrecognized callee operand type."); 990 case MachineOperand::MO_Immediate: 991 if (CalleeMO.getImm()) 992 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm()); 993 break; 994 case MachineOperand::MO_ExternalSymbol: 995 case MachineOperand::MO_GlobalAddress: 996 CalleeMCOp = 997 MCIL.LowerSymbolOperand(CalleeMO, 998 MCIL.GetSymbolFromOperand(CalleeMO)); 999 break; 1000 } 1001 1002 // Emit MOV to materialize the target address and the CALL to target. 1003 // This is encoded with 12-13 bytes, depending on which register is used. 1004 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg(); 1005 if (X86II::isX86_64ExtendedReg(ScratchReg)) 1006 EncodedBytes = 13; 1007 else 1008 EncodedBytes = 12; 1009 1010 EmitAndCountInstruction( 1011 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); 1012 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); 1013 } 1014 1015 // Emit padding. 1016 unsigned NumBytes = opers.getNumPatchBytes(); 1017 assert(NumBytes >= EncodedBytes && 1018 "Patchpoint can't request size less than the length of a call."); 1019 1020 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(), 1021 getSubtargetInfo()); 1022 } 1023 1024 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI, 1025 X86MCInstLower &MCIL) { 1026 // We want to emit the following pattern: 1027 // 1028 // .p2align 1, ... 1029 // .Lxray_sled_N: 1030 // jmp .tmpN 1031 // # 9 bytes worth of noops 1032 // .tmpN 1033 // 1034 // We need the 9 bytes because at runtime, we'd be patching over the full 11 1035 // bytes with the following pattern: 1036 // 1037 // mov %r10, <function id, 32-bit> // 6 bytes 1038 // call <relative offset, 32-bits> // 5 bytes 1039 // 1040 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1041 OutStreamer->EmitCodeAlignment(2); 1042 OutStreamer->EmitLabel(CurSled); 1043 auto Target = OutContext.createTempSymbol(); 1044 1045 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1046 // an operand (computed as an offset from the jmp instruction). 1047 // FIXME: Find another less hacky way do force the relative jump. 1048 OutStreamer->EmitBytes("\xeb\x09"); 1049 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1050 OutStreamer->EmitLabel(Target); 1051 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER); 1052 } 1053 1054 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI, 1055 X86MCInstLower &MCIL) { 1056 // Since PATCHABLE_RET takes the opcode of the return statement as an 1057 // argument, we use that to emit the correct form of the RET that we want. 1058 // i.e. when we see this: 1059 // 1060 // PATCHABLE_RET X86::RET ... 1061 // 1062 // We should emit the RET followed by sleds. 1063 // 1064 // .p2align 1, ... 1065 // .Lxray_sled_N: 1066 // ret # or equivalent instruction 1067 // # 10 bytes worth of noops 1068 // 1069 // This just makes sure that the alignment for the next instruction is 2. 1070 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1071 OutStreamer->EmitCodeAlignment(2); 1072 OutStreamer->EmitLabel(CurSled); 1073 unsigned OpCode = MI.getOperand(0).getImm(); 1074 MCInst Ret; 1075 Ret.setOpcode(OpCode); 1076 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1077 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1078 Ret.addOperand(MaybeOperand.getValue()); 1079 OutStreamer->EmitInstruction(Ret, getSubtargetInfo()); 1080 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo()); 1081 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT); 1082 } 1083 1084 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL) { 1085 // Like PATCHABLE_RET, we have the actual instruction in the operands to this 1086 // instruction so we lower that particular instruction and its operands. 1087 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how 1088 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to 1089 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual 1090 // tail call much like how we have it in PATCHABLE_RET. 1091 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1092 OutStreamer->EmitCodeAlignment(2); 1093 OutStreamer->EmitLabel(CurSled); 1094 auto Target = OutContext.createTempSymbol(); 1095 1096 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1097 // an operand (computed as an offset from the jmp instruction). 1098 // FIXME: Find another less hacky way do force the relative jump. 1099 OutStreamer->EmitBytes("\xeb\x09"); 1100 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1101 OutStreamer->EmitLabel(Target); 1102 recordSled(CurSled, MI, SledKind::TAIL_CALL); 1103 1104 unsigned OpCode = MI.getOperand(0).getImm(); 1105 MCInst TC; 1106 TC.setOpcode(OpCode); 1107 1108 // Before emitting the instruction, add a comment to indicate that this is 1109 // indeed a tail call. 1110 OutStreamer->AddComment("TAILCALL"); 1111 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1112 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1113 TC.addOperand(MaybeOperand.getValue()); 1114 OutStreamer->EmitInstruction(TC, getSubtargetInfo()); 1115 } 1116 1117 void X86AsmPrinter::EmitXRayTable() { 1118 if (Sleds.empty()) 1119 return; 1120 1121 auto PrevSection = OutStreamer->getCurrentSectionOnly(); 1122 auto Fn = MF->getFunction(); 1123 MCSection *Section = nullptr; 1124 if (Subtarget->isTargetELF()) { 1125 if (Fn->hasComdat()) { 1126 Section = OutContext.getELFSection("xray_instr_map", ELF::SHT_PROGBITS, 1127 ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, 1128 Fn->getComdat()->getName()); 1129 } else { 1130 Section = OutContext.getELFSection("xray_instr_map", ELF::SHT_PROGBITS, 1131 ELF::SHF_ALLOC); 1132 } 1133 } else if (Subtarget->isTargetMachO()) { 1134 Section = OutContext.getMachOSection("__DATA", "xray_instr_map", 0, 1135 SectionKind::getReadOnlyWithRel()); 1136 } else { 1137 llvm_unreachable("Unsupported target"); 1138 } 1139 1140 // Before we switch over, we force a reference to a label inside the 1141 // xray_instr_map section. Since EmitXRayTable() is always called just 1142 // before the function's end, we assume that this is happening after the 1143 // last return instruction. 1144 // 1145 // We then align the reference to 16 byte boundaries, which we determined 1146 // experimentally to be beneficial to avoid causing decoder stalls. 1147 MCSymbol *Tmp = OutContext.createTempSymbol("xray_synthetic_", true); 1148 OutStreamer->EmitCodeAlignment(16); 1149 OutStreamer->EmitSymbolValue(Tmp, 8, false); 1150 OutStreamer->SwitchSection(Section); 1151 OutStreamer->EmitLabel(Tmp); 1152 for (const auto &Sled : Sleds) { 1153 OutStreamer->EmitSymbolValue(Sled.Sled, 8); 1154 OutStreamer->EmitSymbolValue(CurrentFnSym, 8); 1155 auto Kind = static_cast<uint8_t>(Sled.Kind); 1156 OutStreamer->EmitBytes( 1157 StringRef(reinterpret_cast<const char *>(&Kind), 1)); 1158 OutStreamer->EmitBytes( 1159 StringRef(reinterpret_cast<const char *>(&Sled.AlwaysInstrument), 1)); 1160 OutStreamer->EmitZeros(14); 1161 } 1162 OutStreamer->SwitchSection(PrevSection); 1163 1164 Sleds.clear(); 1165 } 1166 1167 // Returns instruction preceding MBBI in MachineFunction. 1168 // If MBBI is the first instruction of the first basic block, returns null. 1169 static MachineBasicBlock::const_iterator 1170 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) { 1171 const MachineBasicBlock *MBB = MBBI->getParent(); 1172 while (MBBI == MBB->begin()) { 1173 if (MBB == &MBB->getParent()->front()) 1174 return MachineBasicBlock::const_iterator(); 1175 MBB = MBB->getPrevNode(); 1176 MBBI = MBB->end(); 1177 } 1178 return --MBBI; 1179 } 1180 1181 static const Constant *getConstantFromPool(const MachineInstr &MI, 1182 const MachineOperand &Op) { 1183 if (!Op.isCPI()) 1184 return nullptr; 1185 1186 ArrayRef<MachineConstantPoolEntry> Constants = 1187 MI.getParent()->getParent()->getConstantPool()->getConstants(); 1188 const MachineConstantPoolEntry &ConstantEntry = 1189 Constants[Op.getIndex()]; 1190 1191 // Bail if this is a machine constant pool entry, we won't be able to dig out 1192 // anything useful. 1193 if (ConstantEntry.isMachineConstantPoolEntry()) 1194 return nullptr; 1195 1196 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal); 1197 assert((!C || ConstantEntry.getType() == C->getType()) && 1198 "Expected a constant of the same type!"); 1199 return C; 1200 } 1201 1202 static std::string getShuffleComment(const MachineInstr *MI, 1203 unsigned SrcOp1Idx, 1204 unsigned SrcOp2Idx, 1205 ArrayRef<int> Mask) { 1206 std::string Comment; 1207 1208 // Compute the name for a register. This is really goofy because we have 1209 // multiple instruction printers that could (in theory) use different 1210 // names. Fortunately most people use the ATT style (outside of Windows) 1211 // and they actually agree on register naming here. Ultimately, this is 1212 // a comment, and so its OK if it isn't perfect. 1213 auto GetRegisterName = [](unsigned RegNum) -> StringRef { 1214 return X86ATTInstPrinter::getRegisterName(RegNum); 1215 }; 1216 1217 const MachineOperand &DstOp = MI->getOperand(0); 1218 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); 1219 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); 1220 1221 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; 1222 StringRef Src1Name = 1223 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; 1224 StringRef Src2Name = 1225 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; 1226 1227 // One source operand, fix the mask to print all elements in one span. 1228 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end()); 1229 if (Src1Name == Src2Name) 1230 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) 1231 if (ShuffleMask[i] >= e) 1232 ShuffleMask[i] -= e; 1233 1234 raw_string_ostream CS(Comment); 1235 CS << DstName; 1236 1237 // Handle AVX512 MASK/MASXZ write mask comments. 1238 // MASK: zmmX {%kY} 1239 // MASKZ: zmmX {%kY} {z} 1240 if (SrcOp1Idx > 1) { 1241 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask"); 1242 1243 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1); 1244 if (WriteMaskOp.isReg()) { 1245 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}"; 1246 1247 if (SrcOp1Idx == 2) { 1248 CS << " {z}"; 1249 } 1250 } 1251 } 1252 1253 CS << " = "; 1254 1255 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) { 1256 if (i != 0) 1257 CS << ","; 1258 if (ShuffleMask[i] == SM_SentinelZero) { 1259 CS << "zero"; 1260 continue; 1261 } 1262 1263 // Otherwise, it must come from src1 or src2. Print the span of elements 1264 // that comes from this src. 1265 bool isSrc1 = ShuffleMask[i] < (int)e; 1266 CS << (isSrc1 ? Src1Name : Src2Name) << '['; 1267 1268 bool IsFirst = true; 1269 while (i != e && ShuffleMask[i] != SM_SentinelZero && 1270 (ShuffleMask[i] < (int)e) == isSrc1) { 1271 if (!IsFirst) 1272 CS << ','; 1273 else 1274 IsFirst = false; 1275 if (ShuffleMask[i] == SM_SentinelUndef) 1276 CS << "u"; 1277 else 1278 CS << ShuffleMask[i] % (int)e; 1279 ++i; 1280 } 1281 CS << ']'; 1282 --i; // For loop increments element #. 1283 } 1284 CS.flush(); 1285 1286 return Comment; 1287 } 1288 1289 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 1290 X86MCInstLower MCInstLowering(*MF, *this); 1291 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo(); 1292 1293 switch (MI->getOpcode()) { 1294 case TargetOpcode::DBG_VALUE: 1295 llvm_unreachable("Should be handled target independently"); 1296 1297 // Emit nothing here but a comment if we can. 1298 case X86::Int_MemBarrier: 1299 OutStreamer->emitRawComment("MEMBARRIER"); 1300 return; 1301 1302 1303 case X86::EH_RETURN: 1304 case X86::EH_RETURN64: { 1305 // Lower these as normal, but add some comments. 1306 unsigned Reg = MI->getOperand(0).getReg(); 1307 OutStreamer->AddComment(StringRef("eh_return, addr: %") + 1308 X86ATTInstPrinter::getRegisterName(Reg)); 1309 break; 1310 } 1311 case X86::CLEANUPRET: { 1312 // Lower these as normal, but add some comments. 1313 OutStreamer->AddComment("CLEANUPRET"); 1314 break; 1315 } 1316 1317 case X86::CATCHRET: { 1318 // Lower these as normal, but add some comments. 1319 OutStreamer->AddComment("CATCHRET"); 1320 break; 1321 } 1322 1323 case X86::TAILJMPr: 1324 case X86::TAILJMPm: 1325 case X86::TAILJMPd: 1326 case X86::TAILJMPd_CC: 1327 case X86::TAILJMPr64: 1328 case X86::TAILJMPm64: 1329 case X86::TAILJMPd64: 1330 case X86::TAILJMPd64_CC: 1331 case X86::TAILJMPr64_REX: 1332 case X86::TAILJMPm64_REX: 1333 // Lower these as normal, but add some comments. 1334 OutStreamer->AddComment("TAILCALL"); 1335 break; 1336 1337 case X86::TLS_addr32: 1338 case X86::TLS_addr64: 1339 case X86::TLS_base_addr32: 1340 case X86::TLS_base_addr64: 1341 return LowerTlsAddr(MCInstLowering, *MI); 1342 1343 case X86::MOVPC32r: { 1344 // This is a pseudo op for a two instruction sequence with a label, which 1345 // looks like: 1346 // call "L1$pb" 1347 // "L1$pb": 1348 // popl %esi 1349 1350 // Emit the call. 1351 MCSymbol *PICBase = MF->getPICBaseSymbol(); 1352 // FIXME: We would like an efficient form for this, so we don't have to do a 1353 // lot of extra uniquing. 1354 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32) 1355 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext))); 1356 1357 const X86FrameLowering* FrameLowering = 1358 MF->getSubtarget<X86Subtarget>().getFrameLowering(); 1359 bool hasFP = FrameLowering->hasFP(*MF); 1360 1361 // TODO: This is needed only if we require precise CFA. 1362 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() && 1363 !OutStreamer->getDwarfFrameInfos().back().End; 1364 1365 int stackGrowth = -RI->getSlotSize(); 1366 1367 if (HasActiveDwarfFrame && !hasFP) { 1368 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth); 1369 } 1370 1371 // Emit the label. 1372 OutStreamer->EmitLabel(PICBase); 1373 1374 // popl $reg 1375 EmitAndCountInstruction(MCInstBuilder(X86::POP32r) 1376 .addReg(MI->getOperand(0).getReg())); 1377 1378 if (HasActiveDwarfFrame && !hasFP) { 1379 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth); 1380 } 1381 return; 1382 } 1383 1384 case X86::ADD32ri: { 1385 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 1386 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 1387 break; 1388 1389 // Okay, we have something like: 1390 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 1391 1392 // For this, we want to print something like: 1393 // MYGLOBAL + (. - PICBASE) 1394 // However, we can't generate a ".", so just emit a new label here and refer 1395 // to it. 1396 MCSymbol *DotSym = OutContext.createTempSymbol(); 1397 OutStreamer->EmitLabel(DotSym); 1398 1399 // Now that we have emitted the label, lower the complex operand expression. 1400 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 1401 1402 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext); 1403 const MCExpr *PICBase = 1404 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext); 1405 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext); 1406 1407 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext), 1408 DotExpr, OutContext); 1409 1410 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri) 1411 .addReg(MI->getOperand(0).getReg()) 1412 .addReg(MI->getOperand(1).getReg()) 1413 .addExpr(DotExpr)); 1414 return; 1415 } 1416 case TargetOpcode::STATEPOINT: 1417 return LowerSTATEPOINT(*MI, MCInstLowering); 1418 1419 case TargetOpcode::FAULTING_LOAD_OP: 1420 return LowerFAULTING_LOAD_OP(*MI, MCInstLowering); 1421 1422 case TargetOpcode::PATCHABLE_OP: 1423 return LowerPATCHABLE_OP(*MI, MCInstLowering); 1424 1425 case TargetOpcode::STACKMAP: 1426 return LowerSTACKMAP(*MI); 1427 1428 case TargetOpcode::PATCHPOINT: 1429 return LowerPATCHPOINT(*MI, MCInstLowering); 1430 1431 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: 1432 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering); 1433 1434 case TargetOpcode::PATCHABLE_RET: 1435 return LowerPATCHABLE_RET(*MI, MCInstLowering); 1436 1437 case TargetOpcode::PATCHABLE_TAIL_CALL: 1438 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering); 1439 1440 case X86::MORESTACK_RET: 1441 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1442 return; 1443 1444 case X86::MORESTACK_RET_RESTORE_R10: 1445 // Return, then restore R10. 1446 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1447 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr) 1448 .addReg(X86::R10) 1449 .addReg(X86::RAX)); 1450 return; 1451 1452 case X86::SEH_PushReg: 1453 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1454 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm())); 1455 return; 1456 1457 case X86::SEH_SaveReg: 1458 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1459 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1460 MI->getOperand(1).getImm()); 1461 return; 1462 1463 case X86::SEH_SaveXMM: 1464 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1465 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1466 MI->getOperand(1).getImm()); 1467 return; 1468 1469 case X86::SEH_StackAlloc: 1470 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1471 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm()); 1472 return; 1473 1474 case X86::SEH_SetFrame: 1475 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1476 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1477 MI->getOperand(1).getImm()); 1478 return; 1479 1480 case X86::SEH_PushFrame: 1481 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1482 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm()); 1483 return; 1484 1485 case X86::SEH_EndPrologue: 1486 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1487 OutStreamer->EmitWinCFIEndProlog(); 1488 return; 1489 1490 case X86::SEH_Epilogue: { 1491 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1492 MachineBasicBlock::const_iterator MBBI(MI); 1493 // Check if preceded by a call and emit nop if so. 1494 for (MBBI = PrevCrossBBInst(MBBI); 1495 MBBI != MachineBasicBlock::const_iterator(); 1496 MBBI = PrevCrossBBInst(MBBI)) { 1497 // Conservatively assume that pseudo instructions don't emit code and keep 1498 // looking for a call. We may emit an unnecessary nop in some cases. 1499 if (!MBBI->isPseudo()) { 1500 if (MBBI->isCall()) 1501 EmitAndCountInstruction(MCInstBuilder(X86::NOOP)); 1502 break; 1503 } 1504 } 1505 return; 1506 } 1507 1508 // Lower PSHUFB and VPERMILP normally but add a comment if we can find 1509 // a constant shuffle mask. We won't be able to do this at the MC layer 1510 // because the mask isn't an immediate. 1511 case X86::PSHUFBrm: 1512 case X86::VPSHUFBrm: 1513 case X86::VPSHUFBYrm: 1514 case X86::VPSHUFBZ128rm: 1515 case X86::VPSHUFBZ128rmk: 1516 case X86::VPSHUFBZ128rmkz: 1517 case X86::VPSHUFBZ256rm: 1518 case X86::VPSHUFBZ256rmk: 1519 case X86::VPSHUFBZ256rmkz: 1520 case X86::VPSHUFBZrm: 1521 case X86::VPSHUFBZrmk: 1522 case X86::VPSHUFBZrmkz: { 1523 if (!OutStreamer->isVerboseAsm()) 1524 break; 1525 unsigned SrcIdx, MaskIdx; 1526 switch (MI->getOpcode()) { 1527 default: llvm_unreachable("Invalid opcode"); 1528 case X86::PSHUFBrm: 1529 case X86::VPSHUFBrm: 1530 case X86::VPSHUFBYrm: 1531 case X86::VPSHUFBZ128rm: 1532 case X86::VPSHUFBZ256rm: 1533 case X86::VPSHUFBZrm: 1534 SrcIdx = 1; MaskIdx = 5; break; 1535 case X86::VPSHUFBZ128rmkz: 1536 case X86::VPSHUFBZ256rmkz: 1537 case X86::VPSHUFBZrmkz: 1538 SrcIdx = 2; MaskIdx = 6; break; 1539 case X86::VPSHUFBZ128rmk: 1540 case X86::VPSHUFBZ256rmk: 1541 case X86::VPSHUFBZrmk: 1542 SrcIdx = 3; MaskIdx = 7; break; 1543 } 1544 1545 assert(MI->getNumOperands() >= 6 && 1546 "We should always have at least 6 operands!"); 1547 1548 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 1549 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1550 SmallVector<int, 64> Mask; 1551 DecodePSHUFBMask(C, Mask); 1552 if (!Mask.empty()) 1553 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 1554 } 1555 break; 1556 } 1557 1558 case X86::VPERMILPSrm: 1559 case X86::VPERMILPSYrm: 1560 case X86::VPERMILPSZ128rm: 1561 case X86::VPERMILPSZ128rmk: 1562 case X86::VPERMILPSZ128rmkz: 1563 case X86::VPERMILPSZ256rm: 1564 case X86::VPERMILPSZ256rmk: 1565 case X86::VPERMILPSZ256rmkz: 1566 case X86::VPERMILPSZrm: 1567 case X86::VPERMILPSZrmk: 1568 case X86::VPERMILPSZrmkz: 1569 case X86::VPERMILPDrm: 1570 case X86::VPERMILPDYrm: 1571 case X86::VPERMILPDZ128rm: 1572 case X86::VPERMILPDZ128rmk: 1573 case X86::VPERMILPDZ128rmkz: 1574 case X86::VPERMILPDZ256rm: 1575 case X86::VPERMILPDZ256rmk: 1576 case X86::VPERMILPDZ256rmkz: 1577 case X86::VPERMILPDZrm: 1578 case X86::VPERMILPDZrmk: 1579 case X86::VPERMILPDZrmkz: { 1580 if (!OutStreamer->isVerboseAsm()) 1581 break; 1582 unsigned SrcIdx, MaskIdx; 1583 unsigned ElSize; 1584 switch (MI->getOpcode()) { 1585 default: llvm_unreachable("Invalid opcode"); 1586 case X86::VPERMILPSrm: 1587 case X86::VPERMILPSYrm: 1588 case X86::VPERMILPSZ128rm: 1589 case X86::VPERMILPSZ256rm: 1590 case X86::VPERMILPSZrm: 1591 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; 1592 case X86::VPERMILPSZ128rmkz: 1593 case X86::VPERMILPSZ256rmkz: 1594 case X86::VPERMILPSZrmkz: 1595 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; 1596 case X86::VPERMILPSZ128rmk: 1597 case X86::VPERMILPSZ256rmk: 1598 case X86::VPERMILPSZrmk: 1599 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; 1600 case X86::VPERMILPDrm: 1601 case X86::VPERMILPDYrm: 1602 case X86::VPERMILPDZ128rm: 1603 case X86::VPERMILPDZ256rm: 1604 case X86::VPERMILPDZrm: 1605 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; 1606 case X86::VPERMILPDZ128rmkz: 1607 case X86::VPERMILPDZ256rmkz: 1608 case X86::VPERMILPDZrmkz: 1609 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break; 1610 case X86::VPERMILPDZ128rmk: 1611 case X86::VPERMILPDZ256rmk: 1612 case X86::VPERMILPDZrmk: 1613 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break; 1614 } 1615 1616 assert(MI->getNumOperands() >= 6 && 1617 "We should always have at least 6 operands!"); 1618 1619 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 1620 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1621 SmallVector<int, 16> Mask; 1622 DecodeVPERMILPMask(C, ElSize, Mask); 1623 if (!Mask.empty()) 1624 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 1625 } 1626 break; 1627 } 1628 1629 case X86::VPERMIL2PDrm: 1630 case X86::VPERMIL2PSrm: 1631 case X86::VPERMIL2PDrmY: 1632 case X86::VPERMIL2PSrmY: { 1633 if (!OutStreamer->isVerboseAsm()) 1634 break; 1635 assert(MI->getNumOperands() >= 8 && 1636 "We should always have at least 8 operands!"); 1637 1638 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); 1639 if (!CtrlOp.isImm()) 1640 break; 1641 1642 unsigned ElSize; 1643 switch (MI->getOpcode()) { 1644 default: llvm_unreachable("Invalid opcode"); 1645 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSrmY: ElSize = 32; break; 1646 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDrmY: ElSize = 64; break; 1647 } 1648 1649 const MachineOperand &MaskOp = MI->getOperand(6); 1650 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1651 SmallVector<int, 16> Mask; 1652 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask); 1653 if (!Mask.empty()) 1654 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 1655 } 1656 break; 1657 } 1658 1659 case X86::VPPERMrrm: { 1660 if (!OutStreamer->isVerboseAsm()) 1661 break; 1662 assert(MI->getNumOperands() >= 7 && 1663 "We should always have at least 7 operands!"); 1664 1665 const MachineOperand &MaskOp = MI->getOperand(6); 1666 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1667 SmallVector<int, 16> Mask; 1668 DecodeVPPERMMask(C, Mask); 1669 if (!Mask.empty()) 1670 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 1671 } 1672 break; 1673 } 1674 1675 #define MOV_CASE(Prefix, Suffix) \ 1676 case X86::Prefix##MOVAPD##Suffix##rm: \ 1677 case X86::Prefix##MOVAPS##Suffix##rm: \ 1678 case X86::Prefix##MOVUPD##Suffix##rm: \ 1679 case X86::Prefix##MOVUPS##Suffix##rm: \ 1680 case X86::Prefix##MOVDQA##Suffix##rm: \ 1681 case X86::Prefix##MOVDQU##Suffix##rm: 1682 1683 #define MOV_AVX512_CASE(Suffix) \ 1684 case X86::VMOVDQA64##Suffix##rm: \ 1685 case X86::VMOVDQA32##Suffix##rm: \ 1686 case X86::VMOVDQU64##Suffix##rm: \ 1687 case X86::VMOVDQU32##Suffix##rm: \ 1688 case X86::VMOVDQU16##Suffix##rm: \ 1689 case X86::VMOVDQU8##Suffix##rm: \ 1690 case X86::VMOVAPS##Suffix##rm: \ 1691 case X86::VMOVAPD##Suffix##rm: \ 1692 case X86::VMOVUPS##Suffix##rm: \ 1693 case X86::VMOVUPD##Suffix##rm: 1694 1695 #define CASE_ALL_MOV_RM() \ 1696 MOV_CASE(, ) /* SSE */ \ 1697 MOV_CASE(V, ) /* AVX-128 */ \ 1698 MOV_CASE(V, Y) /* AVX-256 */ \ 1699 MOV_AVX512_CASE(Z) \ 1700 MOV_AVX512_CASE(Z256) \ 1701 MOV_AVX512_CASE(Z128) 1702 1703 // For loads from a constant pool to a vector register, print the constant 1704 // loaded. 1705 CASE_ALL_MOV_RM() 1706 if (!OutStreamer->isVerboseAsm()) 1707 break; 1708 if (MI->getNumOperands() <= 4) 1709 break; 1710 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 1711 std::string Comment; 1712 raw_string_ostream CS(Comment); 1713 const MachineOperand &DstOp = MI->getOperand(0); 1714 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 1715 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) { 1716 CS << "["; 1717 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) { 1718 if (i != 0) 1719 CS << ","; 1720 if (CDS->getElementType()->isIntegerTy()) 1721 CS << CDS->getElementAsInteger(i); 1722 else if (CDS->getElementType()->isFloatTy()) 1723 CS << CDS->getElementAsFloat(i); 1724 else if (CDS->getElementType()->isDoubleTy()) 1725 CS << CDS->getElementAsDouble(i); 1726 else 1727 CS << "?"; 1728 } 1729 CS << "]"; 1730 OutStreamer->AddComment(CS.str()); 1731 } else if (auto *CV = dyn_cast<ConstantVector>(C)) { 1732 CS << "<"; 1733 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) { 1734 if (i != 0) 1735 CS << ","; 1736 Constant *COp = CV->getOperand(i); 1737 if (isa<UndefValue>(COp)) { 1738 CS << "u"; 1739 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) { 1740 if (CI->getBitWidth() <= 64) { 1741 CS << CI->getZExtValue(); 1742 } else { 1743 // print multi-word constant as (w0,w1) 1744 const auto &Val = CI->getValue(); 1745 CS << "("; 1746 for (int i = 0, N = Val.getNumWords(); i < N; ++i) { 1747 if (i > 0) 1748 CS << ","; 1749 CS << Val.getRawData()[i]; 1750 } 1751 CS << ")"; 1752 } 1753 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) { 1754 SmallString<32> Str; 1755 CF->getValueAPF().toString(Str); 1756 CS << Str; 1757 } else { 1758 CS << "?"; 1759 } 1760 } 1761 CS << ">"; 1762 OutStreamer->AddComment(CS.str()); 1763 } 1764 } 1765 break; 1766 } 1767 1768 MCInst TmpInst; 1769 MCInstLowering.Lower(MI, TmpInst); 1770 1771 // Stackmap shadows cannot include branch targets, so we can count the bytes 1772 // in a call towards the shadow, but must ensure that the no thread returns 1773 // in to the stackmap shadow. The only way to achieve this is if the call 1774 // is at the end of the shadow. 1775 if (MI->isCall()) { 1776 // Count then size of the call towards the shadow 1777 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get()); 1778 // Then flush the shadow so that we fill with nops before the call, not 1779 // after it. 1780 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 1781 // Then emit the call 1782 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo()); 1783 return; 1784 } 1785 1786 EmitAndCountInstruction(TmpInst); 1787 } 1788