1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains code to lower X86 MachineInstrs to their corresponding 10 // MCInst records. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/X86ATTInstPrinter.h" 15 #include "MCTargetDesc/X86BaseInfo.h" 16 #include "MCTargetDesc/X86InstComments.h" 17 #include "MCTargetDesc/X86ShuffleDecode.h" 18 #include "MCTargetDesc/X86TargetStreamer.h" 19 #include "X86AsmPrinter.h" 20 #include "X86RegisterInfo.h" 21 #include "X86ShuffleDecodeConstantPool.h" 22 #include "X86Subtarget.h" 23 #include "llvm/ADT/Optional.h" 24 #include "llvm/ADT/SmallString.h" 25 #include "llvm/ADT/iterator_range.h" 26 #include "llvm/CodeGen/MachineConstantPool.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 29 #include "llvm/CodeGen/MachineOperand.h" 30 #include "llvm/CodeGen/StackMaps.h" 31 #include "llvm/IR/DataLayout.h" 32 #include "llvm/IR/GlobalValue.h" 33 #include "llvm/IR/Mangler.h" 34 #include "llvm/MC/MCAsmInfo.h" 35 #include "llvm/MC/MCCodeEmitter.h" 36 #include "llvm/MC/MCContext.h" 37 #include "llvm/MC/MCExpr.h" 38 #include "llvm/MC/MCFixup.h" 39 #include "llvm/MC/MCInst.h" 40 #include "llvm/MC/MCInstBuilder.h" 41 #include "llvm/MC/MCSection.h" 42 #include "llvm/MC/MCSectionELF.h" 43 #include "llvm/MC/MCStreamer.h" 44 #include "llvm/MC/MCSymbol.h" 45 #include "llvm/MC/MCSymbolELF.h" 46 #include "llvm/Target/TargetLoweringObjectFile.h" 47 #include "llvm/Target/TargetMachine.h" 48 49 using namespace llvm; 50 51 namespace { 52 53 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 54 class X86MCInstLower { 55 MCContext &Ctx; 56 const MachineFunction &MF; 57 const TargetMachine &TM; 58 const MCAsmInfo &MAI; 59 X86AsmPrinter &AsmPrinter; 60 61 public: 62 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter); 63 64 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI, 65 const MachineOperand &MO) const; 66 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 67 68 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 69 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 70 71 private: 72 MachineModuleInfoMachO &getMachOMMI() const; 73 }; 74 75 } // end anonymous namespace 76 77 /// A RAII helper which defines a region of instructions which can't have 78 /// padding added between them for correctness. 79 struct NoAutoPaddingScope { 80 MCStreamer &OS; 81 const bool OldAllowAutoPadding; 82 NoAutoPaddingScope(MCStreamer &OS) 83 : OS(OS), OldAllowAutoPadding(OS.getAllowAutoPadding()) { 84 changeAndComment(false); 85 } 86 ~NoAutoPaddingScope() { changeAndComment(OldAllowAutoPadding); } 87 void changeAndComment(bool b) { 88 if (b == OS.getAllowAutoPadding()) 89 return; 90 OS.setAllowAutoPadding(b); 91 if (b) 92 OS.emitRawComment("autopadding"); 93 else 94 OS.emitRawComment("noautopadding"); 95 } 96 }; 97 98 // Emit a minimal sequence of nops spanning NumBytes bytes. 99 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 100 const MCSubtargetInfo &STI); 101 102 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst, 103 const MCSubtargetInfo &STI, 104 MCCodeEmitter *CodeEmitter) { 105 if (InShadow) { 106 SmallString<256> Code; 107 SmallVector<MCFixup, 4> Fixups; 108 raw_svector_ostream VecOS(Code); 109 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI); 110 CurrentShadowSize += Code.size(); 111 if (CurrentShadowSize >= RequiredShadowSize) 112 InShadow = false; // The shadow is big enough. Stop counting. 113 } 114 } 115 116 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding( 117 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { 118 if (InShadow && CurrentShadowSize < RequiredShadowSize) { 119 InShadow = false; 120 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize, 121 MF->getSubtarget<X86Subtarget>().is64Bit(), STI); 122 } 123 } 124 125 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) { 126 OutStreamer->emitInstruction(Inst, getSubtargetInfo()); 127 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get()); 128 } 129 130 X86MCInstLower::X86MCInstLower(const MachineFunction &mf, 131 X86AsmPrinter &asmprinter) 132 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()), 133 AsmPrinter(asmprinter) {} 134 135 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 136 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 137 } 138 139 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 140 /// operand to an MCSymbol. 141 MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const { 142 const Triple &TT = TM.getTargetTriple(); 143 if (MO.isGlobal() && TT.isOSBinFormatELF()) 144 return AsmPrinter.getSymbolPreferLocal(*MO.getGlobal()); 145 146 const DataLayout &DL = MF.getDataLayout(); 147 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && 148 "Isn't a symbol reference"); 149 150 MCSymbol *Sym = nullptr; 151 SmallString<128> Name; 152 StringRef Suffix; 153 154 switch (MO.getTargetFlags()) { 155 case X86II::MO_DLLIMPORT: 156 // Handle dllimport linkage. 157 Name += "__imp_"; 158 break; 159 case X86II::MO_COFFSTUB: 160 Name += ".refptr."; 161 break; 162 case X86II::MO_DARWIN_NONLAZY: 163 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 164 Suffix = "$non_lazy_ptr"; 165 break; 166 } 167 168 if (!Suffix.empty()) 169 Name += DL.getPrivateGlobalPrefix(); 170 171 if (MO.isGlobal()) { 172 const GlobalValue *GV = MO.getGlobal(); 173 AsmPrinter.getNameWithPrefix(Name, GV); 174 } else if (MO.isSymbol()) { 175 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL); 176 } else if (MO.isMBB()) { 177 assert(Suffix.empty()); 178 Sym = MO.getMBB()->getSymbol(); 179 } 180 181 Name += Suffix; 182 if (!Sym) 183 Sym = Ctx.getOrCreateSymbol(Name); 184 185 // If the target flags on the operand changes the name of the symbol, do that 186 // before we return the symbol. 187 switch (MO.getTargetFlags()) { 188 default: 189 break; 190 case X86II::MO_COFFSTUB: { 191 MachineModuleInfoCOFF &MMICOFF = 192 MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>(); 193 MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym); 194 if (!StubSym.getPointer()) { 195 assert(MO.isGlobal() && "Extern symbol not handled yet"); 196 StubSym = MachineModuleInfoImpl::StubValueTy( 197 AsmPrinter.getSymbol(MO.getGlobal()), true); 198 } 199 break; 200 } 201 case X86II::MO_DARWIN_NONLAZY: 202 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 203 MachineModuleInfoImpl::StubValueTy &StubSym = 204 getMachOMMI().getGVStubEntry(Sym); 205 if (!StubSym.getPointer()) { 206 assert(MO.isGlobal() && "Extern symbol not handled yet"); 207 StubSym = MachineModuleInfoImpl::StubValueTy( 208 AsmPrinter.getSymbol(MO.getGlobal()), 209 !MO.getGlobal()->hasInternalLinkage()); 210 } 211 break; 212 } 213 } 214 215 return Sym; 216 } 217 218 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 219 MCSymbol *Sym) const { 220 // FIXME: We would like an efficient form for this, so we don't have to do a 221 // lot of extra uniquing. 222 const MCExpr *Expr = nullptr; 223 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 224 225 switch (MO.getTargetFlags()) { 226 default: 227 llvm_unreachable("Unknown target flag on GV operand"); 228 case X86II::MO_NO_FLAG: // No flag. 229 // These affect the name of the symbol, not any suffix. 230 case X86II::MO_DARWIN_NONLAZY: 231 case X86II::MO_DLLIMPORT: 232 case X86II::MO_COFFSTUB: 233 break; 234 235 case X86II::MO_TLVP: 236 RefKind = MCSymbolRefExpr::VK_TLVP; 237 break; 238 case X86II::MO_TLVP_PIC_BASE: 239 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 240 // Subtract the pic base. 241 Expr = MCBinaryExpr::createSub( 242 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx); 243 break; 244 case X86II::MO_SECREL: 245 RefKind = MCSymbolRefExpr::VK_SECREL; 246 break; 247 case X86II::MO_TLSGD: 248 RefKind = MCSymbolRefExpr::VK_TLSGD; 249 break; 250 case X86II::MO_TLSLD: 251 RefKind = MCSymbolRefExpr::VK_TLSLD; 252 break; 253 case X86II::MO_TLSLDM: 254 RefKind = MCSymbolRefExpr::VK_TLSLDM; 255 break; 256 case X86II::MO_GOTTPOFF: 257 RefKind = MCSymbolRefExpr::VK_GOTTPOFF; 258 break; 259 case X86II::MO_INDNTPOFF: 260 RefKind = MCSymbolRefExpr::VK_INDNTPOFF; 261 break; 262 case X86II::MO_TPOFF: 263 RefKind = MCSymbolRefExpr::VK_TPOFF; 264 break; 265 case X86II::MO_DTPOFF: 266 RefKind = MCSymbolRefExpr::VK_DTPOFF; 267 break; 268 case X86II::MO_NTPOFF: 269 RefKind = MCSymbolRefExpr::VK_NTPOFF; 270 break; 271 case X86II::MO_GOTNTPOFF: 272 RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; 273 break; 274 case X86II::MO_GOTPCREL: 275 RefKind = MCSymbolRefExpr::VK_GOTPCREL; 276 break; 277 case X86II::MO_GOT: 278 RefKind = MCSymbolRefExpr::VK_GOT; 279 break; 280 case X86II::MO_GOTOFF: 281 RefKind = MCSymbolRefExpr::VK_GOTOFF; 282 break; 283 case X86II::MO_PLT: 284 RefKind = MCSymbolRefExpr::VK_PLT; 285 break; 286 case X86II::MO_ABS8: 287 RefKind = MCSymbolRefExpr::VK_X86_ABS8; 288 break; 289 case X86II::MO_PIC_BASE_OFFSET: 290 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 291 Expr = MCSymbolRefExpr::create(Sym, Ctx); 292 // Subtract the pic base. 293 Expr = MCBinaryExpr::createSub( 294 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx); 295 if (MO.isJTI()) { 296 assert(MAI.doesSetDirectiveSuppressReloc()); 297 // If .set directive is supported, use it to reduce the number of 298 // relocations the assembler will generate for differences between 299 // local labels. This is only safe when the symbols are in the same 300 // section so we are restricting it to jumptable references. 301 MCSymbol *Label = Ctx.createTempSymbol(); 302 AsmPrinter.OutStreamer->emitAssignment(Label, Expr); 303 Expr = MCSymbolRefExpr::create(Label, Ctx); 304 } 305 break; 306 } 307 308 if (!Expr) 309 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx); 310 311 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 312 Expr = MCBinaryExpr::createAdd( 313 Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); 314 return MCOperand::createExpr(Expr); 315 } 316 317 /// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 318 /// a short fixed-register form. 319 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 320 unsigned ImmOp = Inst.getNumOperands() - 1; 321 assert(Inst.getOperand(0).isReg() && 322 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 323 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 324 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 325 Inst.getNumOperands() == 2) && 326 "Unexpected instruction!"); 327 328 // Check whether the destination register can be fixed. 329 unsigned Reg = Inst.getOperand(0).getReg(); 330 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 331 return; 332 333 // If so, rewrite the instruction. 334 MCOperand Saved = Inst.getOperand(ImmOp); 335 Inst = MCInst(); 336 Inst.setOpcode(Opcode); 337 Inst.addOperand(Saved); 338 } 339 340 /// If a movsx instruction has a shorter encoding for the used register 341 /// simplify the instruction to use it instead. 342 static void SimplifyMOVSX(MCInst &Inst) { 343 unsigned NewOpcode = 0; 344 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 345 switch (Inst.getOpcode()) { 346 default: 347 llvm_unreachable("Unexpected instruction!"); 348 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 349 if (Op0 == X86::AX && Op1 == X86::AL) 350 NewOpcode = X86::CBW; 351 break; 352 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 353 if (Op0 == X86::EAX && Op1 == X86::AX) 354 NewOpcode = X86::CWDE; 355 break; 356 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 357 if (Op0 == X86::RAX && Op1 == X86::EAX) 358 NewOpcode = X86::CDQE; 359 break; 360 } 361 362 if (NewOpcode != 0) { 363 Inst = MCInst(); 364 Inst.setOpcode(NewOpcode); 365 } 366 } 367 368 /// Simplify things like MOV32rm to MOV32o32a. 369 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 370 unsigned Opcode) { 371 // Don't make these simplifications in 64-bit mode; other assemblers don't 372 // perform them because they make the code larger. 373 if (Printer.getSubtarget().is64Bit()) 374 return; 375 376 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 377 unsigned AddrBase = IsStore; 378 unsigned RegOp = IsStore ? 0 : 5; 379 unsigned AddrOp = AddrBase + 3; 380 assert( 381 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 382 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && 383 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && 384 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && 385 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && 386 (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && 387 "Unexpected instruction!"); 388 389 // Check whether the destination register can be fixed. 390 unsigned Reg = Inst.getOperand(RegOp).getReg(); 391 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 392 return; 393 394 // Check whether this is an absolute address. 395 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 396 // to do this here. 397 bool Absolute = true; 398 if (Inst.getOperand(AddrOp).isExpr()) { 399 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 400 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 401 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 402 Absolute = false; 403 } 404 405 if (Absolute && 406 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || 407 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || 408 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) 409 return; 410 411 // If so, rewrite the instruction. 412 MCOperand Saved = Inst.getOperand(AddrOp); 413 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); 414 Inst = MCInst(); 415 Inst.setOpcode(Opcode); 416 Inst.addOperand(Saved); 417 Inst.addOperand(Seg); 418 } 419 420 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { 421 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 422 } 423 424 Optional<MCOperand> 425 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI, 426 const MachineOperand &MO) const { 427 switch (MO.getType()) { 428 default: 429 MI->print(errs()); 430 llvm_unreachable("unknown operand type"); 431 case MachineOperand::MO_Register: 432 // Ignore all implicit register operands. 433 if (MO.isImplicit()) 434 return None; 435 return MCOperand::createReg(MO.getReg()); 436 case MachineOperand::MO_Immediate: 437 return MCOperand::createImm(MO.getImm()); 438 case MachineOperand::MO_MachineBasicBlock: 439 case MachineOperand::MO_GlobalAddress: 440 case MachineOperand::MO_ExternalSymbol: 441 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 442 case MachineOperand::MO_MCSymbol: 443 return LowerSymbolOperand(MO, MO.getMCSymbol()); 444 case MachineOperand::MO_JumpTableIndex: 445 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 446 case MachineOperand::MO_ConstantPoolIndex: 447 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 448 case MachineOperand::MO_BlockAddress: 449 return LowerSymbolOperand( 450 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 451 case MachineOperand::MO_RegisterMask: 452 // Ignore call clobbers. 453 return None; 454 } 455 } 456 457 // Replace TAILJMP opcodes with their equivalent opcodes that have encoding 458 // information. 459 static unsigned convertTailJumpOpcode(unsigned Opcode) { 460 switch (Opcode) { 461 case X86::TAILJMPr: 462 Opcode = X86::JMP32r; 463 break; 464 case X86::TAILJMPm: 465 Opcode = X86::JMP32m; 466 break; 467 case X86::TAILJMPr64: 468 Opcode = X86::JMP64r; 469 break; 470 case X86::TAILJMPm64: 471 Opcode = X86::JMP64m; 472 break; 473 case X86::TAILJMPr64_REX: 474 Opcode = X86::JMP64r_REX; 475 break; 476 case X86::TAILJMPm64_REX: 477 Opcode = X86::JMP64m_REX; 478 break; 479 case X86::TAILJMPd: 480 case X86::TAILJMPd64: 481 Opcode = X86::JMP_1; 482 break; 483 case X86::TAILJMPd_CC: 484 case X86::TAILJMPd64_CC: 485 Opcode = X86::JCC_1; 486 break; 487 } 488 489 return Opcode; 490 } 491 492 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 493 OutMI.setOpcode(MI->getOpcode()); 494 495 for (const MachineOperand &MO : MI->operands()) 496 if (auto MaybeMCOp = LowerMachineOperand(MI, MO)) 497 OutMI.addOperand(MaybeMCOp.getValue()); 498 499 // Handle a few special cases to eliminate operand modifiers. 500 switch (OutMI.getOpcode()) { 501 case X86::LEA64_32r: 502 case X86::LEA64r: 503 case X86::LEA16r: 504 case X86::LEA32r: 505 // LEA should have a segment register, but it must be empty. 506 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands && 507 "Unexpected # of LEA operands"); 508 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && 509 "LEA has segment specified!"); 510 break; 511 512 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 513 // if one of the registers is extended, but other isn't. 514 case X86::VMOVZPQILo2PQIrr: 515 case X86::VMOVAPDrr: 516 case X86::VMOVAPDYrr: 517 case X86::VMOVAPSrr: 518 case X86::VMOVAPSYrr: 519 case X86::VMOVDQArr: 520 case X86::VMOVDQAYrr: 521 case X86::VMOVDQUrr: 522 case X86::VMOVDQUYrr: 523 case X86::VMOVUPDrr: 524 case X86::VMOVUPDYrr: 525 case X86::VMOVUPSrr: 526 case X86::VMOVUPSYrr: { 527 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 528 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 529 unsigned NewOpc; 530 switch (OutMI.getOpcode()) { 531 default: llvm_unreachable("Invalid opcode"); 532 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; 533 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 534 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 535 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 536 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 537 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 538 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 539 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 540 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 541 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 542 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 543 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 544 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 545 } 546 OutMI.setOpcode(NewOpc); 547 } 548 break; 549 } 550 case X86::VMOVSDrr: 551 case X86::VMOVSSrr: { 552 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 553 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 554 unsigned NewOpc; 555 switch (OutMI.getOpcode()) { 556 default: llvm_unreachable("Invalid opcode"); 557 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 558 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 559 } 560 OutMI.setOpcode(NewOpc); 561 } 562 break; 563 } 564 565 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rmik: 566 case X86::VPCMPBZ128rri: case X86::VPCMPBZ128rrik: 567 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rmik: 568 case X86::VPCMPBZ256rri: case X86::VPCMPBZ256rrik: 569 case X86::VPCMPBZrmi: case X86::VPCMPBZrmik: 570 case X86::VPCMPBZrri: case X86::VPCMPBZrrik: 571 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rmik: 572 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk: 573 case X86::VPCMPDZ128rri: case X86::VPCMPDZ128rrik: 574 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rmik: 575 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk: 576 case X86::VPCMPDZ256rri: case X86::VPCMPDZ256rrik: 577 case X86::VPCMPDZrmi: case X86::VPCMPDZrmik: 578 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk: 579 case X86::VPCMPDZrri: case X86::VPCMPDZrrik: 580 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rmik: 581 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk: 582 case X86::VPCMPQZ128rri: case X86::VPCMPQZ128rrik: 583 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rmik: 584 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk: 585 case X86::VPCMPQZ256rri: case X86::VPCMPQZ256rrik: 586 case X86::VPCMPQZrmi: case X86::VPCMPQZrmik: 587 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk: 588 case X86::VPCMPQZrri: case X86::VPCMPQZrrik: 589 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rmik: 590 case X86::VPCMPWZ128rri: case X86::VPCMPWZ128rrik: 591 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rmik: 592 case X86::VPCMPWZ256rri: case X86::VPCMPWZ256rrik: 593 case X86::VPCMPWZrmi: case X86::VPCMPWZrmik: 594 case X86::VPCMPWZrri: case X86::VPCMPWZrrik: { 595 // Turn immediate 0 into the VPCMPEQ instruction. 596 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 0) { 597 unsigned NewOpc; 598 switch (OutMI.getOpcode()) { 599 default: llvm_unreachable("Invalid opcode"); 600 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPEQBZ128rm; break; 601 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPEQBZ128rmk; break; 602 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPEQBZ128rr; break; 603 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPEQBZ128rrk; break; 604 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPEQBZ256rm; break; 605 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPEQBZ256rmk; break; 606 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPEQBZ256rr; break; 607 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPEQBZ256rrk; break; 608 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPEQBZrm; break; 609 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPEQBZrmk; break; 610 case X86::VPCMPBZrri: NewOpc = X86::VPCMPEQBZrr; break; 611 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPEQBZrrk; break; 612 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPEQDZ128rm; break; 613 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPEQDZ128rmb; break; 614 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPEQDZ128rmbk; break; 615 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPEQDZ128rmk; break; 616 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPEQDZ128rr; break; 617 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPEQDZ128rrk; break; 618 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPEQDZ256rm; break; 619 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPEQDZ256rmb; break; 620 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPEQDZ256rmbk; break; 621 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPEQDZ256rmk; break; 622 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPEQDZ256rr; break; 623 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPEQDZ256rrk; break; 624 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPEQDZrm; break; 625 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPEQDZrmb; break; 626 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPEQDZrmbk; break; 627 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPEQDZrmk; break; 628 case X86::VPCMPDZrri: NewOpc = X86::VPCMPEQDZrr; break; 629 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPEQDZrrk; break; 630 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPEQQZ128rm; break; 631 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPEQQZ128rmb; break; 632 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPEQQZ128rmbk; break; 633 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPEQQZ128rmk; break; 634 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPEQQZ128rr; break; 635 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPEQQZ128rrk; break; 636 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPEQQZ256rm; break; 637 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPEQQZ256rmb; break; 638 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPEQQZ256rmbk; break; 639 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPEQQZ256rmk; break; 640 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPEQQZ256rr; break; 641 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPEQQZ256rrk; break; 642 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPEQQZrm; break; 643 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPEQQZrmb; break; 644 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPEQQZrmbk; break; 645 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPEQQZrmk; break; 646 case X86::VPCMPQZrri: NewOpc = X86::VPCMPEQQZrr; break; 647 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPEQQZrrk; break; 648 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPEQWZ128rm; break; 649 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPEQWZ128rmk; break; 650 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPEQWZ128rr; break; 651 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPEQWZ128rrk; break; 652 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPEQWZ256rm; break; 653 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPEQWZ256rmk; break; 654 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPEQWZ256rr; break; 655 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPEQWZ256rrk; break; 656 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPEQWZrm; break; 657 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPEQWZrmk; break; 658 case X86::VPCMPWZrri: NewOpc = X86::VPCMPEQWZrr; break; 659 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPEQWZrrk; break; 660 } 661 662 OutMI.setOpcode(NewOpc); 663 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1)); 664 break; 665 } 666 667 // Turn immediate 6 into the VPCMPGT instruction. 668 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 6) { 669 unsigned NewOpc; 670 switch (OutMI.getOpcode()) { 671 default: llvm_unreachable("Invalid opcode"); 672 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPGTBZ128rm; break; 673 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPGTBZ128rmk; break; 674 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPGTBZ128rr; break; 675 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPGTBZ128rrk; break; 676 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPGTBZ256rm; break; 677 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPGTBZ256rmk; break; 678 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPGTBZ256rr; break; 679 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPGTBZ256rrk; break; 680 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPGTBZrm; break; 681 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPGTBZrmk; break; 682 case X86::VPCMPBZrri: NewOpc = X86::VPCMPGTBZrr; break; 683 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPGTBZrrk; break; 684 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPGTDZ128rm; break; 685 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPGTDZ128rmb; break; 686 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPGTDZ128rmbk; break; 687 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPGTDZ128rmk; break; 688 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPGTDZ128rr; break; 689 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPGTDZ128rrk; break; 690 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPGTDZ256rm; break; 691 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPGTDZ256rmb; break; 692 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPGTDZ256rmbk; break; 693 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPGTDZ256rmk; break; 694 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPGTDZ256rr; break; 695 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPGTDZ256rrk; break; 696 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPGTDZrm; break; 697 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPGTDZrmb; break; 698 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPGTDZrmbk; break; 699 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPGTDZrmk; break; 700 case X86::VPCMPDZrri: NewOpc = X86::VPCMPGTDZrr; break; 701 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPGTDZrrk; break; 702 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPGTQZ128rm; break; 703 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPGTQZ128rmb; break; 704 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPGTQZ128rmbk; break; 705 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPGTQZ128rmk; break; 706 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPGTQZ128rr; break; 707 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPGTQZ128rrk; break; 708 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPGTQZ256rm; break; 709 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPGTQZ256rmb; break; 710 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPGTQZ256rmbk; break; 711 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPGTQZ256rmk; break; 712 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPGTQZ256rr; break; 713 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPGTQZ256rrk; break; 714 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPGTQZrm; break; 715 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPGTQZrmb; break; 716 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPGTQZrmbk; break; 717 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPGTQZrmk; break; 718 case X86::VPCMPQZrri: NewOpc = X86::VPCMPGTQZrr; break; 719 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPGTQZrrk; break; 720 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPGTWZ128rm; break; 721 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPGTWZ128rmk; break; 722 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPGTWZ128rr; break; 723 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPGTWZ128rrk; break; 724 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPGTWZ256rm; break; 725 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPGTWZ256rmk; break; 726 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPGTWZ256rr; break; 727 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPGTWZ256rrk; break; 728 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPGTWZrm; break; 729 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPGTWZrmk; break; 730 case X86::VPCMPWZrri: NewOpc = X86::VPCMPGTWZrr; break; 731 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPGTWZrrk; break; 732 } 733 734 OutMI.setOpcode(NewOpc); 735 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1)); 736 break; 737 } 738 739 break; 740 } 741 742 // CALL64r, CALL64pcrel32 - These instructions used to have 743 // register inputs modeled as normal uses instead of implicit uses. As such, 744 // they we used to truncate off all but the first operand (the callee). This 745 // issue seems to have been fixed at some point. This assert verifies that. 746 case X86::CALL64r: 747 case X86::CALL64pcrel32: 748 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!"); 749 break; 750 751 case X86::EH_RETURN: 752 case X86::EH_RETURN64: { 753 OutMI = MCInst(); 754 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 755 break; 756 } 757 758 case X86::CLEANUPRET: { 759 // Replace CLEANUPRET with the appropriate RET. 760 OutMI = MCInst(); 761 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 762 break; 763 } 764 765 case X86::CATCHRET: { 766 // Replace CATCHRET with the appropriate RET. 767 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); 768 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 769 OutMI = MCInst(); 770 OutMI.setOpcode(getRetOpcode(Subtarget)); 771 OutMI.addOperand(MCOperand::createReg(ReturnReg)); 772 break; 773 } 774 775 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump 776 // instruction. 777 case X86::TAILJMPr: 778 case X86::TAILJMPr64: 779 case X86::TAILJMPr64_REX: 780 case X86::TAILJMPd: 781 case X86::TAILJMPd64: 782 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!"); 783 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); 784 break; 785 786 case X86::TAILJMPd_CC: 787 case X86::TAILJMPd64_CC: 788 assert(OutMI.getNumOperands() == 2 && "Unexpected number of operands!"); 789 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); 790 break; 791 792 case X86::TAILJMPm: 793 case X86::TAILJMPm64: 794 case X86::TAILJMPm64_REX: 795 assert(OutMI.getNumOperands() == X86::AddrNumOperands && 796 "Unexpected number of operands!"); 797 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); 798 break; 799 800 case X86::DEC16r: 801 case X86::DEC32r: 802 case X86::INC16r: 803 case X86::INC32r: 804 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions. 805 if (!AsmPrinter.getSubtarget().is64Bit()) { 806 unsigned Opcode; 807 switch (OutMI.getOpcode()) { 808 default: llvm_unreachable("Invalid opcode"); 809 case X86::DEC16r: Opcode = X86::DEC16r_alt; break; 810 case X86::DEC32r: Opcode = X86::DEC32r_alt; break; 811 case X86::INC16r: Opcode = X86::INC16r_alt; break; 812 case X86::INC32r: Opcode = X86::INC32r_alt; break; 813 } 814 OutMI.setOpcode(Opcode); 815 } 816 break; 817 818 // We don't currently select the correct instruction form for instructions 819 // which have a short %eax, etc. form. Handle this by custom lowering, for 820 // now. 821 // 822 // Note, we are currently not handling the following instructions: 823 // MOV64ao8, MOV64o8a 824 // XCHG16ar, XCHG32ar, XCHG64ar 825 case X86::MOV8mr_NOREX: 826 case X86::MOV8mr: 827 case X86::MOV8rm_NOREX: 828 case X86::MOV8rm: 829 case X86::MOV16mr: 830 case X86::MOV16rm: 831 case X86::MOV32mr: 832 case X86::MOV32rm: { 833 unsigned NewOpc; 834 switch (OutMI.getOpcode()) { 835 default: llvm_unreachable("Invalid opcode"); 836 case X86::MOV8mr_NOREX: 837 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; 838 case X86::MOV8rm_NOREX: 839 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; 840 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; 841 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; 842 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break; 843 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break; 844 } 845 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc); 846 break; 847 } 848 849 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32: 850 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32: 851 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32: 852 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32: 853 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32: 854 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32: 855 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32: 856 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32: 857 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: { 858 unsigned NewOpc; 859 switch (OutMI.getOpcode()) { 860 default: llvm_unreachable("Invalid opcode"); 861 case X86::ADC8ri: NewOpc = X86::ADC8i8; break; 862 case X86::ADC16ri: NewOpc = X86::ADC16i16; break; 863 case X86::ADC32ri: NewOpc = X86::ADC32i32; break; 864 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break; 865 case X86::ADD8ri: NewOpc = X86::ADD8i8; break; 866 case X86::ADD16ri: NewOpc = X86::ADD16i16; break; 867 case X86::ADD32ri: NewOpc = X86::ADD32i32; break; 868 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break; 869 case X86::AND8ri: NewOpc = X86::AND8i8; break; 870 case X86::AND16ri: NewOpc = X86::AND16i16; break; 871 case X86::AND32ri: NewOpc = X86::AND32i32; break; 872 case X86::AND64ri32: NewOpc = X86::AND64i32; break; 873 case X86::CMP8ri: NewOpc = X86::CMP8i8; break; 874 case X86::CMP16ri: NewOpc = X86::CMP16i16; break; 875 case X86::CMP32ri: NewOpc = X86::CMP32i32; break; 876 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break; 877 case X86::OR8ri: NewOpc = X86::OR8i8; break; 878 case X86::OR16ri: NewOpc = X86::OR16i16; break; 879 case X86::OR32ri: NewOpc = X86::OR32i32; break; 880 case X86::OR64ri32: NewOpc = X86::OR64i32; break; 881 case X86::SBB8ri: NewOpc = X86::SBB8i8; break; 882 case X86::SBB16ri: NewOpc = X86::SBB16i16; break; 883 case X86::SBB32ri: NewOpc = X86::SBB32i32; break; 884 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break; 885 case X86::SUB8ri: NewOpc = X86::SUB8i8; break; 886 case X86::SUB16ri: NewOpc = X86::SUB16i16; break; 887 case X86::SUB32ri: NewOpc = X86::SUB32i32; break; 888 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break; 889 case X86::TEST8ri: NewOpc = X86::TEST8i8; break; 890 case X86::TEST16ri: NewOpc = X86::TEST16i16; break; 891 case X86::TEST32ri: NewOpc = X86::TEST32i32; break; 892 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break; 893 case X86::XOR8ri: NewOpc = X86::XOR8i8; break; 894 case X86::XOR16ri: NewOpc = X86::XOR16i16; break; 895 case X86::XOR32ri: NewOpc = X86::XOR32i32; break; 896 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break; 897 } 898 SimplifyShortImmForm(OutMI, NewOpc); 899 break; 900 } 901 902 // Try to shrink some forms of movsx. 903 case X86::MOVSX16rr8: 904 case X86::MOVSX32rr16: 905 case X86::MOVSX64rr32: 906 SimplifyMOVSX(OutMI); 907 break; 908 909 case X86::VCMPPDrri: 910 case X86::VCMPPDYrri: 911 case X86::VCMPPSrri: 912 case X86::VCMPPSYrri: 913 case X86::VCMPSDrr: 914 case X86::VCMPSSrr: { 915 // Swap the operands if it will enable a 2 byte VEX encoding. 916 // FIXME: Change the immediate to improve opportunities? 917 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) && 918 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 919 unsigned Imm = MI->getOperand(3).getImm() & 0x7; 920 switch (Imm) { 921 default: break; 922 case 0x00: // EQUAL 923 case 0x03: // UNORDERED 924 case 0x04: // NOT EQUAL 925 case 0x07: // ORDERED 926 std::swap(OutMI.getOperand(1), OutMI.getOperand(2)); 927 break; 928 } 929 } 930 break; 931 } 932 933 case X86::VMOVHLPSrr: 934 case X86::VUNPCKHPDrr: 935 // These are not truly commutable so hide them from the default case. 936 break; 937 938 default: { 939 // If the instruction is a commutable arithmetic instruction we might be 940 // able to commute the operands to get a 2 byte VEX prefix. 941 uint64_t TSFlags = MI->getDesc().TSFlags; 942 if (MI->getDesc().isCommutable() && 943 (TSFlags & X86II::EncodingMask) == X86II::VEX && 944 (TSFlags & X86II::OpMapMask) == X86II::TB && 945 (TSFlags & X86II::FormMask) == X86II::MRMSrcReg && 946 !(TSFlags & X86II::VEX_W) && (TSFlags & X86II::VEX_4V) && 947 OutMI.getNumOperands() == 3) { 948 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) && 949 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) 950 std::swap(OutMI.getOperand(1), OutMI.getOperand(2)); 951 } 952 break; 953 } 954 } 955 } 956 957 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering, 958 const MachineInstr &MI) { 959 NoAutoPaddingScope NoPadScope(*OutStreamer); 960 bool Is64Bits = MI.getOpcode() == X86::TLS_addr64 || 961 MI.getOpcode() == X86::TLS_base_addr64; 962 MCContext &Ctx = OutStreamer->getContext(); 963 964 MCSymbolRefExpr::VariantKind SRVK; 965 switch (MI.getOpcode()) { 966 case X86::TLS_addr32: 967 case X86::TLS_addr64: 968 SRVK = MCSymbolRefExpr::VK_TLSGD; 969 break; 970 case X86::TLS_base_addr32: 971 SRVK = MCSymbolRefExpr::VK_TLSLDM; 972 break; 973 case X86::TLS_base_addr64: 974 SRVK = MCSymbolRefExpr::VK_TLSLD; 975 break; 976 default: 977 llvm_unreachable("unexpected opcode"); 978 } 979 980 const MCSymbolRefExpr *Sym = MCSymbolRefExpr::create( 981 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx); 982 983 // As of binutils 2.32, ld has a bogus TLS relaxation error when the GD/LD 984 // code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is 985 // attempted to be relaxed to IE/LE (binutils PR24784). Work around the bug by 986 // only using GOT when GOTPCRELX is enabled. 987 // TODO Delete the workaround when GOTPCRELX becomes commonplace. 988 bool UseGot = MMI->getModule()->getRtLibUseGOT() && 989 Ctx.getAsmInfo()->canRelaxRelocations(); 990 991 if (Is64Bits) { 992 bool NeedsPadding = SRVK == MCSymbolRefExpr::VK_TLSGD; 993 if (NeedsPadding) 994 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 995 EmitAndCountInstruction(MCInstBuilder(X86::LEA64r) 996 .addReg(X86::RDI) 997 .addReg(X86::RIP) 998 .addImm(1) 999 .addReg(0) 1000 .addExpr(Sym) 1001 .addReg(0)); 1002 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("__tls_get_addr"); 1003 if (NeedsPadding) { 1004 if (!UseGot) 1005 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 1006 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 1007 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX)); 1008 } 1009 if (UseGot) { 1010 const MCExpr *Expr = MCSymbolRefExpr::create( 1011 TlsGetAddr, MCSymbolRefExpr::VK_GOTPCREL, Ctx); 1012 EmitAndCountInstruction(MCInstBuilder(X86::CALL64m) 1013 .addReg(X86::RIP) 1014 .addImm(1) 1015 .addReg(0) 1016 .addExpr(Expr) 1017 .addReg(0)); 1018 } else { 1019 EmitAndCountInstruction( 1020 MCInstBuilder(X86::CALL64pcrel32) 1021 .addExpr(MCSymbolRefExpr::create(TlsGetAddr, 1022 MCSymbolRefExpr::VK_PLT, Ctx))); 1023 } 1024 } else { 1025 if (SRVK == MCSymbolRefExpr::VK_TLSGD && !UseGot) { 1026 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r) 1027 .addReg(X86::EAX) 1028 .addReg(0) 1029 .addImm(1) 1030 .addReg(X86::EBX) 1031 .addExpr(Sym) 1032 .addReg(0)); 1033 } else { 1034 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r) 1035 .addReg(X86::EAX) 1036 .addReg(X86::EBX) 1037 .addImm(1) 1038 .addReg(0) 1039 .addExpr(Sym) 1040 .addReg(0)); 1041 } 1042 1043 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("___tls_get_addr"); 1044 if (UseGot) { 1045 const MCExpr *Expr = 1046 MCSymbolRefExpr::create(TlsGetAddr, MCSymbolRefExpr::VK_GOT, Ctx); 1047 EmitAndCountInstruction(MCInstBuilder(X86::CALL32m) 1048 .addReg(X86::EBX) 1049 .addImm(1) 1050 .addReg(0) 1051 .addExpr(Expr) 1052 .addReg(0)); 1053 } else { 1054 EmitAndCountInstruction( 1055 MCInstBuilder(X86::CALLpcrel32) 1056 .addExpr(MCSymbolRefExpr::create(TlsGetAddr, 1057 MCSymbolRefExpr::VK_PLT, Ctx))); 1058 } 1059 } 1060 } 1061 1062 /// Return the longest nop which can be efficiently decoded for the given 1063 /// target cpu. 15-bytes is the longest single NOP instruction, but some 1064 /// platforms can't decode the longest forms efficiently. 1065 static unsigned MaxLongNopLength(const MCSubtargetInfo &STI) { 1066 uint64_t MaxNopLength = 10; 1067 if (STI.getFeatureBits()[X86::ProcIntelSLM]) 1068 MaxNopLength = 7; 1069 else if (STI.getFeatureBits()[X86::FeatureFast15ByteNOP]) 1070 MaxNopLength = 15; 1071 else if (STI.getFeatureBits()[X86::FeatureFast11ByteNOP]) 1072 MaxNopLength = 11; 1073 return MaxNopLength; 1074 } 1075 1076 /// Emit the largest nop instruction smaller than or equal to \p NumBytes 1077 /// bytes. Return the size of nop emitted. 1078 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 1079 const MCSubtargetInfo &STI) { 1080 if (!Is64Bit) { 1081 // TODO Do additional checking if the CPU supports multi-byte nops. 1082 OS.emitInstruction(MCInstBuilder(X86::NOOP), STI); 1083 return 1; 1084 } 1085 1086 // Cap a single nop emission at the profitable value for the target 1087 NumBytes = std::min(NumBytes, MaxLongNopLength(STI)); 1088 1089 unsigned NopSize; 1090 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; 1091 IndexReg = Displacement = SegmentReg = 0; 1092 BaseReg = X86::RAX; 1093 ScaleVal = 1; 1094 switch (NumBytes) { 1095 case 0: 1096 llvm_unreachable("Zero nops?"); 1097 break; 1098 case 1: 1099 NopSize = 1; 1100 Opc = X86::NOOP; 1101 break; 1102 case 2: 1103 NopSize = 2; 1104 Opc = X86::XCHG16ar; 1105 break; 1106 case 3: 1107 NopSize = 3; 1108 Opc = X86::NOOPL; 1109 break; 1110 case 4: 1111 NopSize = 4; 1112 Opc = X86::NOOPL; 1113 Displacement = 8; 1114 break; 1115 case 5: 1116 NopSize = 5; 1117 Opc = X86::NOOPL; 1118 Displacement = 8; 1119 IndexReg = X86::RAX; 1120 break; 1121 case 6: 1122 NopSize = 6; 1123 Opc = X86::NOOPW; 1124 Displacement = 8; 1125 IndexReg = X86::RAX; 1126 break; 1127 case 7: 1128 NopSize = 7; 1129 Opc = X86::NOOPL; 1130 Displacement = 512; 1131 break; 1132 case 8: 1133 NopSize = 8; 1134 Opc = X86::NOOPL; 1135 Displacement = 512; 1136 IndexReg = X86::RAX; 1137 break; 1138 case 9: 1139 NopSize = 9; 1140 Opc = X86::NOOPW; 1141 Displacement = 512; 1142 IndexReg = X86::RAX; 1143 break; 1144 default: 1145 NopSize = 10; 1146 Opc = X86::NOOPW; 1147 Displacement = 512; 1148 IndexReg = X86::RAX; 1149 SegmentReg = X86::CS; 1150 break; 1151 } 1152 1153 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U); 1154 NopSize += NumPrefixes; 1155 for (unsigned i = 0; i != NumPrefixes; ++i) 1156 OS.emitBytes("\x66"); 1157 1158 switch (Opc) { 1159 default: llvm_unreachable("Unexpected opcode"); 1160 case X86::NOOP: 1161 OS.emitInstruction(MCInstBuilder(Opc), STI); 1162 break; 1163 case X86::XCHG16ar: 1164 OS.emitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI); 1165 break; 1166 case X86::NOOPL: 1167 case X86::NOOPW: 1168 OS.emitInstruction(MCInstBuilder(Opc) 1169 .addReg(BaseReg) 1170 .addImm(ScaleVal) 1171 .addReg(IndexReg) 1172 .addImm(Displacement) 1173 .addReg(SegmentReg), 1174 STI); 1175 break; 1176 } 1177 assert(NopSize <= NumBytes && "We overemitted?"); 1178 return NopSize; 1179 } 1180 1181 /// Emit the optimal amount of multi-byte nops on X86. 1182 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 1183 const MCSubtargetInfo &STI) { 1184 unsigned NopsToEmit = NumBytes; 1185 (void)NopsToEmit; 1186 while (NumBytes) { 1187 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI); 1188 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!"); 1189 } 1190 } 1191 1192 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI, 1193 X86MCInstLower &MCIL) { 1194 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); 1195 1196 NoAutoPaddingScope NoPadScope(*OutStreamer); 1197 1198 StatepointOpers SOpers(&MI); 1199 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) { 1200 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(), 1201 getSubtargetInfo()); 1202 } else { 1203 // Lower call target and choose correct opcode 1204 const MachineOperand &CallTarget = SOpers.getCallTarget(); 1205 MCOperand CallTargetMCOp; 1206 unsigned CallOpcode; 1207 switch (CallTarget.getType()) { 1208 case MachineOperand::MO_GlobalAddress: 1209 case MachineOperand::MO_ExternalSymbol: 1210 CallTargetMCOp = MCIL.LowerSymbolOperand( 1211 CallTarget, MCIL.GetSymbolFromOperand(CallTarget)); 1212 CallOpcode = X86::CALL64pcrel32; 1213 // Currently, we only support relative addressing with statepoints. 1214 // Otherwise, we'll need a scratch register to hold the target 1215 // address. You'll fail asserts during load & relocation if this 1216 // symbol is to far away. (TODO: support non-relative addressing) 1217 break; 1218 case MachineOperand::MO_Immediate: 1219 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); 1220 CallOpcode = X86::CALL64pcrel32; 1221 // Currently, we only support relative addressing with statepoints. 1222 // Otherwise, we'll need a scratch register to hold the target 1223 // immediate. You'll fail asserts during load & relocation if this 1224 // address is to far away. (TODO: support non-relative addressing) 1225 break; 1226 case MachineOperand::MO_Register: 1227 // FIXME: Add retpoline support and remove this. 1228 if (Subtarget->useIndirectThunkCalls()) 1229 report_fatal_error("Lowering register statepoints with thunks not " 1230 "yet implemented."); 1231 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); 1232 CallOpcode = X86::CALL64r; 1233 break; 1234 default: 1235 llvm_unreachable("Unsupported operand type in statepoint call target"); 1236 break; 1237 } 1238 1239 // Emit call 1240 MCInst CallInst; 1241 CallInst.setOpcode(CallOpcode); 1242 CallInst.addOperand(CallTargetMCOp); 1243 OutStreamer->emitInstruction(CallInst, getSubtargetInfo()); 1244 } 1245 1246 // Record our statepoint node in the same section used by STACKMAP 1247 // and PATCHPOINT 1248 auto &Ctx = OutStreamer->getContext(); 1249 MCSymbol *MILabel = Ctx.createTempSymbol(); 1250 OutStreamer->emitLabel(MILabel); 1251 SM.recordStatepoint(*MILabel, MI); 1252 } 1253 1254 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI, 1255 X86MCInstLower &MCIL) { 1256 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>, 1257 // <opcode>, <operands> 1258 1259 NoAutoPaddingScope NoPadScope(*OutStreamer); 1260 1261 Register DefRegister = FaultingMI.getOperand(0).getReg(); 1262 FaultMaps::FaultKind FK = 1263 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm()); 1264 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol(); 1265 unsigned Opcode = FaultingMI.getOperand(3).getImm(); 1266 unsigned OperandsBeginIdx = 4; 1267 1268 auto &Ctx = OutStreamer->getContext(); 1269 MCSymbol *FaultingLabel = Ctx.createTempSymbol(); 1270 OutStreamer->emitLabel(FaultingLabel); 1271 1272 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!"); 1273 FM.recordFaultingOp(FK, FaultingLabel, HandlerLabel); 1274 1275 MCInst MI; 1276 MI.setOpcode(Opcode); 1277 1278 if (DefRegister != X86::NoRegister) 1279 MI.addOperand(MCOperand::createReg(DefRegister)); 1280 1281 for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx, 1282 E = FaultingMI.operands_end(); 1283 I != E; ++I) 1284 if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I)) 1285 MI.addOperand(MaybeOperand.getValue()); 1286 1287 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName()); 1288 OutStreamer->emitInstruction(MI, getSubtargetInfo()); 1289 } 1290 1291 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI, 1292 X86MCInstLower &MCIL) { 1293 bool Is64Bits = Subtarget->is64Bit(); 1294 MCContext &Ctx = OutStreamer->getContext(); 1295 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__"); 1296 const MCSymbolRefExpr *Op = 1297 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx); 1298 1299 EmitAndCountInstruction( 1300 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32) 1301 .addExpr(Op)); 1302 } 1303 1304 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, 1305 X86MCInstLower &MCIL) { 1306 // PATCHABLE_OP minsize, opcode, operands 1307 1308 NoAutoPaddingScope NoPadScope(*OutStreamer); 1309 1310 unsigned MinSize = MI.getOperand(0).getImm(); 1311 unsigned Opcode = MI.getOperand(1).getImm(); 1312 1313 MCInst MCI; 1314 MCI.setOpcode(Opcode); 1315 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end())) 1316 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1317 MCI.addOperand(MaybeOperand.getValue()); 1318 1319 SmallString<256> Code; 1320 SmallVector<MCFixup, 4> Fixups; 1321 raw_svector_ostream VecOS(Code); 1322 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo()); 1323 1324 if (Code.size() < MinSize) { 1325 if (MinSize == 2 && Opcode == X86::PUSH64r) { 1326 // This is an optimization that lets us get away without emitting a nop in 1327 // many cases. 1328 // 1329 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two 1330 // bytes too, so the check on MinSize is important. 1331 MCI.setOpcode(X86::PUSH64rmr); 1332 } else { 1333 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(), 1334 getSubtargetInfo()); 1335 assert(NopSize == MinSize && "Could not implement MinSize!"); 1336 (void)NopSize; 1337 } 1338 } 1339 1340 OutStreamer->emitInstruction(MCI, getSubtargetInfo()); 1341 } 1342 1343 // Lower a stackmap of the form: 1344 // <id>, <shadowBytes>, ... 1345 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { 1346 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 1347 1348 auto &Ctx = OutStreamer->getContext(); 1349 MCSymbol *MILabel = Ctx.createTempSymbol(); 1350 OutStreamer->emitLabel(MILabel); 1351 1352 SM.recordStackMap(*MILabel, MI); 1353 unsigned NumShadowBytes = MI.getOperand(1).getImm(); 1354 SMShadowTracker.reset(NumShadowBytes); 1355 } 1356 1357 // Lower a patchpoint of the form: 1358 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ... 1359 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI, 1360 X86MCInstLower &MCIL) { 1361 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); 1362 1363 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 1364 1365 NoAutoPaddingScope NoPadScope(*OutStreamer); 1366 1367 auto &Ctx = OutStreamer->getContext(); 1368 MCSymbol *MILabel = Ctx.createTempSymbol(); 1369 OutStreamer->emitLabel(MILabel); 1370 SM.recordPatchPoint(*MILabel, MI); 1371 1372 PatchPointOpers opers(&MI); 1373 unsigned ScratchIdx = opers.getNextScratchIdx(); 1374 unsigned EncodedBytes = 0; 1375 const MachineOperand &CalleeMO = opers.getCallTarget(); 1376 1377 // Check for null target. If target is non-null (i.e. is non-zero or is 1378 // symbolic) then emit a call. 1379 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) { 1380 MCOperand CalleeMCOp; 1381 switch (CalleeMO.getType()) { 1382 default: 1383 /// FIXME: Add a verifier check for bad callee types. 1384 llvm_unreachable("Unrecognized callee operand type."); 1385 case MachineOperand::MO_Immediate: 1386 if (CalleeMO.getImm()) 1387 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm()); 1388 break; 1389 case MachineOperand::MO_ExternalSymbol: 1390 case MachineOperand::MO_GlobalAddress: 1391 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO, 1392 MCIL.GetSymbolFromOperand(CalleeMO)); 1393 break; 1394 } 1395 1396 // Emit MOV to materialize the target address and the CALL to target. 1397 // This is encoded with 12-13 bytes, depending on which register is used. 1398 Register ScratchReg = MI.getOperand(ScratchIdx).getReg(); 1399 if (X86II::isX86_64ExtendedReg(ScratchReg)) 1400 EncodedBytes = 13; 1401 else 1402 EncodedBytes = 12; 1403 1404 EmitAndCountInstruction( 1405 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); 1406 // FIXME: Add retpoline support and remove this. 1407 if (Subtarget->useIndirectThunkCalls()) 1408 report_fatal_error( 1409 "Lowering patchpoint with thunks not yet implemented."); 1410 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); 1411 } 1412 1413 // Emit padding. 1414 unsigned NumBytes = opers.getNumPatchBytes(); 1415 assert(NumBytes >= EncodedBytes && 1416 "Patchpoint can't request size less than the length of a call."); 1417 1418 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(), 1419 getSubtargetInfo()); 1420 } 1421 1422 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, 1423 X86MCInstLower &MCIL) { 1424 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64"); 1425 1426 NoAutoPaddingScope NoPadScope(*OutStreamer); 1427 1428 // We want to emit the following pattern, which follows the x86 calling 1429 // convention to prepare for the trampoline call to be patched in. 1430 // 1431 // .p2align 1, ... 1432 // .Lxray_event_sled_N: 1433 // jmp +N // jump across the instrumentation sled 1434 // ... // set up arguments in register 1435 // callq __xray_CustomEvent@plt // force dependency to symbol 1436 // ... 1437 // <jump here> 1438 // 1439 // After patching, it would look something like: 1440 // 1441 // nopw (2-byte nop) 1442 // ... 1443 // callq __xrayCustomEvent // already lowered 1444 // ... 1445 // 1446 // --- 1447 // First we emit the label and the jump. 1448 auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true); 1449 OutStreamer->AddComment("# XRay Custom Event Log"); 1450 OutStreamer->emitCodeAlignment(2); 1451 OutStreamer->emitLabel(CurSled); 1452 1453 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1454 // an operand (computed as an offset from the jmp instruction). 1455 // FIXME: Find another less hacky way do force the relative jump. 1456 OutStreamer->emitBinaryData("\xeb\x0f"); 1457 1458 // The default C calling convention will place two arguments into %rcx and 1459 // %rdx -- so we only work with those. 1460 const Register DestRegs[] = {X86::RDI, X86::RSI}; 1461 bool UsedMask[] = {false, false}; 1462 // Filled out in loop. 1463 Register SrcRegs[] = {0, 0}; 1464 1465 // Then we put the operands in the %rdi and %rsi registers. We spill the 1466 // values in the register before we clobber them, and mark them as used in 1467 // UsedMask. In case the arguments are already in the correct register, we use 1468 // emit nops appropriately sized to keep the sled the same size in every 1469 // situation. 1470 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1471 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) { 1472 assert(Op->isReg() && "Only support arguments in registers"); 1473 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); 1474 if (SrcRegs[I] != DestRegs[I]) { 1475 UsedMask[I] = true; 1476 EmitAndCountInstruction( 1477 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); 1478 } else { 1479 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo()); 1480 } 1481 } 1482 1483 // Now that the register values are stashed, mov arguments into place. 1484 // FIXME: This doesn't work if one of the later SrcRegs is equal to an 1485 // earlier DestReg. We will have already overwritten over the register before 1486 // we can copy from it. 1487 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1488 if (SrcRegs[I] != DestRegs[I]) 1489 EmitAndCountInstruction( 1490 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1491 1492 // We emit a hard dependency on the __xray_CustomEvent symbol, which is the 1493 // name of the trampoline to be implemented by the XRay runtime. 1494 auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent"); 1495 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym); 1496 if (isPositionIndependent()) 1497 TOp.setTargetFlags(X86II::MO_PLT); 1498 1499 // Emit the call instruction. 1500 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32) 1501 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym))); 1502 1503 // Restore caller-saved and used registers. 1504 for (unsigned I = sizeof UsedMask; I-- > 0;) 1505 if (UsedMask[I]) 1506 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); 1507 else 1508 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo()); 1509 1510 OutStreamer->AddComment("xray custom event end."); 1511 1512 // Record the sled version. Version 0 of this sled was spelled differently, so 1513 // we let the runtime handle the different offsets we're using. Version 2 1514 // changed the absolute address to a PC-relative address. 1515 recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 2); 1516 } 1517 1518 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI, 1519 X86MCInstLower &MCIL) { 1520 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64"); 1521 1522 NoAutoPaddingScope NoPadScope(*OutStreamer); 1523 1524 // We want to emit the following pattern, which follows the x86 calling 1525 // convention to prepare for the trampoline call to be patched in. 1526 // 1527 // .p2align 1, ... 1528 // .Lxray_event_sled_N: 1529 // jmp +N // jump across the instrumentation sled 1530 // ... // set up arguments in register 1531 // callq __xray_TypedEvent@plt // force dependency to symbol 1532 // ... 1533 // <jump here> 1534 // 1535 // After patching, it would look something like: 1536 // 1537 // nopw (2-byte nop) 1538 // ... 1539 // callq __xrayTypedEvent // already lowered 1540 // ... 1541 // 1542 // --- 1543 // First we emit the label and the jump. 1544 auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true); 1545 OutStreamer->AddComment("# XRay Typed Event Log"); 1546 OutStreamer->emitCodeAlignment(2); 1547 OutStreamer->emitLabel(CurSled); 1548 1549 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1550 // an operand (computed as an offset from the jmp instruction). 1551 // FIXME: Find another less hacky way do force the relative jump. 1552 OutStreamer->emitBinaryData("\xeb\x14"); 1553 1554 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8, 1555 // so we'll work with those. Or we may be called via SystemV, in which case 1556 // we don't have to do any translation. 1557 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX}; 1558 bool UsedMask[] = {false, false, false}; 1559 1560 // Will fill out src regs in the loop. 1561 Register SrcRegs[] = {0, 0, 0}; 1562 1563 // Then we put the operands in the SystemV registers. We spill the values in 1564 // the registers before we clobber them, and mark them as used in UsedMask. 1565 // In case the arguments are already in the correct register, we emit nops 1566 // appropriately sized to keep the sled the same size in every situation. 1567 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1568 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) { 1569 // TODO: Is register only support adequate? 1570 assert(Op->isReg() && "Only supports arguments in registers"); 1571 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); 1572 if (SrcRegs[I] != DestRegs[I]) { 1573 UsedMask[I] = true; 1574 EmitAndCountInstruction( 1575 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); 1576 } else { 1577 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo()); 1578 } 1579 } 1580 1581 // In the above loop we only stash all of the destination registers or emit 1582 // nops if the arguments are already in the right place. Doing the actually 1583 // moving is postponed until after all the registers are stashed so nothing 1584 // is clobbers. We've already added nops to account for the size of mov and 1585 // push if the register is in the right place, so we only have to worry about 1586 // emitting movs. 1587 // FIXME: This doesn't work if one of the later SrcRegs is equal to an 1588 // earlier DestReg. We will have already overwritten over the register before 1589 // we can copy from it. 1590 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1591 if (UsedMask[I]) 1592 EmitAndCountInstruction( 1593 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1594 1595 // We emit a hard dependency on the __xray_TypedEvent symbol, which is the 1596 // name of the trampoline to be implemented by the XRay runtime. 1597 auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent"); 1598 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym); 1599 if (isPositionIndependent()) 1600 TOp.setTargetFlags(X86II::MO_PLT); 1601 1602 // Emit the call instruction. 1603 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32) 1604 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym))); 1605 1606 // Restore caller-saved and used registers. 1607 for (unsigned I = sizeof UsedMask; I-- > 0;) 1608 if (UsedMask[I]) 1609 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); 1610 else 1611 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo()); 1612 1613 OutStreamer->AddComment("xray typed event end."); 1614 1615 // Record the sled version. 1616 recordSled(CurSled, MI, SledKind::TYPED_EVENT, 2); 1617 } 1618 1619 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI, 1620 X86MCInstLower &MCIL) { 1621 1622 NoAutoPaddingScope NoPadScope(*OutStreamer); 1623 1624 const Function &F = MF->getFunction(); 1625 if (F.hasFnAttribute("patchable-function-entry")) { 1626 unsigned Num; 1627 if (F.getFnAttribute("patchable-function-entry") 1628 .getValueAsString() 1629 .getAsInteger(10, Num)) 1630 return; 1631 EmitNops(*OutStreamer, Num, Subtarget->is64Bit(), getSubtargetInfo()); 1632 return; 1633 } 1634 // We want to emit the following pattern: 1635 // 1636 // .p2align 1, ... 1637 // .Lxray_sled_N: 1638 // jmp .tmpN 1639 // # 9 bytes worth of noops 1640 // 1641 // We need the 9 bytes because at runtime, we'd be patching over the full 11 1642 // bytes with the following pattern: 1643 // 1644 // mov %r10, <function id, 32-bit> // 6 bytes 1645 // call <relative offset, 32-bits> // 5 bytes 1646 // 1647 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1648 OutStreamer->emitCodeAlignment(2); 1649 OutStreamer->emitLabel(CurSled); 1650 1651 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1652 // an operand (computed as an offset from the jmp instruction). 1653 // FIXME: Find another less hacky way do force the relative jump. 1654 OutStreamer->emitBytes("\xeb\x09"); 1655 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1656 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER, 2); 1657 } 1658 1659 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI, 1660 X86MCInstLower &MCIL) { 1661 NoAutoPaddingScope NoPadScope(*OutStreamer); 1662 1663 // Since PATCHABLE_RET takes the opcode of the return statement as an 1664 // argument, we use that to emit the correct form of the RET that we want. 1665 // i.e. when we see this: 1666 // 1667 // PATCHABLE_RET X86::RET ... 1668 // 1669 // We should emit the RET followed by sleds. 1670 // 1671 // .p2align 1, ... 1672 // .Lxray_sled_N: 1673 // ret # or equivalent instruction 1674 // # 10 bytes worth of noops 1675 // 1676 // This just makes sure that the alignment for the next instruction is 2. 1677 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1678 OutStreamer->emitCodeAlignment(2); 1679 OutStreamer->emitLabel(CurSled); 1680 unsigned OpCode = MI.getOperand(0).getImm(); 1681 MCInst Ret; 1682 Ret.setOpcode(OpCode); 1683 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1684 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1685 Ret.addOperand(MaybeOperand.getValue()); 1686 OutStreamer->emitInstruction(Ret, getSubtargetInfo()); 1687 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo()); 1688 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT, 2); 1689 } 1690 1691 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, 1692 X86MCInstLower &MCIL) { 1693 NoAutoPaddingScope NoPadScope(*OutStreamer); 1694 1695 // Like PATCHABLE_RET, we have the actual instruction in the operands to this 1696 // instruction so we lower that particular instruction and its operands. 1697 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how 1698 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to 1699 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual 1700 // tail call much like how we have it in PATCHABLE_RET. 1701 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1702 OutStreamer->emitCodeAlignment(2); 1703 OutStreamer->emitLabel(CurSled); 1704 auto Target = OutContext.createTempSymbol(); 1705 1706 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1707 // an operand (computed as an offset from the jmp instruction). 1708 // FIXME: Find another less hacky way do force the relative jump. 1709 OutStreamer->emitBytes("\xeb\x09"); 1710 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1711 OutStreamer->emitLabel(Target); 1712 recordSled(CurSled, MI, SledKind::TAIL_CALL, 2); 1713 1714 unsigned OpCode = MI.getOperand(0).getImm(); 1715 OpCode = convertTailJumpOpcode(OpCode); 1716 MCInst TC; 1717 TC.setOpcode(OpCode); 1718 1719 // Before emitting the instruction, add a comment to indicate that this is 1720 // indeed a tail call. 1721 OutStreamer->AddComment("TAILCALL"); 1722 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1723 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1724 TC.addOperand(MaybeOperand.getValue()); 1725 OutStreamer->emitInstruction(TC, getSubtargetInfo()); 1726 } 1727 1728 // Returns instruction preceding MBBI in MachineFunction. 1729 // If MBBI is the first instruction of the first basic block, returns null. 1730 static MachineBasicBlock::const_iterator 1731 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) { 1732 const MachineBasicBlock *MBB = MBBI->getParent(); 1733 while (MBBI == MBB->begin()) { 1734 if (MBB == &MBB->getParent()->front()) 1735 return MachineBasicBlock::const_iterator(); 1736 MBB = MBB->getPrevNode(); 1737 MBBI = MBB->end(); 1738 } 1739 --MBBI; 1740 return MBBI; 1741 } 1742 1743 static const Constant *getConstantFromPool(const MachineInstr &MI, 1744 const MachineOperand &Op) { 1745 if (!Op.isCPI() || Op.getOffset() != 0) 1746 return nullptr; 1747 1748 ArrayRef<MachineConstantPoolEntry> Constants = 1749 MI.getParent()->getParent()->getConstantPool()->getConstants(); 1750 const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()]; 1751 1752 // Bail if this is a machine constant pool entry, we won't be able to dig out 1753 // anything useful. 1754 if (ConstantEntry.isMachineConstantPoolEntry()) 1755 return nullptr; 1756 1757 const Constant *C = ConstantEntry.Val.ConstVal; 1758 assert((!C || ConstantEntry.getType() == C->getType()) && 1759 "Expected a constant of the same type!"); 1760 return C; 1761 } 1762 1763 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, 1764 unsigned SrcOp2Idx, ArrayRef<int> Mask) { 1765 std::string Comment; 1766 1767 // Compute the name for a register. This is really goofy because we have 1768 // multiple instruction printers that could (in theory) use different 1769 // names. Fortunately most people use the ATT style (outside of Windows) 1770 // and they actually agree on register naming here. Ultimately, this is 1771 // a comment, and so its OK if it isn't perfect. 1772 auto GetRegisterName = [](unsigned RegNum) -> StringRef { 1773 return X86ATTInstPrinter::getRegisterName(RegNum); 1774 }; 1775 1776 const MachineOperand &DstOp = MI->getOperand(0); 1777 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); 1778 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); 1779 1780 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; 1781 StringRef Src1Name = 1782 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; 1783 StringRef Src2Name = 1784 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; 1785 1786 // One source operand, fix the mask to print all elements in one span. 1787 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end()); 1788 if (Src1Name == Src2Name) 1789 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) 1790 if (ShuffleMask[i] >= e) 1791 ShuffleMask[i] -= e; 1792 1793 raw_string_ostream CS(Comment); 1794 CS << DstName; 1795 1796 // Handle AVX512 MASK/MASXZ write mask comments. 1797 // MASK: zmmX {%kY} 1798 // MASKZ: zmmX {%kY} {z} 1799 if (SrcOp1Idx > 1) { 1800 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask"); 1801 1802 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1); 1803 if (WriteMaskOp.isReg()) { 1804 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}"; 1805 1806 if (SrcOp1Idx == 2) { 1807 CS << " {z}"; 1808 } 1809 } 1810 } 1811 1812 CS << " = "; 1813 1814 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) { 1815 if (i != 0) 1816 CS << ","; 1817 if (ShuffleMask[i] == SM_SentinelZero) { 1818 CS << "zero"; 1819 continue; 1820 } 1821 1822 // Otherwise, it must come from src1 or src2. Print the span of elements 1823 // that comes from this src. 1824 bool isSrc1 = ShuffleMask[i] < (int)e; 1825 CS << (isSrc1 ? Src1Name : Src2Name) << '['; 1826 1827 bool IsFirst = true; 1828 while (i != e && ShuffleMask[i] != SM_SentinelZero && 1829 (ShuffleMask[i] < (int)e) == isSrc1) { 1830 if (!IsFirst) 1831 CS << ','; 1832 else 1833 IsFirst = false; 1834 if (ShuffleMask[i] == SM_SentinelUndef) 1835 CS << "u"; 1836 else 1837 CS << ShuffleMask[i] % (int)e; 1838 ++i; 1839 } 1840 CS << ']'; 1841 --i; // For loop increments element #. 1842 } 1843 CS.flush(); 1844 1845 return Comment; 1846 } 1847 1848 static void printConstant(const APInt &Val, raw_ostream &CS) { 1849 if (Val.getBitWidth() <= 64) { 1850 CS << Val.getZExtValue(); 1851 } else { 1852 // print multi-word constant as (w0,w1) 1853 CS << "("; 1854 for (int i = 0, N = Val.getNumWords(); i < N; ++i) { 1855 if (i > 0) 1856 CS << ","; 1857 CS << Val.getRawData()[i]; 1858 } 1859 CS << ")"; 1860 } 1861 } 1862 1863 static void printConstant(const APFloat &Flt, raw_ostream &CS) { 1864 SmallString<32> Str; 1865 // Force scientific notation to distinquish from integers. 1866 Flt.toString(Str, 0, 0); 1867 CS << Str; 1868 } 1869 1870 static void printConstant(const Constant *COp, raw_ostream &CS) { 1871 if (isa<UndefValue>(COp)) { 1872 CS << "u"; 1873 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) { 1874 printConstant(CI->getValue(), CS); 1875 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) { 1876 printConstant(CF->getValueAPF(), CS); 1877 } else { 1878 CS << "?"; 1879 } 1880 } 1881 1882 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) { 1883 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1884 assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only"); 1885 1886 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86. 1887 if (EmitFPOData) { 1888 X86TargetStreamer *XTS = 1889 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer()); 1890 switch (MI->getOpcode()) { 1891 case X86::SEH_PushReg: 1892 XTS->emitFPOPushReg(MI->getOperand(0).getImm()); 1893 break; 1894 case X86::SEH_StackAlloc: 1895 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm()); 1896 break; 1897 case X86::SEH_StackAlign: 1898 XTS->emitFPOStackAlign(MI->getOperand(0).getImm()); 1899 break; 1900 case X86::SEH_SetFrame: 1901 assert(MI->getOperand(1).getImm() == 0 && 1902 ".cv_fpo_setframe takes no offset"); 1903 XTS->emitFPOSetFrame(MI->getOperand(0).getImm()); 1904 break; 1905 case X86::SEH_EndPrologue: 1906 XTS->emitFPOEndPrologue(); 1907 break; 1908 case X86::SEH_SaveReg: 1909 case X86::SEH_SaveXMM: 1910 case X86::SEH_PushFrame: 1911 llvm_unreachable("SEH_ directive incompatible with FPO"); 1912 break; 1913 default: 1914 llvm_unreachable("expected SEH_ instruction"); 1915 } 1916 return; 1917 } 1918 1919 // Otherwise, use the .seh_ directives for all other Windows platforms. 1920 switch (MI->getOpcode()) { 1921 case X86::SEH_PushReg: 1922 OutStreamer->EmitWinCFIPushReg(MI->getOperand(0).getImm()); 1923 break; 1924 1925 case X86::SEH_SaveReg: 1926 OutStreamer->EmitWinCFISaveReg(MI->getOperand(0).getImm(), 1927 MI->getOperand(1).getImm()); 1928 break; 1929 1930 case X86::SEH_SaveXMM: 1931 OutStreamer->EmitWinCFISaveXMM(MI->getOperand(0).getImm(), 1932 MI->getOperand(1).getImm()); 1933 break; 1934 1935 case X86::SEH_StackAlloc: 1936 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm()); 1937 break; 1938 1939 case X86::SEH_SetFrame: 1940 OutStreamer->EmitWinCFISetFrame(MI->getOperand(0).getImm(), 1941 MI->getOperand(1).getImm()); 1942 break; 1943 1944 case X86::SEH_PushFrame: 1945 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm()); 1946 break; 1947 1948 case X86::SEH_EndPrologue: 1949 OutStreamer->EmitWinCFIEndProlog(); 1950 break; 1951 1952 default: 1953 llvm_unreachable("expected SEH_ instruction"); 1954 } 1955 } 1956 1957 static unsigned getRegisterWidth(const MCOperandInfo &Info) { 1958 if (Info.RegClass == X86::VR128RegClassID || 1959 Info.RegClass == X86::VR128XRegClassID) 1960 return 128; 1961 if (Info.RegClass == X86::VR256RegClassID || 1962 Info.RegClass == X86::VR256XRegClassID) 1963 return 256; 1964 if (Info.RegClass == X86::VR512RegClassID) 1965 return 512; 1966 llvm_unreachable("Unknown register class!"); 1967 } 1968 1969 void X86AsmPrinter::emitInstruction(const MachineInstr *MI) { 1970 X86MCInstLower MCInstLowering(*MF, *this); 1971 const X86RegisterInfo *RI = 1972 MF->getSubtarget<X86Subtarget>().getRegisterInfo(); 1973 1974 // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that 1975 // are compressed from EVEX encoding to VEX encoding. 1976 if (TM.Options.MCOptions.ShowMCEncoding) { 1977 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) 1978 OutStreamer->AddComment("EVEX TO VEX Compression ", false); 1979 } 1980 1981 switch (MI->getOpcode()) { 1982 case TargetOpcode::DBG_VALUE: 1983 llvm_unreachable("Should be handled target independently"); 1984 1985 // Emit nothing here but a comment if we can. 1986 case X86::Int_MemBarrier: 1987 OutStreamer->emitRawComment("MEMBARRIER"); 1988 return; 1989 1990 case X86::EH_RETURN: 1991 case X86::EH_RETURN64: { 1992 // Lower these as normal, but add some comments. 1993 Register Reg = MI->getOperand(0).getReg(); 1994 OutStreamer->AddComment(StringRef("eh_return, addr: %") + 1995 X86ATTInstPrinter::getRegisterName(Reg)); 1996 break; 1997 } 1998 case X86::CLEANUPRET: { 1999 // Lower these as normal, but add some comments. 2000 OutStreamer->AddComment("CLEANUPRET"); 2001 break; 2002 } 2003 2004 case X86::CATCHRET: { 2005 // Lower these as normal, but add some comments. 2006 OutStreamer->AddComment("CATCHRET"); 2007 break; 2008 } 2009 2010 case X86::ENDBR32: 2011 case X86::ENDBR64: { 2012 // CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for 2013 // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be 2014 // non-empty. If MI is the initial ENDBR, place the 2015 // __patchable_function_entries label after ENDBR. 2016 if (CurrentPatchableFunctionEntrySym && 2017 CurrentPatchableFunctionEntrySym == CurrentFnBegin && 2018 MI == &MF->front().front()) { 2019 MCInst Inst; 2020 MCInstLowering.Lower(MI, Inst); 2021 EmitAndCountInstruction(Inst); 2022 CurrentPatchableFunctionEntrySym = createTempSymbol("patch"); 2023 OutStreamer->emitLabel(CurrentPatchableFunctionEntrySym); 2024 return; 2025 } 2026 break; 2027 } 2028 2029 case X86::TAILJMPr: 2030 case X86::TAILJMPm: 2031 case X86::TAILJMPd: 2032 case X86::TAILJMPd_CC: 2033 case X86::TAILJMPr64: 2034 case X86::TAILJMPm64: 2035 case X86::TAILJMPd64: 2036 case X86::TAILJMPd64_CC: 2037 case X86::TAILJMPr64_REX: 2038 case X86::TAILJMPm64_REX: 2039 // Lower these as normal, but add some comments. 2040 OutStreamer->AddComment("TAILCALL"); 2041 break; 2042 2043 case X86::TLS_addr32: 2044 case X86::TLS_addr64: 2045 case X86::TLS_base_addr32: 2046 case X86::TLS_base_addr64: 2047 return LowerTlsAddr(MCInstLowering, *MI); 2048 2049 case X86::MOVPC32r: { 2050 // This is a pseudo op for a two instruction sequence with a label, which 2051 // looks like: 2052 // call "L1$pb" 2053 // "L1$pb": 2054 // popl %esi 2055 2056 // Emit the call. 2057 MCSymbol *PICBase = MF->getPICBaseSymbol(); 2058 // FIXME: We would like an efficient form for this, so we don't have to do a 2059 // lot of extra uniquing. 2060 EmitAndCountInstruction( 2061 MCInstBuilder(X86::CALLpcrel32) 2062 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext))); 2063 2064 const X86FrameLowering *FrameLowering = 2065 MF->getSubtarget<X86Subtarget>().getFrameLowering(); 2066 bool hasFP = FrameLowering->hasFP(*MF); 2067 2068 // TODO: This is needed only if we require precise CFA. 2069 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() && 2070 !OutStreamer->getDwarfFrameInfos().back().End; 2071 2072 int stackGrowth = -RI->getSlotSize(); 2073 2074 if (HasActiveDwarfFrame && !hasFP) { 2075 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth); 2076 } 2077 2078 // Emit the label. 2079 OutStreamer->emitLabel(PICBase); 2080 2081 // popl $reg 2082 EmitAndCountInstruction( 2083 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg())); 2084 2085 if (HasActiveDwarfFrame && !hasFP) { 2086 OutStreamer->emitCFIAdjustCfaOffset(stackGrowth); 2087 } 2088 return; 2089 } 2090 2091 case X86::ADD32ri: { 2092 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 2093 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 2094 break; 2095 2096 // Okay, we have something like: 2097 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 2098 2099 // For this, we want to print something like: 2100 // MYGLOBAL + (. - PICBASE) 2101 // However, we can't generate a ".", so just emit a new label here and refer 2102 // to it. 2103 MCSymbol *DotSym = OutContext.createTempSymbol(); 2104 OutStreamer->emitLabel(DotSym); 2105 2106 // Now that we have emitted the label, lower the complex operand expression. 2107 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 2108 2109 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext); 2110 const MCExpr *PICBase = 2111 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext); 2112 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext); 2113 2114 DotExpr = MCBinaryExpr::createAdd( 2115 MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext); 2116 2117 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri) 2118 .addReg(MI->getOperand(0).getReg()) 2119 .addReg(MI->getOperand(1).getReg()) 2120 .addExpr(DotExpr)); 2121 return; 2122 } 2123 case TargetOpcode::STATEPOINT: 2124 return LowerSTATEPOINT(*MI, MCInstLowering); 2125 2126 case TargetOpcode::FAULTING_OP: 2127 return LowerFAULTING_OP(*MI, MCInstLowering); 2128 2129 case TargetOpcode::FENTRY_CALL: 2130 return LowerFENTRY_CALL(*MI, MCInstLowering); 2131 2132 case TargetOpcode::PATCHABLE_OP: 2133 return LowerPATCHABLE_OP(*MI, MCInstLowering); 2134 2135 case TargetOpcode::STACKMAP: 2136 return LowerSTACKMAP(*MI); 2137 2138 case TargetOpcode::PATCHPOINT: 2139 return LowerPATCHPOINT(*MI, MCInstLowering); 2140 2141 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: 2142 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering); 2143 2144 case TargetOpcode::PATCHABLE_RET: 2145 return LowerPATCHABLE_RET(*MI, MCInstLowering); 2146 2147 case TargetOpcode::PATCHABLE_TAIL_CALL: 2148 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering); 2149 2150 case TargetOpcode::PATCHABLE_EVENT_CALL: 2151 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering); 2152 2153 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL: 2154 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering); 2155 2156 case X86::MORESTACK_RET: 2157 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 2158 return; 2159 2160 case X86::MORESTACK_RET_RESTORE_R10: 2161 // Return, then restore R10. 2162 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 2163 EmitAndCountInstruction( 2164 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX)); 2165 return; 2166 2167 case X86::SEH_PushReg: 2168 case X86::SEH_SaveReg: 2169 case X86::SEH_SaveXMM: 2170 case X86::SEH_StackAlloc: 2171 case X86::SEH_StackAlign: 2172 case X86::SEH_SetFrame: 2173 case X86::SEH_PushFrame: 2174 case X86::SEH_EndPrologue: 2175 EmitSEHInstruction(MI); 2176 return; 2177 2178 case X86::SEH_Epilogue: { 2179 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 2180 MachineBasicBlock::const_iterator MBBI(MI); 2181 // Check if preceded by a call and emit nop if so. 2182 for (MBBI = PrevCrossBBInst(MBBI); 2183 MBBI != MachineBasicBlock::const_iterator(); 2184 MBBI = PrevCrossBBInst(MBBI)) { 2185 // Conservatively assume that pseudo instructions don't emit code and keep 2186 // looking for a call. We may emit an unnecessary nop in some cases. 2187 if (!MBBI->isPseudo()) { 2188 if (MBBI->isCall()) 2189 EmitAndCountInstruction(MCInstBuilder(X86::NOOP)); 2190 break; 2191 } 2192 } 2193 return; 2194 } 2195 2196 // Lower PSHUFB and VPERMILP normally but add a comment if we can find 2197 // a constant shuffle mask. We won't be able to do this at the MC layer 2198 // because the mask isn't an immediate. 2199 case X86::PSHUFBrm: 2200 case X86::VPSHUFBrm: 2201 case X86::VPSHUFBYrm: 2202 case X86::VPSHUFBZ128rm: 2203 case X86::VPSHUFBZ128rmk: 2204 case X86::VPSHUFBZ128rmkz: 2205 case X86::VPSHUFBZ256rm: 2206 case X86::VPSHUFBZ256rmk: 2207 case X86::VPSHUFBZ256rmkz: 2208 case X86::VPSHUFBZrm: 2209 case X86::VPSHUFBZrmk: 2210 case X86::VPSHUFBZrmkz: { 2211 if (!OutStreamer->isVerboseAsm()) 2212 break; 2213 unsigned SrcIdx, MaskIdx; 2214 switch (MI->getOpcode()) { 2215 default: llvm_unreachable("Invalid opcode"); 2216 case X86::PSHUFBrm: 2217 case X86::VPSHUFBrm: 2218 case X86::VPSHUFBYrm: 2219 case X86::VPSHUFBZ128rm: 2220 case X86::VPSHUFBZ256rm: 2221 case X86::VPSHUFBZrm: 2222 SrcIdx = 1; MaskIdx = 5; break; 2223 case X86::VPSHUFBZ128rmkz: 2224 case X86::VPSHUFBZ256rmkz: 2225 case X86::VPSHUFBZrmkz: 2226 SrcIdx = 2; MaskIdx = 6; break; 2227 case X86::VPSHUFBZ128rmk: 2228 case X86::VPSHUFBZ256rmk: 2229 case X86::VPSHUFBZrmk: 2230 SrcIdx = 3; MaskIdx = 7; break; 2231 } 2232 2233 assert(MI->getNumOperands() >= 6 && 2234 "We should always have at least 6 operands!"); 2235 2236 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 2237 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2238 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2239 SmallVector<int, 64> Mask; 2240 DecodePSHUFBMask(C, Width, Mask); 2241 if (!Mask.empty()) 2242 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 2243 } 2244 break; 2245 } 2246 2247 case X86::VPERMILPSrm: 2248 case X86::VPERMILPSYrm: 2249 case X86::VPERMILPSZ128rm: 2250 case X86::VPERMILPSZ128rmk: 2251 case X86::VPERMILPSZ128rmkz: 2252 case X86::VPERMILPSZ256rm: 2253 case X86::VPERMILPSZ256rmk: 2254 case X86::VPERMILPSZ256rmkz: 2255 case X86::VPERMILPSZrm: 2256 case X86::VPERMILPSZrmk: 2257 case X86::VPERMILPSZrmkz: 2258 case X86::VPERMILPDrm: 2259 case X86::VPERMILPDYrm: 2260 case X86::VPERMILPDZ128rm: 2261 case X86::VPERMILPDZ128rmk: 2262 case X86::VPERMILPDZ128rmkz: 2263 case X86::VPERMILPDZ256rm: 2264 case X86::VPERMILPDZ256rmk: 2265 case X86::VPERMILPDZ256rmkz: 2266 case X86::VPERMILPDZrm: 2267 case X86::VPERMILPDZrmk: 2268 case X86::VPERMILPDZrmkz: { 2269 if (!OutStreamer->isVerboseAsm()) 2270 break; 2271 unsigned SrcIdx, MaskIdx; 2272 unsigned ElSize; 2273 switch (MI->getOpcode()) { 2274 default: llvm_unreachable("Invalid opcode"); 2275 case X86::VPERMILPSrm: 2276 case X86::VPERMILPSYrm: 2277 case X86::VPERMILPSZ128rm: 2278 case X86::VPERMILPSZ256rm: 2279 case X86::VPERMILPSZrm: 2280 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; 2281 case X86::VPERMILPSZ128rmkz: 2282 case X86::VPERMILPSZ256rmkz: 2283 case X86::VPERMILPSZrmkz: 2284 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; 2285 case X86::VPERMILPSZ128rmk: 2286 case X86::VPERMILPSZ256rmk: 2287 case X86::VPERMILPSZrmk: 2288 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; 2289 case X86::VPERMILPDrm: 2290 case X86::VPERMILPDYrm: 2291 case X86::VPERMILPDZ128rm: 2292 case X86::VPERMILPDZ256rm: 2293 case X86::VPERMILPDZrm: 2294 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; 2295 case X86::VPERMILPDZ128rmkz: 2296 case X86::VPERMILPDZ256rmkz: 2297 case X86::VPERMILPDZrmkz: 2298 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break; 2299 case X86::VPERMILPDZ128rmk: 2300 case X86::VPERMILPDZ256rmk: 2301 case X86::VPERMILPDZrmk: 2302 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break; 2303 } 2304 2305 assert(MI->getNumOperands() >= 6 && 2306 "We should always have at least 6 operands!"); 2307 2308 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 2309 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2310 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2311 SmallVector<int, 16> Mask; 2312 DecodeVPERMILPMask(C, ElSize, Width, Mask); 2313 if (!Mask.empty()) 2314 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 2315 } 2316 break; 2317 } 2318 2319 case X86::VPERMIL2PDrm: 2320 case X86::VPERMIL2PSrm: 2321 case X86::VPERMIL2PDYrm: 2322 case X86::VPERMIL2PSYrm: { 2323 if (!OutStreamer->isVerboseAsm()) 2324 break; 2325 assert(MI->getNumOperands() >= 8 && 2326 "We should always have at least 8 operands!"); 2327 2328 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); 2329 if (!CtrlOp.isImm()) 2330 break; 2331 2332 unsigned ElSize; 2333 switch (MI->getOpcode()) { 2334 default: llvm_unreachable("Invalid opcode"); 2335 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break; 2336 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break; 2337 } 2338 2339 const MachineOperand &MaskOp = MI->getOperand(6); 2340 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2341 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2342 SmallVector<int, 16> Mask; 2343 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask); 2344 if (!Mask.empty()) 2345 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 2346 } 2347 break; 2348 } 2349 2350 case X86::VPPERMrrm: { 2351 if (!OutStreamer->isVerboseAsm()) 2352 break; 2353 assert(MI->getNumOperands() >= 7 && 2354 "We should always have at least 7 operands!"); 2355 2356 const MachineOperand &MaskOp = MI->getOperand(6); 2357 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2358 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2359 SmallVector<int, 16> Mask; 2360 DecodeVPPERMMask(C, Width, Mask); 2361 if (!Mask.empty()) 2362 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 2363 } 2364 break; 2365 } 2366 2367 case X86::MMX_MOVQ64rm: { 2368 if (!OutStreamer->isVerboseAsm()) 2369 break; 2370 if (MI->getNumOperands() <= 4) 2371 break; 2372 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2373 std::string Comment; 2374 raw_string_ostream CS(Comment); 2375 const MachineOperand &DstOp = MI->getOperand(0); 2376 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 2377 if (auto *CF = dyn_cast<ConstantFP>(C)) { 2378 CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false); 2379 OutStreamer->AddComment(CS.str()); 2380 } 2381 } 2382 break; 2383 } 2384 2385 #define MOV_CASE(Prefix, Suffix) \ 2386 case X86::Prefix##MOVAPD##Suffix##rm: \ 2387 case X86::Prefix##MOVAPS##Suffix##rm: \ 2388 case X86::Prefix##MOVUPD##Suffix##rm: \ 2389 case X86::Prefix##MOVUPS##Suffix##rm: \ 2390 case X86::Prefix##MOVDQA##Suffix##rm: \ 2391 case X86::Prefix##MOVDQU##Suffix##rm: 2392 2393 #define MOV_AVX512_CASE(Suffix) \ 2394 case X86::VMOVDQA64##Suffix##rm: \ 2395 case X86::VMOVDQA32##Suffix##rm: \ 2396 case X86::VMOVDQU64##Suffix##rm: \ 2397 case X86::VMOVDQU32##Suffix##rm: \ 2398 case X86::VMOVDQU16##Suffix##rm: \ 2399 case X86::VMOVDQU8##Suffix##rm: \ 2400 case X86::VMOVAPS##Suffix##rm: \ 2401 case X86::VMOVAPD##Suffix##rm: \ 2402 case X86::VMOVUPS##Suffix##rm: \ 2403 case X86::VMOVUPD##Suffix##rm: 2404 2405 #define CASE_ALL_MOV_RM() \ 2406 MOV_CASE(, ) /* SSE */ \ 2407 MOV_CASE(V, ) /* AVX-128 */ \ 2408 MOV_CASE(V, Y) /* AVX-256 */ \ 2409 MOV_AVX512_CASE(Z) \ 2410 MOV_AVX512_CASE(Z256) \ 2411 MOV_AVX512_CASE(Z128) 2412 2413 // For loads from a constant pool to a vector register, print the constant 2414 // loaded. 2415 CASE_ALL_MOV_RM() 2416 case X86::VBROADCASTF128: 2417 case X86::VBROADCASTI128: 2418 case X86::VBROADCASTF32X4Z256rm: 2419 case X86::VBROADCASTF32X4rm: 2420 case X86::VBROADCASTF32X8rm: 2421 case X86::VBROADCASTF64X2Z128rm: 2422 case X86::VBROADCASTF64X2rm: 2423 case X86::VBROADCASTF64X4rm: 2424 case X86::VBROADCASTI32X4Z256rm: 2425 case X86::VBROADCASTI32X4rm: 2426 case X86::VBROADCASTI32X8rm: 2427 case X86::VBROADCASTI64X2Z128rm: 2428 case X86::VBROADCASTI64X2rm: 2429 case X86::VBROADCASTI64X4rm: 2430 if (!OutStreamer->isVerboseAsm()) 2431 break; 2432 if (MI->getNumOperands() <= 4) 2433 break; 2434 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2435 int NumLanes = 1; 2436 // Override NumLanes for the broadcast instructions. 2437 switch (MI->getOpcode()) { 2438 case X86::VBROADCASTF128: NumLanes = 2; break; 2439 case X86::VBROADCASTI128: NumLanes = 2; break; 2440 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break; 2441 case X86::VBROADCASTF32X4rm: NumLanes = 4; break; 2442 case X86::VBROADCASTF32X8rm: NumLanes = 2; break; 2443 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break; 2444 case X86::VBROADCASTF64X2rm: NumLanes = 4; break; 2445 case X86::VBROADCASTF64X4rm: NumLanes = 2; break; 2446 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break; 2447 case X86::VBROADCASTI32X4rm: NumLanes = 4; break; 2448 case X86::VBROADCASTI32X8rm: NumLanes = 2; break; 2449 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break; 2450 case X86::VBROADCASTI64X2rm: NumLanes = 4; break; 2451 case X86::VBROADCASTI64X4rm: NumLanes = 2; break; 2452 } 2453 2454 std::string Comment; 2455 raw_string_ostream CS(Comment); 2456 const MachineOperand &DstOp = MI->getOperand(0); 2457 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 2458 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) { 2459 CS << "["; 2460 for (int l = 0; l != NumLanes; ++l) { 2461 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; 2462 ++i) { 2463 if (i != 0 || l != 0) 2464 CS << ","; 2465 if (CDS->getElementType()->isIntegerTy()) 2466 printConstant(CDS->getElementAsAPInt(i), CS); 2467 else if (CDS->getElementType()->isHalfTy() || 2468 CDS->getElementType()->isFloatTy() || 2469 CDS->getElementType()->isDoubleTy()) 2470 printConstant(CDS->getElementAsAPFloat(i), CS); 2471 else 2472 CS << "?"; 2473 } 2474 } 2475 CS << "]"; 2476 OutStreamer->AddComment(CS.str()); 2477 } else if (auto *CV = dyn_cast<ConstantVector>(C)) { 2478 CS << "<"; 2479 for (int l = 0; l != NumLanes; ++l) { 2480 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; 2481 ++i) { 2482 if (i != 0 || l != 0) 2483 CS << ","; 2484 printConstant(CV->getOperand(i), CS); 2485 } 2486 } 2487 CS << ">"; 2488 OutStreamer->AddComment(CS.str()); 2489 } 2490 } 2491 break; 2492 case X86::MOVDDUPrm: 2493 case X86::VMOVDDUPrm: 2494 case X86::VMOVDDUPZ128rm: 2495 case X86::VBROADCASTSSrm: 2496 case X86::VBROADCASTSSYrm: 2497 case X86::VBROADCASTSSZ128rm: 2498 case X86::VBROADCASTSSZ256rm: 2499 case X86::VBROADCASTSSZrm: 2500 case X86::VBROADCASTSDYrm: 2501 case X86::VBROADCASTSDZ256rm: 2502 case X86::VBROADCASTSDZrm: 2503 case X86::VPBROADCASTBrm: 2504 case X86::VPBROADCASTBYrm: 2505 case X86::VPBROADCASTBZ128rm: 2506 case X86::VPBROADCASTBZ256rm: 2507 case X86::VPBROADCASTBZrm: 2508 case X86::VPBROADCASTDrm: 2509 case X86::VPBROADCASTDYrm: 2510 case X86::VPBROADCASTDZ128rm: 2511 case X86::VPBROADCASTDZ256rm: 2512 case X86::VPBROADCASTDZrm: 2513 case X86::VPBROADCASTQrm: 2514 case X86::VPBROADCASTQYrm: 2515 case X86::VPBROADCASTQZ128rm: 2516 case X86::VPBROADCASTQZ256rm: 2517 case X86::VPBROADCASTQZrm: 2518 case X86::VPBROADCASTWrm: 2519 case X86::VPBROADCASTWYrm: 2520 case X86::VPBROADCASTWZ128rm: 2521 case X86::VPBROADCASTWZ256rm: 2522 case X86::VPBROADCASTWZrm: 2523 if (!OutStreamer->isVerboseAsm()) 2524 break; 2525 if (MI->getNumOperands() <= 4) 2526 break; 2527 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2528 int NumElts; 2529 switch (MI->getOpcode()) { 2530 default: llvm_unreachable("Invalid opcode"); 2531 case X86::MOVDDUPrm: NumElts = 2; break; 2532 case X86::VMOVDDUPrm: NumElts = 2; break; 2533 case X86::VMOVDDUPZ128rm: NumElts = 2; break; 2534 case X86::VBROADCASTSSrm: NumElts = 4; break; 2535 case X86::VBROADCASTSSYrm: NumElts = 8; break; 2536 case X86::VBROADCASTSSZ128rm: NumElts = 4; break; 2537 case X86::VBROADCASTSSZ256rm: NumElts = 8; break; 2538 case X86::VBROADCASTSSZrm: NumElts = 16; break; 2539 case X86::VBROADCASTSDYrm: NumElts = 4; break; 2540 case X86::VBROADCASTSDZ256rm: NumElts = 4; break; 2541 case X86::VBROADCASTSDZrm: NumElts = 8; break; 2542 case X86::VPBROADCASTBrm: NumElts = 16; break; 2543 case X86::VPBROADCASTBYrm: NumElts = 32; break; 2544 case X86::VPBROADCASTBZ128rm: NumElts = 16; break; 2545 case X86::VPBROADCASTBZ256rm: NumElts = 32; break; 2546 case X86::VPBROADCASTBZrm: NumElts = 64; break; 2547 case X86::VPBROADCASTDrm: NumElts = 4; break; 2548 case X86::VPBROADCASTDYrm: NumElts = 8; break; 2549 case X86::VPBROADCASTDZ128rm: NumElts = 4; break; 2550 case X86::VPBROADCASTDZ256rm: NumElts = 8; break; 2551 case X86::VPBROADCASTDZrm: NumElts = 16; break; 2552 case X86::VPBROADCASTQrm: NumElts = 2; break; 2553 case X86::VPBROADCASTQYrm: NumElts = 4; break; 2554 case X86::VPBROADCASTQZ128rm: NumElts = 2; break; 2555 case X86::VPBROADCASTQZ256rm: NumElts = 4; break; 2556 case X86::VPBROADCASTQZrm: NumElts = 8; break; 2557 case X86::VPBROADCASTWrm: NumElts = 8; break; 2558 case X86::VPBROADCASTWYrm: NumElts = 16; break; 2559 case X86::VPBROADCASTWZ128rm: NumElts = 8; break; 2560 case X86::VPBROADCASTWZ256rm: NumElts = 16; break; 2561 case X86::VPBROADCASTWZrm: NumElts = 32; break; 2562 } 2563 2564 std::string Comment; 2565 raw_string_ostream CS(Comment); 2566 const MachineOperand &DstOp = MI->getOperand(0); 2567 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 2568 CS << "["; 2569 for (int i = 0; i != NumElts; ++i) { 2570 if (i != 0) 2571 CS << ","; 2572 printConstant(C, CS); 2573 } 2574 CS << "]"; 2575 OutStreamer->AddComment(CS.str()); 2576 } 2577 } 2578 2579 MCInst TmpInst; 2580 MCInstLowering.Lower(MI, TmpInst); 2581 2582 // Stackmap shadows cannot include branch targets, so we can count the bytes 2583 // in a call towards the shadow, but must ensure that the no thread returns 2584 // in to the stackmap shadow. The only way to achieve this is if the call 2585 // is at the end of the shadow. 2586 if (MI->isCall()) { 2587 // Count then size of the call towards the shadow 2588 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get()); 2589 // Then flush the shadow so that we fill with nops before the call, not 2590 // after it. 2591 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 2592 // Then emit the call 2593 OutStreamer->emitInstruction(TmpInst, getSubtargetInfo()); 2594 return; 2595 } 2596 2597 EmitAndCountInstruction(TmpInst); 2598 } 2599