1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower X86 MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86AsmPrinter.h" 16 #include "InstPrinter/X86ATTInstPrinter.h" 17 #include "X86COFFMachineModuleInfo.h" 18 #include "llvm/ADT/SmallString.h" 19 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 20 #include "llvm/CodeGen/StackMaps.h" 21 #include "llvm/IR/Mangler.h" 22 #include "llvm/IR/Type.h" 23 #include "llvm/MC/MCAsmInfo.h" 24 #include "llvm/MC/MCContext.h" 25 #include "llvm/MC/MCExpr.h" 26 #include "llvm/MC/MCInst.h" 27 #include "llvm/MC/MCInstBuilder.h" 28 #include "llvm/MC/MCStreamer.h" 29 #include "llvm/MC/MCSymbol.h" 30 #include "llvm/Support/FormattedStream.h" 31 using namespace llvm; 32 33 namespace { 34 35 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 36 class X86MCInstLower { 37 MCContext &Ctx; 38 const MachineFunction &MF; 39 const TargetMachine &TM; 40 const MCAsmInfo &MAI; 41 X86AsmPrinter &AsmPrinter; 42 public: 43 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter); 44 45 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 46 47 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 48 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 49 50 private: 51 MachineModuleInfoMachO &getMachOMMI() const; 52 Mangler *getMang() const { 53 return AsmPrinter.Mang; 54 } 55 }; 56 57 } // end anonymous namespace 58 59 X86MCInstLower::X86MCInstLower(const MachineFunction &mf, 60 X86AsmPrinter &asmprinter) 61 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), 62 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {} 63 64 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 65 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 66 } 67 68 69 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 70 /// operand to an MCSymbol. 71 MCSymbol *X86MCInstLower:: 72 GetSymbolFromOperand(const MachineOperand &MO) const { 73 const DataLayout *DL = TM.getDataLayout(); 74 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"); 75 76 SmallString<128> Name; 77 StringRef Suffix; 78 79 switch (MO.getTargetFlags()) { 80 case X86II::MO_DLLIMPORT: 81 // Handle dllimport linkage. 82 Name += "__imp_"; 83 break; 84 case X86II::MO_DARWIN_STUB: 85 Suffix = "$stub"; 86 break; 87 case X86II::MO_DARWIN_NONLAZY: 88 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 89 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: 90 Suffix = "$non_lazy_ptr"; 91 break; 92 } 93 94 if (!Suffix.empty()) 95 Name += DL->getPrivateGlobalPrefix(); 96 97 unsigned PrefixLen = Name.size(); 98 99 if (MO.isGlobal()) { 100 const GlobalValue *GV = MO.getGlobal(); 101 AsmPrinter.getNameWithPrefix(Name, GV); 102 } else if (MO.isSymbol()) { 103 getMang()->getNameWithPrefix(Name, MO.getSymbolName()); 104 } else if (MO.isMBB()) { 105 Name += MO.getMBB()->getSymbol()->getName(); 106 } 107 unsigned OrigLen = Name.size() - PrefixLen; 108 109 Name += Suffix; 110 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name); 111 112 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen); 113 114 // If the target flags on the operand changes the name of the symbol, do that 115 // before we return the symbol. 116 switch (MO.getTargetFlags()) { 117 default: break; 118 case X86II::MO_DARWIN_NONLAZY: 119 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 120 MachineModuleInfoImpl::StubValueTy &StubSym = 121 getMachOMMI().getGVStubEntry(Sym); 122 if (StubSym.getPointer() == 0) { 123 assert(MO.isGlobal() && "Extern symbol not handled yet"); 124 StubSym = 125 MachineModuleInfoImpl:: 126 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 127 !MO.getGlobal()->hasInternalLinkage()); 128 } 129 break; 130 } 131 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: { 132 MachineModuleInfoImpl::StubValueTy &StubSym = 133 getMachOMMI().getHiddenGVStubEntry(Sym); 134 if (StubSym.getPointer() == 0) { 135 assert(MO.isGlobal() && "Extern symbol not handled yet"); 136 StubSym = 137 MachineModuleInfoImpl:: 138 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 139 !MO.getGlobal()->hasInternalLinkage()); 140 } 141 break; 142 } 143 case X86II::MO_DARWIN_STUB: { 144 MachineModuleInfoImpl::StubValueTy &StubSym = 145 getMachOMMI().getFnStubEntry(Sym); 146 if (StubSym.getPointer()) 147 return Sym; 148 149 if (MO.isGlobal()) { 150 StubSym = 151 MachineModuleInfoImpl:: 152 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 153 !MO.getGlobal()->hasInternalLinkage()); 154 } else { 155 StubSym = 156 MachineModuleInfoImpl:: 157 StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false); 158 } 159 break; 160 } 161 } 162 163 return Sym; 164 } 165 166 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 167 MCSymbol *Sym) const { 168 // FIXME: We would like an efficient form for this, so we don't have to do a 169 // lot of extra uniquing. 170 const MCExpr *Expr = 0; 171 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 172 173 switch (MO.getTargetFlags()) { 174 default: llvm_unreachable("Unknown target flag on GV operand"); 175 case X86II::MO_NO_FLAG: // No flag. 176 // These affect the name of the symbol, not any suffix. 177 case X86II::MO_DARWIN_NONLAZY: 178 case X86II::MO_DLLIMPORT: 179 case X86II::MO_DARWIN_STUB: 180 break; 181 182 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; 183 case X86II::MO_TLVP_PIC_BASE: 184 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 185 // Subtract the pic base. 186 Expr = MCBinaryExpr::CreateSub(Expr, 187 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), 188 Ctx), 189 Ctx); 190 break; 191 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break; 192 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 193 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break; 194 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break; 195 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 196 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 197 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 198 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break; 199 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 200 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break; 201 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 202 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 203 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 204 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 205 case X86II::MO_PIC_BASE_OFFSET: 206 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 207 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: 208 Expr = MCSymbolRefExpr::Create(Sym, Ctx); 209 // Subtract the pic base. 210 Expr = MCBinaryExpr::CreateSub(Expr, 211 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx), 212 Ctx); 213 if (MO.isJTI() && MAI.hasSetDirective()) { 214 // If .set directive is supported, use it to reduce the number of 215 // relocations the assembler will generate for differences between 216 // local labels. This is only safe when the symbols are in the same 217 // section so we are restricting it to jumptable references. 218 MCSymbol *Label = Ctx.CreateTempSymbol(); 219 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr); 220 Expr = MCSymbolRefExpr::Create(Label, Ctx); 221 } 222 break; 223 } 224 225 if (Expr == 0) 226 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx); 227 228 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 229 Expr = MCBinaryExpr::CreateAdd(Expr, 230 MCConstantExpr::Create(MO.getOffset(), Ctx), 231 Ctx); 232 return MCOperand::CreateExpr(Expr); 233 } 234 235 236 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 237 /// a short fixed-register form. 238 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 239 unsigned ImmOp = Inst.getNumOperands() - 1; 240 assert(Inst.getOperand(0).isReg() && 241 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 242 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 243 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 244 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 245 246 // Check whether the destination register can be fixed. 247 unsigned Reg = Inst.getOperand(0).getReg(); 248 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 249 return; 250 251 // If so, rewrite the instruction. 252 MCOperand Saved = Inst.getOperand(ImmOp); 253 Inst = MCInst(); 254 Inst.setOpcode(Opcode); 255 Inst.addOperand(Saved); 256 } 257 258 /// \brief If a movsx instruction has a shorter encoding for the used register 259 /// simplify the instruction to use it instead. 260 static void SimplifyMOVSX(MCInst &Inst) { 261 unsigned NewOpcode = 0; 262 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 263 switch (Inst.getOpcode()) { 264 default: 265 llvm_unreachable("Unexpected instruction!"); 266 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 267 if (Op0 == X86::AX && Op1 == X86::AL) 268 NewOpcode = X86::CBW; 269 break; 270 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 271 if (Op0 == X86::EAX && Op1 == X86::AX) 272 NewOpcode = X86::CWDE; 273 break; 274 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 275 if (Op0 == X86::RAX && Op1 == X86::EAX) 276 NewOpcode = X86::CDQE; 277 break; 278 } 279 280 if (NewOpcode != 0) { 281 Inst = MCInst(); 282 Inst.setOpcode(NewOpcode); 283 } 284 } 285 286 /// \brief Simplify things like MOV32rm to MOV32o32a. 287 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 288 unsigned Opcode) { 289 // Don't make these simplifications in 64-bit mode; other assemblers don't 290 // perform them because they make the code larger. 291 if (Printer.getSubtarget().is64Bit()) 292 return; 293 294 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 295 unsigned AddrBase = IsStore; 296 unsigned RegOp = IsStore ? 0 : 5; 297 unsigned AddrOp = AddrBase + 3; 298 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 299 Inst.getOperand(AddrBase + 0).isReg() && // base 300 Inst.getOperand(AddrBase + 1).isImm() && // scale 301 Inst.getOperand(AddrBase + 2).isReg() && // index register 302 (Inst.getOperand(AddrOp).isExpr() || // address 303 Inst.getOperand(AddrOp).isImm())&& 304 Inst.getOperand(AddrBase + 4).isReg() && // segment 305 "Unexpected instruction!"); 306 307 // Check whether the destination register can be fixed. 308 unsigned Reg = Inst.getOperand(RegOp).getReg(); 309 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 310 return; 311 312 // Check whether this is an absolute address. 313 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 314 // to do this here. 315 bool Absolute = true; 316 if (Inst.getOperand(AddrOp).isExpr()) { 317 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 318 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 319 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 320 Absolute = false; 321 } 322 323 if (Absolute && 324 (Inst.getOperand(AddrBase + 0).getReg() != 0 || 325 Inst.getOperand(AddrBase + 2).getReg() != 0 || 326 Inst.getOperand(AddrBase + 1).getImm() != 1)) 327 return; 328 329 // If so, rewrite the instruction. 330 MCOperand Saved = Inst.getOperand(AddrOp); 331 MCOperand Seg = Inst.getOperand(AddrBase + 4); 332 Inst = MCInst(); 333 Inst.setOpcode(Opcode); 334 Inst.addOperand(Saved); 335 Inst.addOperand(Seg); 336 } 337 338 static unsigned getRetOpcode(const X86Subtarget &Subtarget) 339 { 340 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 341 } 342 343 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 344 OutMI.setOpcode(MI->getOpcode()); 345 346 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 347 const MachineOperand &MO = MI->getOperand(i); 348 349 MCOperand MCOp; 350 switch (MO.getType()) { 351 default: 352 MI->dump(); 353 llvm_unreachable("unknown operand type"); 354 case MachineOperand::MO_Register: 355 // Ignore all implicit register operands. 356 if (MO.isImplicit()) continue; 357 MCOp = MCOperand::CreateReg(MO.getReg()); 358 break; 359 case MachineOperand::MO_Immediate: 360 MCOp = MCOperand::CreateImm(MO.getImm()); 361 break; 362 case MachineOperand::MO_MachineBasicBlock: 363 case MachineOperand::MO_GlobalAddress: 364 case MachineOperand::MO_ExternalSymbol: 365 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 366 break; 367 case MachineOperand::MO_JumpTableIndex: 368 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 369 break; 370 case MachineOperand::MO_ConstantPoolIndex: 371 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 372 break; 373 case MachineOperand::MO_BlockAddress: 374 MCOp = LowerSymbolOperand(MO, 375 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 376 break; 377 case MachineOperand::MO_RegisterMask: 378 // Ignore call clobbers. 379 continue; 380 } 381 382 OutMI.addOperand(MCOp); 383 } 384 385 // Handle a few special cases to eliminate operand modifiers. 386 ReSimplify: 387 switch (OutMI.getOpcode()) { 388 case X86::LEA64_32r: 389 case X86::LEA64r: 390 case X86::LEA16r: 391 case X86::LEA32r: 392 // LEA should have a segment register, but it must be empty. 393 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && 394 "Unexpected # of LEA operands"); 395 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && 396 "LEA has segment specified!"); 397 break; 398 399 case X86::MOV32ri64: 400 OutMI.setOpcode(X86::MOV32ri); 401 break; 402 403 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 404 // if one of the registers is extended, but other isn't. 405 case X86::VMOVAPDrr: 406 case X86::VMOVAPDYrr: 407 case X86::VMOVAPSrr: 408 case X86::VMOVAPSYrr: 409 case X86::VMOVDQArr: 410 case X86::VMOVDQAYrr: 411 case X86::VMOVDQUrr: 412 case X86::VMOVDQUYrr: 413 case X86::VMOVUPDrr: 414 case X86::VMOVUPDYrr: 415 case X86::VMOVUPSrr: 416 case X86::VMOVUPSYrr: { 417 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 418 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 419 unsigned NewOpc; 420 switch (OutMI.getOpcode()) { 421 default: llvm_unreachable("Invalid opcode"); 422 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 423 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 424 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 425 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 426 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 427 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 428 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 429 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 430 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 431 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 432 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 433 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 434 } 435 OutMI.setOpcode(NewOpc); 436 } 437 break; 438 } 439 case X86::VMOVSDrr: 440 case X86::VMOVSSrr: { 441 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 442 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 443 unsigned NewOpc; 444 switch (OutMI.getOpcode()) { 445 default: llvm_unreachable("Invalid opcode"); 446 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 447 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 448 } 449 OutMI.setOpcode(NewOpc); 450 } 451 break; 452 } 453 454 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 455 // inputs modeled as normal uses instead of implicit uses. As such, truncate 456 // off all but the first operand (the callee). FIXME: Change isel. 457 case X86::TAILJMPr64: 458 case X86::CALL64r: 459 case X86::CALL64pcrel32: { 460 unsigned Opcode = OutMI.getOpcode(); 461 MCOperand Saved = OutMI.getOperand(0); 462 OutMI = MCInst(); 463 OutMI.setOpcode(Opcode); 464 OutMI.addOperand(Saved); 465 break; 466 } 467 468 case X86::EH_RETURN: 469 case X86::EH_RETURN64: { 470 OutMI = MCInst(); 471 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 472 break; 473 } 474 475 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions. 476 case X86::TAILJMPr: 477 case X86::TAILJMPd: 478 case X86::TAILJMPd64: { 479 unsigned Opcode; 480 switch (OutMI.getOpcode()) { 481 default: llvm_unreachable("Invalid opcode"); 482 case X86::TAILJMPr: Opcode = X86::JMP32r; break; 483 case X86::TAILJMPd: 484 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; 485 } 486 487 MCOperand Saved = OutMI.getOperand(0); 488 OutMI = MCInst(); 489 OutMI.setOpcode(Opcode); 490 OutMI.addOperand(Saved); 491 break; 492 } 493 494 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 495 // this with an ugly goto in case the resultant OR uses EAX and needs the 496 // short form. 497 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 498 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 499 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 500 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 501 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 502 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 503 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 504 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 505 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 506 507 // The assembler backend wants to see branches in their small form and relax 508 // them to their large form. The JIT can only handle the large form because 509 // it does not do relaxation. For now, translate the large form to the 510 // small one here. 511 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break; 512 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break; 513 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break; 514 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break; 515 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break; 516 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break; 517 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break; 518 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break; 519 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break; 520 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break; 521 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break; 522 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break; 523 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break; 524 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break; 525 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break; 526 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break; 527 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break; 528 529 // Atomic load and store require a separate pseudo-inst because Acquire 530 // implies mayStore and Release implies mayLoad; fix these to regular MOV 531 // instructions here 532 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; 533 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; 534 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; 535 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; 536 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; 537 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; 538 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; 539 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; 540 541 // We don't currently select the correct instruction form for instructions 542 // which have a short %eax, etc. form. Handle this by custom lowering, for 543 // now. 544 // 545 // Note, we are currently not handling the following instructions: 546 // MOV64ao8, MOV64o8a 547 // XCHG16ar, XCHG32ar, XCHG64ar 548 case X86::MOV8mr_NOREX: 549 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break; 550 case X86::MOV8rm_NOREX: 551 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break; 552 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break; 553 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break; 554 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break; 555 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break; 556 557 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break; 558 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break; 559 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break; 560 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break; 561 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break; 562 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break; 563 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break; 564 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break; 565 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break; 566 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break; 567 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break; 568 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break; 569 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break; 570 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break; 571 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break; 572 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break; 573 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break; 574 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break; 575 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break; 576 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break; 577 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break; 578 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break; 579 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break; 580 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break; 581 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break; 582 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break; 583 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break; 584 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break; 585 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break; 586 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break; 587 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break; 588 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break; 589 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break; 590 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break; 591 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break; 592 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break; 593 594 // Try to shrink some forms of movsx. 595 case X86::MOVSX16rr8: 596 case X86::MOVSX32rr16: 597 case X86::MOVSX64rr32: 598 SimplifyMOVSX(OutMI); 599 break; 600 } 601 } 602 603 static void LowerTlsAddr(MCStreamer &OutStreamer, 604 X86MCInstLower &MCInstLowering, 605 const MachineInstr &MI, 606 const MCSubtargetInfo& STI) { 607 608 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || 609 MI.getOpcode() == X86::TLS_base_addr64; 610 611 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; 612 613 MCContext &context = OutStreamer.getContext(); 614 615 if (needsPadding) 616 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); 617 618 MCSymbolRefExpr::VariantKind SRVK; 619 switch (MI.getOpcode()) { 620 case X86::TLS_addr32: 621 case X86::TLS_addr64: 622 SRVK = MCSymbolRefExpr::VK_TLSGD; 623 break; 624 case X86::TLS_base_addr32: 625 SRVK = MCSymbolRefExpr::VK_TLSLDM; 626 break; 627 case X86::TLS_base_addr64: 628 SRVK = MCSymbolRefExpr::VK_TLSLD; 629 break; 630 default: 631 llvm_unreachable("unexpected opcode"); 632 } 633 634 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 635 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context); 636 637 MCInst LEA; 638 if (is64Bits) { 639 LEA.setOpcode(X86::LEA64r); 640 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest 641 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base 642 LEA.addOperand(MCOperand::CreateImm(1)); // scale 643 LEA.addOperand(MCOperand::CreateReg(0)); // index 644 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 645 LEA.addOperand(MCOperand::CreateReg(0)); // seg 646 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) { 647 LEA.setOpcode(X86::LEA32r); 648 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 649 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base 650 LEA.addOperand(MCOperand::CreateImm(1)); // scale 651 LEA.addOperand(MCOperand::CreateReg(0)); // index 652 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 653 LEA.addOperand(MCOperand::CreateReg(0)); // seg 654 } else { 655 LEA.setOpcode(X86::LEA32r); 656 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 657 LEA.addOperand(MCOperand::CreateReg(0)); // base 658 LEA.addOperand(MCOperand::CreateImm(1)); // scale 659 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index 660 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 661 LEA.addOperand(MCOperand::CreateReg(0)); // seg 662 } 663 OutStreamer.EmitInstruction(LEA, STI); 664 665 if (needsPadding) { 666 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); 667 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); 668 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI); 669 } 670 671 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 672 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name); 673 const MCSymbolRefExpr *tlsRef = 674 MCSymbolRefExpr::Create(tlsGetAddr, 675 MCSymbolRefExpr::VK_PLT, 676 context); 677 678 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 679 : X86::CALLpcrel32) 680 .addExpr(tlsRef), STI); 681 } 682 683 /// \brief Emit the optimal amount of multi-byte nops on X86. 684 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) { 685 // This works only for 64bit. For 32bit we have to do additional checking if 686 // the CPU supports multi-byte nops. 687 assert(Is64Bit && "EmitNops only supports X86-64"); 688 while (NumBytes) { 689 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; 690 Opc = IndexReg = Displacement = SegmentReg = 0; 691 BaseReg = X86::RAX; ScaleVal = 1; 692 switch (NumBytes) { 693 case 0: llvm_unreachable("Zero nops?"); break; 694 case 1: NumBytes -= 1; Opc = X86::NOOP; break; 695 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break; 696 case 3: NumBytes -= 3; Opc = X86::NOOPL; break; 697 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break; 698 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8; 699 IndexReg = X86::RAX; break; 700 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8; 701 IndexReg = X86::RAX; break; 702 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break; 703 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512; 704 IndexReg = X86::RAX; break; 705 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512; 706 IndexReg = X86::RAX; break; 707 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512; 708 IndexReg = X86::RAX; SegmentReg = X86::CS; break; 709 } 710 711 unsigned NumPrefixes = std::min(NumBytes, 5U); 712 NumBytes -= NumPrefixes; 713 for (unsigned i = 0; i != NumPrefixes; ++i) 714 OS.EmitBytes("\x66"); 715 716 switch (Opc) { 717 default: llvm_unreachable("Unexpected opcode"); break; 718 case X86::NOOP: 719 OS.EmitInstruction(MCInstBuilder(Opc), STI); 720 break; 721 case X86::XCHG16ar: 722 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); 723 break; 724 case X86::NOOPL: 725 case X86::NOOPW: 726 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal) 727 .addReg(IndexReg) 728 .addImm(Displacement) 729 .addReg(SegmentReg), STI); 730 break; 731 } 732 } // while (NumBytes) 733 } 734 735 // Lower a stackmap of the form: 736 // <id>, <shadowBytes>, ... 737 static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM, 738 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) { 739 unsigned NumBytes = MI.getOperand(1).getImm(); 740 SM.recordStackMap(MI); 741 // Emit padding. 742 // FIXME: These nops ensure that the stackmap's shadow is covered by 743 // instructions from the same basic block, but the nops should not be 744 // necessary if instructions from the same block follow the stackmap. 745 EmitNops(OS, NumBytes, Is64Bit, STI); 746 } 747 748 // Lower a patchpoint of the form: 749 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ... 750 static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM, 751 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) { 752 assert(Is64Bit && "Patchpoint currently only supports X86-64"); 753 SM.recordPatchPoint(MI); 754 755 PatchPointOpers opers(&MI); 756 unsigned ScratchIdx = opers.getNextScratchIdx(); 757 unsigned EncodedBytes = 0; 758 int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm(); 759 if (CallTarget) { 760 // Emit MOV to materialize the target address and the CALL to target. 761 // This is encoded with 12-13 bytes, depending on which register is used. 762 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg(); 763 if (X86II::isX86_64ExtendedReg(ScratchReg)) 764 EncodedBytes = 13; 765 else 766 EncodedBytes = 12; 767 OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg) 768 .addImm(CallTarget), STI); 769 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI); 770 } 771 // Emit padding. 772 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm(); 773 assert(NumBytes >= EncodedBytes && 774 "Patchpoint can't request size less than the length of a call."); 775 776 EmitNops(OS, NumBytes - EncodedBytes, Is64Bit, STI); 777 } 778 779 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 780 X86MCInstLower MCInstLowering(*MF, *this); 781 switch (MI->getOpcode()) { 782 case TargetOpcode::DBG_VALUE: 783 llvm_unreachable("Should be handled target independently"); 784 785 // Emit nothing here but a comment if we can. 786 case X86::Int_MemBarrier: 787 OutStreamer.emitRawComment("MEMBARRIER"); 788 return; 789 790 791 case X86::EH_RETURN: 792 case X86::EH_RETURN64: { 793 // Lower these as normal, but add some comments. 794 unsigned Reg = MI->getOperand(0).getReg(); 795 OutStreamer.AddComment(StringRef("eh_return, addr: %") + 796 X86ATTInstPrinter::getRegisterName(Reg)); 797 break; 798 } 799 case X86::TAILJMPr: 800 case X86::TAILJMPd: 801 case X86::TAILJMPd64: 802 // Lower these as normal, but add some comments. 803 OutStreamer.AddComment("TAILCALL"); 804 break; 805 806 case X86::TLS_addr32: 807 case X86::TLS_addr64: 808 case X86::TLS_base_addr32: 809 case X86::TLS_base_addr64: 810 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI, getSubtargetInfo()); 811 812 case X86::MOVPC32r: { 813 // This is a pseudo op for a two instruction sequence with a label, which 814 // looks like: 815 // call "L1$pb" 816 // "L1$pb": 817 // popl %esi 818 819 // Emit the call. 820 MCSymbol *PICBase = MF->getPICBaseSymbol(); 821 // FIXME: We would like an efficient form for this, so we don't have to do a 822 // lot of extra uniquing. 823 EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32) 824 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext))); 825 826 // Emit the label. 827 OutStreamer.EmitLabel(PICBase); 828 829 // popl $reg 830 EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r) 831 .addReg(MI->getOperand(0).getReg())); 832 return; 833 } 834 835 case X86::ADD32ri: { 836 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 837 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 838 break; 839 840 // Okay, we have something like: 841 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 842 843 // For this, we want to print something like: 844 // MYGLOBAL + (. - PICBASE) 845 // However, we can't generate a ".", so just emit a new label here and refer 846 // to it. 847 MCSymbol *DotSym = OutContext.CreateTempSymbol(); 848 OutStreamer.EmitLabel(DotSym); 849 850 // Now that we have emitted the label, lower the complex operand expression. 851 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 852 853 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); 854 const MCExpr *PICBase = 855 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext); 856 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext); 857 858 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), 859 DotExpr, OutContext); 860 861 EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri) 862 .addReg(MI->getOperand(0).getReg()) 863 .addReg(MI->getOperand(1).getReg()) 864 .addExpr(DotExpr)); 865 return; 866 } 867 868 case TargetOpcode::STACKMAP: 869 return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo()); 870 871 case TargetOpcode::PATCHPOINT: 872 return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo()); 873 874 case X86::MORESTACK_RET: 875 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget))); 876 return; 877 878 case X86::MORESTACK_RET_RESTORE_R10: 879 // Return, then restore R10. 880 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget))); 881 EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr) 882 .addReg(X86::R10) 883 .addReg(X86::RAX)); 884 return; 885 } 886 887 MCInst TmpInst; 888 MCInstLowering.Lower(MI, TmpInst); 889 EmitToStreamer(OutStreamer, TmpInst); 890 } 891