1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/MC/MCInstBuilder.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/Support/TargetRegistry.h"
38 using namespace llvm;
39 
40 namespace {
41 
42 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
43 class X86MCInstLower {
44   MCContext &Ctx;
45   const MachineFunction &MF;
46   const TargetMachine &TM;
47   const MCAsmInfo &MAI;
48   X86AsmPrinter &AsmPrinter;
49 public:
50   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
51 
52   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
53 
54   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
55   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
56 
57 private:
58   MachineModuleInfoMachO &getMachOMMI() const;
59   Mangler *getMang() const {
60     return AsmPrinter.Mang;
61   }
62 };
63 
64 } // end anonymous namespace
65 
66 // Emit a minimal sequence of nops spanning NumBytes bytes.
67 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
68                      const MCSubtargetInfo &STI);
69 
70 namespace llvm {
71    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
72      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
73 
74   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
75 
76   void
77   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &MF) {
78     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
79         *TM.getSubtargetImpl()->getInstrInfo(),
80         *TM.getSubtargetImpl()->getRegisterInfo(), *TM.getSubtargetImpl(),
81         MF.getContext()));
82   }
83 
84   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
85                                                    const MCSubtargetInfo &STI) {
86     if (InShadow) {
87       SmallString<256> Code;
88       SmallVector<MCFixup, 4> Fixups;
89       raw_svector_ostream VecOS(Code);
90       CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
91       VecOS.flush();
92       CurrentShadowSize += Code.size();
93       if (CurrentShadowSize >= RequiredShadowSize)
94         InShadow = false; // The shadow is big enough. Stop counting.
95     }
96   }
97 
98   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
99     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
100     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
101       InShadow = false;
102       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
103                TM.getSubtarget<X86Subtarget>().is64Bit(), STI);
104     }
105   }
106 
107   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
108     OutStreamer.EmitInstruction(Inst, getSubtargetInfo());
109     SMShadowTracker.count(Inst, getSubtargetInfo());
110   }
111 } // end llvm namespace
112 
113 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
114                                X86AsmPrinter &asmprinter)
115 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
116   MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
117 
118 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
119   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
120 }
121 
122 
123 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
124 /// operand to an MCSymbol.
125 MCSymbol *X86MCInstLower::
126 GetSymbolFromOperand(const MachineOperand &MO) const {
127   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
128   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
129 
130   SmallString<128> Name;
131   StringRef Suffix;
132 
133   switch (MO.getTargetFlags()) {
134   case X86II::MO_DLLIMPORT:
135     // Handle dllimport linkage.
136     Name += "__imp_";
137     break;
138   case X86II::MO_DARWIN_STUB:
139     Suffix = "$stub";
140     break;
141   case X86II::MO_DARWIN_NONLAZY:
142   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
143   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
144     Suffix = "$non_lazy_ptr";
145     break;
146   }
147 
148   if (!Suffix.empty())
149     Name += DL->getPrivateGlobalPrefix();
150 
151   unsigned PrefixLen = Name.size();
152 
153   if (MO.isGlobal()) {
154     const GlobalValue *GV = MO.getGlobal();
155     AsmPrinter.getNameWithPrefix(Name, GV);
156   } else if (MO.isSymbol()) {
157     getMang()->getNameWithPrefix(Name, MO.getSymbolName());
158   } else if (MO.isMBB()) {
159     Name += MO.getMBB()->getSymbol()->getName();
160   }
161   unsigned OrigLen = Name.size() - PrefixLen;
162 
163   Name += Suffix;
164   MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
165 
166   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
167 
168   // If the target flags on the operand changes the name of the symbol, do that
169   // before we return the symbol.
170   switch (MO.getTargetFlags()) {
171   default: break;
172   case X86II::MO_DARWIN_NONLAZY:
173   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
174     MachineModuleInfoImpl::StubValueTy &StubSym =
175       getMachOMMI().getGVStubEntry(Sym);
176     if (!StubSym.getPointer()) {
177       assert(MO.isGlobal() && "Extern symbol not handled yet");
178       StubSym =
179         MachineModuleInfoImpl::
180         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
181                     !MO.getGlobal()->hasInternalLinkage());
182     }
183     break;
184   }
185   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
186     MachineModuleInfoImpl::StubValueTy &StubSym =
187       getMachOMMI().getHiddenGVStubEntry(Sym);
188     if (!StubSym.getPointer()) {
189       assert(MO.isGlobal() && "Extern symbol not handled yet");
190       StubSym =
191         MachineModuleInfoImpl::
192         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
193                     !MO.getGlobal()->hasInternalLinkage());
194     }
195     break;
196   }
197   case X86II::MO_DARWIN_STUB: {
198     MachineModuleInfoImpl::StubValueTy &StubSym =
199       getMachOMMI().getFnStubEntry(Sym);
200     if (StubSym.getPointer())
201       return Sym;
202 
203     if (MO.isGlobal()) {
204       StubSym =
205         MachineModuleInfoImpl::
206         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
207                     !MO.getGlobal()->hasInternalLinkage());
208     } else {
209       StubSym =
210         MachineModuleInfoImpl::
211         StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
212     }
213     break;
214   }
215   }
216 
217   return Sym;
218 }
219 
220 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
221                                              MCSymbol *Sym) const {
222   // FIXME: We would like an efficient form for this, so we don't have to do a
223   // lot of extra uniquing.
224   const MCExpr *Expr = nullptr;
225   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
226 
227   switch (MO.getTargetFlags()) {
228   default: llvm_unreachable("Unknown target flag on GV operand");
229   case X86II::MO_NO_FLAG:    // No flag.
230   // These affect the name of the symbol, not any suffix.
231   case X86II::MO_DARWIN_NONLAZY:
232   case X86II::MO_DLLIMPORT:
233   case X86II::MO_DARWIN_STUB:
234     break;
235 
236   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
237   case X86II::MO_TLVP_PIC_BASE:
238     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
239     // Subtract the pic base.
240     Expr = MCBinaryExpr::CreateSub(Expr,
241                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
242                                                            Ctx),
243                                    Ctx);
244     break;
245   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
246   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
247   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
248   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
249   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
250   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
251   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
252   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
253   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
254   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
255   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
256   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
257   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
258   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
259   case X86II::MO_PIC_BASE_OFFSET:
260   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
261   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
262     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
263     // Subtract the pic base.
264     Expr = MCBinaryExpr::CreateSub(Expr,
265                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
266                                    Ctx);
267     if (MO.isJTI()) {
268       assert(MAI.doesSetDirectiveSuppressesReloc());
269       // If .set directive is supported, use it to reduce the number of
270       // relocations the assembler will generate for differences between
271       // local labels. This is only safe when the symbols are in the same
272       // section so we are restricting it to jumptable references.
273       MCSymbol *Label = Ctx.CreateTempSymbol();
274       AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
275       Expr = MCSymbolRefExpr::Create(Label, Ctx);
276     }
277     break;
278   }
279 
280   if (!Expr)
281     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
282 
283   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
284     Expr = MCBinaryExpr::CreateAdd(Expr,
285                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
286                                    Ctx);
287   return MCOperand::CreateExpr(Expr);
288 }
289 
290 
291 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
292 /// a short fixed-register form.
293 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
294   unsigned ImmOp = Inst.getNumOperands() - 1;
295   assert(Inst.getOperand(0).isReg() &&
296          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
297          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
298            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
299           Inst.getNumOperands() == 2) && "Unexpected instruction!");
300 
301   // Check whether the destination register can be fixed.
302   unsigned Reg = Inst.getOperand(0).getReg();
303   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
304     return;
305 
306   // If so, rewrite the instruction.
307   MCOperand Saved = Inst.getOperand(ImmOp);
308   Inst = MCInst();
309   Inst.setOpcode(Opcode);
310   Inst.addOperand(Saved);
311 }
312 
313 /// \brief If a movsx instruction has a shorter encoding for the used register
314 /// simplify the instruction to use it instead.
315 static void SimplifyMOVSX(MCInst &Inst) {
316   unsigned NewOpcode = 0;
317   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
318   switch (Inst.getOpcode()) {
319   default:
320     llvm_unreachable("Unexpected instruction!");
321   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
322     if (Op0 == X86::AX && Op1 == X86::AL)
323       NewOpcode = X86::CBW;
324     break;
325   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
326     if (Op0 == X86::EAX && Op1 == X86::AX)
327       NewOpcode = X86::CWDE;
328     break;
329   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
330     if (Op0 == X86::RAX && Op1 == X86::EAX)
331       NewOpcode = X86::CDQE;
332     break;
333   }
334 
335   if (NewOpcode != 0) {
336     Inst = MCInst();
337     Inst.setOpcode(NewOpcode);
338   }
339 }
340 
341 /// \brief Simplify things like MOV32rm to MOV32o32a.
342 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
343                                   unsigned Opcode) {
344   // Don't make these simplifications in 64-bit mode; other assemblers don't
345   // perform them because they make the code larger.
346   if (Printer.getSubtarget().is64Bit())
347     return;
348 
349   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
350   unsigned AddrBase = IsStore;
351   unsigned RegOp = IsStore ? 0 : 5;
352   unsigned AddrOp = AddrBase + 3;
353   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
354          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
355          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
356          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
357          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
358          (Inst.getOperand(AddrOp).isExpr() ||
359           Inst.getOperand(AddrOp).isImm()) &&
360          "Unexpected instruction!");
361 
362   // Check whether the destination register can be fixed.
363   unsigned Reg = Inst.getOperand(RegOp).getReg();
364   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
365     return;
366 
367   // Check whether this is an absolute address.
368   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
369   // to do this here.
370   bool Absolute = true;
371   if (Inst.getOperand(AddrOp).isExpr()) {
372     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
373     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
374       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
375         Absolute = false;
376   }
377 
378   if (Absolute &&
379       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
380        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
381        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
382     return;
383 
384   // If so, rewrite the instruction.
385   MCOperand Saved = Inst.getOperand(AddrOp);
386   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
387   Inst = MCInst();
388   Inst.setOpcode(Opcode);
389   Inst.addOperand(Saved);
390   Inst.addOperand(Seg);
391 }
392 
393 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
394 {
395 	return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
396 }
397 
398 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
399   OutMI.setOpcode(MI->getOpcode());
400 
401   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
402     const MachineOperand &MO = MI->getOperand(i);
403 
404     MCOperand MCOp;
405     switch (MO.getType()) {
406     default:
407       MI->dump();
408       llvm_unreachable("unknown operand type");
409     case MachineOperand::MO_Register:
410       // Ignore all implicit register operands.
411       if (MO.isImplicit()) continue;
412       MCOp = MCOperand::CreateReg(MO.getReg());
413       break;
414     case MachineOperand::MO_Immediate:
415       MCOp = MCOperand::CreateImm(MO.getImm());
416       break;
417     case MachineOperand::MO_MachineBasicBlock:
418     case MachineOperand::MO_GlobalAddress:
419     case MachineOperand::MO_ExternalSymbol:
420       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
421       break;
422     case MachineOperand::MO_JumpTableIndex:
423       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
424       break;
425     case MachineOperand::MO_ConstantPoolIndex:
426       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
427       break;
428     case MachineOperand::MO_BlockAddress:
429       MCOp = LowerSymbolOperand(MO,
430                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
431       break;
432     case MachineOperand::MO_RegisterMask:
433       // Ignore call clobbers.
434       continue;
435     }
436 
437     OutMI.addOperand(MCOp);
438   }
439 
440   // Handle a few special cases to eliminate operand modifiers.
441 ReSimplify:
442   switch (OutMI.getOpcode()) {
443   case X86::LEA64_32r:
444   case X86::LEA64r:
445   case X86::LEA16r:
446   case X86::LEA32r:
447     // LEA should have a segment register, but it must be empty.
448     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
449            "Unexpected # of LEA operands");
450     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
451            "LEA has segment specified!");
452     break;
453 
454   case X86::MOV32ri64:
455     OutMI.setOpcode(X86::MOV32ri);
456     break;
457 
458   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
459   // if one of the registers is extended, but other isn't.
460   case X86::VMOVAPDrr:
461   case X86::VMOVAPDYrr:
462   case X86::VMOVAPSrr:
463   case X86::VMOVAPSYrr:
464   case X86::VMOVDQArr:
465   case X86::VMOVDQAYrr:
466   case X86::VMOVDQUrr:
467   case X86::VMOVDQUYrr:
468   case X86::VMOVUPDrr:
469   case X86::VMOVUPDYrr:
470   case X86::VMOVUPSrr:
471   case X86::VMOVUPSYrr: {
472     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
473         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
474       unsigned NewOpc;
475       switch (OutMI.getOpcode()) {
476       default: llvm_unreachable("Invalid opcode");
477       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
478       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
479       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
480       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
481       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
482       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
483       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
484       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
485       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
486       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
487       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
488       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
489       }
490       OutMI.setOpcode(NewOpc);
491     }
492     break;
493   }
494   case X86::VMOVSDrr:
495   case X86::VMOVSSrr: {
496     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
497         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
498       unsigned NewOpc;
499       switch (OutMI.getOpcode()) {
500       default: llvm_unreachable("Invalid opcode");
501       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
502       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
503       }
504       OutMI.setOpcode(NewOpc);
505     }
506     break;
507   }
508 
509   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
510   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
511   // off all but the first operand (the callee).  FIXME: Change isel.
512   case X86::TAILJMPr64:
513   case X86::CALL64r:
514   case X86::CALL64pcrel32: {
515     unsigned Opcode = OutMI.getOpcode();
516     MCOperand Saved = OutMI.getOperand(0);
517     OutMI = MCInst();
518     OutMI.setOpcode(Opcode);
519     OutMI.addOperand(Saved);
520     break;
521   }
522 
523   case X86::EH_RETURN:
524   case X86::EH_RETURN64: {
525     OutMI = MCInst();
526     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
527     break;
528   }
529 
530   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
531   case X86::TAILJMPr:
532   case X86::TAILJMPd:
533   case X86::TAILJMPd64: {
534     unsigned Opcode;
535     switch (OutMI.getOpcode()) {
536     default: llvm_unreachable("Invalid opcode");
537     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
538     case X86::TAILJMPd:
539     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
540     }
541 
542     MCOperand Saved = OutMI.getOperand(0);
543     OutMI = MCInst();
544     OutMI.setOpcode(Opcode);
545     OutMI.addOperand(Saved);
546     break;
547   }
548 
549   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
550   // this with an ugly goto in case the resultant OR uses EAX and needs the
551   // short form.
552   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
553   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
554   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
555   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
556   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
557   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
558   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
559   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
560   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
561 
562   // The assembler backend wants to see branches in their small form and relax
563   // them to their large form.  The JIT can only handle the large form because
564   // it does not do relaxation.  For now, translate the large form to the
565   // small one here.
566   case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
567   case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
568   case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
569   case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
570   case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
571   case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
572   case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
573   case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
574   case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
575   case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
576   case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
577   case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
578   case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
579   case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
580   case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
581   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
582   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
583 
584   // Atomic load and store require a separate pseudo-inst because Acquire
585   // implies mayStore and Release implies mayLoad; fix these to regular MOV
586   // instructions here
587   case X86::ACQUIRE_MOV8rm:    OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
588   case X86::ACQUIRE_MOV16rm:   OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
589   case X86::ACQUIRE_MOV32rm:   OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
590   case X86::ACQUIRE_MOV64rm:   OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
591   case X86::RELEASE_MOV8mr:    OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
592   case X86::RELEASE_MOV16mr:   OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
593   case X86::RELEASE_MOV32mr:   OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
594   case X86::RELEASE_MOV64mr:   OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
595   case X86::RELEASE_MOV8mi:    OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
596   case X86::RELEASE_MOV16mi:   OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
597   case X86::RELEASE_MOV32mi:   OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
598   case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
599   case X86::RELEASE_ADD8mi:    OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
600   case X86::RELEASE_ADD32mi:   OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
601   case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
602   case X86::RELEASE_AND8mi:    OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
603   case X86::RELEASE_AND32mi:   OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
604   case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
605   case X86::RELEASE_OR8mi:     OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
606   case X86::RELEASE_OR32mi:    OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
607   case X86::RELEASE_OR64mi32:  OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
608   case X86::RELEASE_XOR8mi:    OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
609   case X86::RELEASE_XOR32mi:   OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
610   case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
611   case X86::RELEASE_INC8m:     OutMI.setOpcode(X86::INC8m); goto ReSimplify;
612   case X86::RELEASE_INC16m:    OutMI.setOpcode(X86::INC16m); goto ReSimplify;
613   case X86::RELEASE_INC32m:    OutMI.setOpcode(X86::INC32m); goto ReSimplify;
614   case X86::RELEASE_INC64m:    OutMI.setOpcode(X86::INC64m); goto ReSimplify;
615   case X86::RELEASE_DEC8m:     OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
616   case X86::RELEASE_DEC16m:    OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
617   case X86::RELEASE_DEC32m:    OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
618   case X86::RELEASE_DEC64m:    OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
619 
620   // We don't currently select the correct instruction form for instructions
621   // which have a short %eax, etc. form. Handle this by custom lowering, for
622   // now.
623   //
624   // Note, we are currently not handling the following instructions:
625   // MOV64ao8, MOV64o8a
626   // XCHG16ar, XCHG32ar, XCHG64ar
627   case X86::MOV8mr_NOREX:
628   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
629   case X86::MOV8rm_NOREX:
630   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
631   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
632   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
633   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
634   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
635 
636   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
637   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
638   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
639   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
640   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
641   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
642   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
643   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
644   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
645   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
646   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
647   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
648   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
649   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
650   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
651   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
652   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
653   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
654   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
655   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
656   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
657   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
658   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
659   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
660   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
661   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
662   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
663   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
664   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
665   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
666   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
667   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
668   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
669   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
670   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
671   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
672 
673   // Try to shrink some forms of movsx.
674   case X86::MOVSX16rr8:
675   case X86::MOVSX32rr16:
676   case X86::MOVSX64rr32:
677     SimplifyMOVSX(OutMI);
678     break;
679   }
680 }
681 
682 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
683                                  const MachineInstr &MI) {
684 
685   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
686                   MI.getOpcode() == X86::TLS_base_addr64;
687 
688   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
689 
690   MCContext &context = OutStreamer.getContext();
691 
692   if (needsPadding)
693     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
694 
695   MCSymbolRefExpr::VariantKind SRVK;
696   switch (MI.getOpcode()) {
697     case X86::TLS_addr32:
698     case X86::TLS_addr64:
699       SRVK = MCSymbolRefExpr::VK_TLSGD;
700       break;
701     case X86::TLS_base_addr32:
702       SRVK = MCSymbolRefExpr::VK_TLSLDM;
703       break;
704     case X86::TLS_base_addr64:
705       SRVK = MCSymbolRefExpr::VK_TLSLD;
706       break;
707     default:
708       llvm_unreachable("unexpected opcode");
709   }
710 
711   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
712   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
713 
714   MCInst LEA;
715   if (is64Bits) {
716     LEA.setOpcode(X86::LEA64r);
717     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
718     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
719     LEA.addOperand(MCOperand::CreateImm(1));        // scale
720     LEA.addOperand(MCOperand::CreateReg(0));        // index
721     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
722     LEA.addOperand(MCOperand::CreateReg(0));        // seg
723   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
724     LEA.setOpcode(X86::LEA32r);
725     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
726     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
727     LEA.addOperand(MCOperand::CreateImm(1));        // scale
728     LEA.addOperand(MCOperand::CreateReg(0));        // index
729     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
730     LEA.addOperand(MCOperand::CreateReg(0));        // seg
731   } else {
732     LEA.setOpcode(X86::LEA32r);
733     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
734     LEA.addOperand(MCOperand::CreateReg(0));        // base
735     LEA.addOperand(MCOperand::CreateImm(1));        // scale
736     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
737     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
738     LEA.addOperand(MCOperand::CreateReg(0));        // seg
739   }
740   EmitAndCountInstruction(LEA);
741 
742   if (needsPadding) {
743     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
744     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
745     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
746   }
747 
748   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
749   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
750   const MCSymbolRefExpr *tlsRef =
751     MCSymbolRefExpr::Create(tlsGetAddr,
752                             MCSymbolRefExpr::VK_PLT,
753                             context);
754 
755   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
756                                                  : X86::CALLpcrel32)
757                             .addExpr(tlsRef));
758 }
759 
760 /// \brief Emit the optimal amount of multi-byte nops on X86.
761 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
762   // This works only for 64bit. For 32bit we have to do additional checking if
763   // the CPU supports multi-byte nops.
764   assert(Is64Bit && "EmitNops only supports X86-64");
765   while (NumBytes) {
766     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
767     Opc = IndexReg = Displacement = SegmentReg = 0;
768     BaseReg = X86::RAX; ScaleVal = 1;
769     switch (NumBytes) {
770     case  0: llvm_unreachable("Zero nops?"); break;
771     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
772     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
773     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
774     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
775     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
776              IndexReg = X86::RAX; break;
777     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
778              IndexReg = X86::RAX; break;
779     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
780     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
781              IndexReg = X86::RAX; break;
782     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
783              IndexReg = X86::RAX; break;
784     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
785              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
786     }
787 
788     unsigned NumPrefixes = std::min(NumBytes, 5U);
789     NumBytes -= NumPrefixes;
790     for (unsigned i = 0; i != NumPrefixes; ++i)
791       OS.EmitBytes("\x66");
792 
793     switch (Opc) {
794     default: llvm_unreachable("Unexpected opcode"); break;
795     case X86::NOOP:
796       OS.EmitInstruction(MCInstBuilder(Opc), STI);
797       break;
798     case X86::XCHG16ar:
799       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
800       break;
801     case X86::NOOPL:
802     case X86::NOOPW:
803       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
804                          .addImm(ScaleVal).addReg(IndexReg)
805                          .addImm(Displacement).addReg(SegmentReg), STI);
806       break;
807     }
808   } // while (NumBytes)
809 }
810 
811 // Lower a stackmap of the form:
812 // <id>, <shadowBytes>, ...
813 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
814   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
815   SM.recordStackMap(MI);
816   unsigned NumShadowBytes = MI.getOperand(1).getImm();
817   SMShadowTracker.reset(NumShadowBytes);
818 }
819 
820 // Lower a patchpoint of the form:
821 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
822 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI) {
823   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
824 
825   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
826 
827   SM.recordPatchPoint(MI);
828 
829   PatchPointOpers opers(&MI);
830   unsigned ScratchIdx = opers.getNextScratchIdx();
831   unsigned EncodedBytes = 0;
832   int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
833   if (CallTarget) {
834     // Emit MOV to materialize the target address and the CALL to target.
835     // This is encoded with 12-13 bytes, depending on which register is used.
836     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
837     if (X86II::isX86_64ExtendedReg(ScratchReg))
838       EncodedBytes = 13;
839     else
840       EncodedBytes = 12;
841     EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
842                                                        .addImm(CallTarget));
843     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
844   }
845   // Emit padding.
846   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
847   assert(NumBytes >= EncodedBytes &&
848          "Patchpoint can't request size less than the length of a call.");
849 
850   EmitNops(OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
851            getSubtargetInfo());
852 }
853 
854 // Returns instruction preceding MBBI in MachineFunction.
855 // If MBBI is the first instruction of the first basic block, returns null.
856 static MachineBasicBlock::const_iterator
857 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
858   const MachineBasicBlock *MBB = MBBI->getParent();
859   while (MBBI == MBB->begin()) {
860     if (MBB == MBB->getParent()->begin())
861       return nullptr;
862     MBB = MBB->getPrevNode();
863     MBBI = MBB->end();
864   }
865   return --MBBI;
866 }
867 
868 static const Constant *getConstantFromPool(const MachineInstr &MI,
869                                            const MachineOperand &Op) {
870   if (!Op.isCPI())
871     return nullptr;
872 
873   ArrayRef<MachineConstantPoolEntry> Constants =
874       MI.getParent()->getParent()->getConstantPool()->getConstants();
875   const MachineConstantPoolEntry &ConstantEntry =
876       Constants[Op.getIndex()];
877 
878   // Bail if this is a machine constant pool entry, we won't be able to dig out
879   // anything useful.
880   if (ConstantEntry.isMachineConstantPoolEntry())
881     return nullptr;
882 
883   auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
884   assert((!C || ConstantEntry.getType() == C->getType()) &&
885          "Expected a constant of the same type!");
886   return C;
887 }
888 
889 static std::string getShuffleComment(const MachineOperand &DstOp,
890                                      const MachineOperand &SrcOp,
891                                      ArrayRef<int> Mask) {
892   std::string Comment;
893 
894   // Compute the name for a register. This is really goofy because we have
895   // multiple instruction printers that could (in theory) use different
896   // names. Fortunately most people use the ATT style (outside of Windows)
897   // and they actually agree on register naming here. Ultimately, this is
898   // a comment, and so its OK if it isn't perfect.
899   auto GetRegisterName = [](unsigned RegNum) -> StringRef {
900     return X86ATTInstPrinter::getRegisterName(RegNum);
901   };
902 
903   StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
904   StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
905 
906   raw_string_ostream CS(Comment);
907   CS << DstName << " = ";
908   bool NeedComma = false;
909   bool InSrc = false;
910   for (int M : Mask) {
911     // Wrap up any prior entry...
912     if (M == SM_SentinelZero && InSrc) {
913       InSrc = false;
914       CS << "]";
915     }
916     if (NeedComma)
917       CS << ",";
918     else
919       NeedComma = true;
920 
921     // Print this shuffle...
922     if (M == SM_SentinelZero) {
923       CS << "zero";
924     } else {
925       if (!InSrc) {
926         InSrc = true;
927         CS << SrcName << "[";
928       }
929       if (M == SM_SentinelUndef)
930         CS << "u";
931       else
932         CS << M;
933     }
934   }
935   if (InSrc)
936     CS << "]";
937   CS.flush();
938 
939   return Comment;
940 }
941 
942 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
943   X86MCInstLower MCInstLowering(*MF, *this);
944   const X86RegisterInfo *RI = static_cast<const X86RegisterInfo *>(
945       TM.getSubtargetImpl()->getRegisterInfo());
946 
947   switch (MI->getOpcode()) {
948   case TargetOpcode::DBG_VALUE:
949     llvm_unreachable("Should be handled target independently");
950 
951   // Emit nothing here but a comment if we can.
952   case X86::Int_MemBarrier:
953     OutStreamer.emitRawComment("MEMBARRIER");
954     return;
955 
956 
957   case X86::EH_RETURN:
958   case X86::EH_RETURN64: {
959     // Lower these as normal, but add some comments.
960     unsigned Reg = MI->getOperand(0).getReg();
961     OutStreamer.AddComment(StringRef("eh_return, addr: %") +
962                            X86ATTInstPrinter::getRegisterName(Reg));
963     break;
964   }
965   case X86::TAILJMPr:
966   case X86::TAILJMPd:
967   case X86::TAILJMPd64:
968     // Lower these as normal, but add some comments.
969     OutStreamer.AddComment("TAILCALL");
970     break;
971 
972   case X86::TLS_addr32:
973   case X86::TLS_addr64:
974   case X86::TLS_base_addr32:
975   case X86::TLS_base_addr64:
976     return LowerTlsAddr(MCInstLowering, *MI);
977 
978   case X86::MOVPC32r: {
979     // This is a pseudo op for a two instruction sequence with a label, which
980     // looks like:
981     //     call "L1$pb"
982     // "L1$pb":
983     //     popl %esi
984 
985     // Emit the call.
986     MCSymbol *PICBase = MF->getPICBaseSymbol();
987     // FIXME: We would like an efficient form for this, so we don't have to do a
988     // lot of extra uniquing.
989     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
990       .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
991 
992     // Emit the label.
993     OutStreamer.EmitLabel(PICBase);
994 
995     // popl $reg
996     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
997                             .addReg(MI->getOperand(0).getReg()));
998     return;
999   }
1000 
1001   case X86::ADD32ri: {
1002     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1003     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1004       break;
1005 
1006     // Okay, we have something like:
1007     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1008 
1009     // For this, we want to print something like:
1010     //   MYGLOBAL + (. - PICBASE)
1011     // However, we can't generate a ".", so just emit a new label here and refer
1012     // to it.
1013     MCSymbol *DotSym = OutContext.CreateTempSymbol();
1014     OutStreamer.EmitLabel(DotSym);
1015 
1016     // Now that we have emitted the label, lower the complex operand expression.
1017     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1018 
1019     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1020     const MCExpr *PICBase =
1021       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
1022     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
1023 
1024     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
1025                                       DotExpr, OutContext);
1026 
1027     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1028       .addReg(MI->getOperand(0).getReg())
1029       .addReg(MI->getOperand(1).getReg())
1030       .addExpr(DotExpr));
1031     return;
1032   }
1033 
1034   case TargetOpcode::STACKMAP:
1035     return LowerSTACKMAP(*MI);
1036 
1037   case TargetOpcode::PATCHPOINT:
1038     return LowerPATCHPOINT(*MI);
1039 
1040   case X86::MORESTACK_RET:
1041     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1042     return;
1043 
1044   case X86::MORESTACK_RET_RESTORE_R10:
1045     // Return, then restore R10.
1046     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1047     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1048                             .addReg(X86::R10)
1049                             .addReg(X86::RAX));
1050     return;
1051 
1052   case X86::SEH_PushReg:
1053     OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1054     return;
1055 
1056   case X86::SEH_SaveReg:
1057     OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1058                                   MI->getOperand(1).getImm());
1059     return;
1060 
1061   case X86::SEH_SaveXMM:
1062     OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1063                                   MI->getOperand(1).getImm());
1064     return;
1065 
1066   case X86::SEH_StackAlloc:
1067     OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1068     return;
1069 
1070   case X86::SEH_SetFrame:
1071     OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1072                                    MI->getOperand(1).getImm());
1073     return;
1074 
1075   case X86::SEH_PushFrame:
1076     OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1077     return;
1078 
1079   case X86::SEH_EndPrologue:
1080     OutStreamer.EmitWinCFIEndProlog();
1081     return;
1082 
1083   case X86::SEH_Epilogue: {
1084     MachineBasicBlock::const_iterator MBBI(MI);
1085     // Check if preceded by a call and emit nop if so.
1086     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1087       // Conservatively assume that pseudo instructions don't emit code and keep
1088       // looking for a call. We may emit an unnecessary nop in some cases.
1089       if (!MBBI->isPseudo()) {
1090         if (MBBI->isCall())
1091           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1092         break;
1093       }
1094     }
1095     return;
1096   }
1097 
1098     // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1099     // a constant shuffle mask. We won't be able to do this at the MC layer
1100     // because the mask isn't an immediate.
1101   case X86::PSHUFBrm:
1102   case X86::VPSHUFBrm:
1103   case X86::VPSHUFBYrm: {
1104     if (!OutStreamer.isVerboseAsm())
1105       break;
1106     assert(MI->getNumOperands() > 5 &&
1107            "We should always have at least 5 operands!");
1108     const MachineOperand &DstOp = MI->getOperand(0);
1109     const MachineOperand &SrcOp = MI->getOperand(1);
1110     const MachineOperand &MaskOp = MI->getOperand(5);
1111 
1112     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1113       SmallVector<int, 16> Mask;
1114       DecodePSHUFBMask(C, Mask);
1115       if (!Mask.empty())
1116         OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1117     }
1118     break;
1119   }
1120   case X86::VPERMILPSrm:
1121   case X86::VPERMILPDrm:
1122   case X86::VPERMILPSYrm:
1123   case X86::VPERMILPDYrm: {
1124     if (!OutStreamer.isVerboseAsm())
1125       break;
1126     assert(MI->getNumOperands() > 5 &&
1127            "We should always have at least 5 operands!");
1128     const MachineOperand &DstOp = MI->getOperand(0);
1129     const MachineOperand &SrcOp = MI->getOperand(1);
1130     const MachineOperand &MaskOp = MI->getOperand(5);
1131 
1132     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1133       SmallVector<int, 16> Mask;
1134       DecodeVPERMILPMask(C, Mask);
1135       if (!Mask.empty())
1136         OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1137     }
1138     break;
1139   }
1140 
1141     // For loads from a constant pool to a vector register, print the constant
1142     // loaded.
1143   case X86::MOVAPDrm:
1144   case X86::VMOVAPDrm:
1145   case X86::VMOVAPDYrm:
1146   case X86::MOVUPDrm:
1147   case X86::VMOVUPDrm:
1148   case X86::VMOVUPDYrm:
1149   case X86::MOVAPSrm:
1150   case X86::VMOVAPSrm:
1151   case X86::VMOVAPSYrm:
1152   case X86::MOVUPSrm:
1153   case X86::VMOVUPSrm:
1154   case X86::VMOVUPSYrm:
1155   case X86::MOVDQArm:
1156   case X86::VMOVDQArm:
1157   case X86::VMOVDQAYrm:
1158   case X86::MOVDQUrm:
1159   case X86::VMOVDQUrm:
1160   case X86::VMOVDQUYrm:
1161     if (!OutStreamer.isVerboseAsm())
1162       break;
1163     if (MI->getNumOperands() > 4)
1164     if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1165       std::string Comment;
1166       raw_string_ostream CS(Comment);
1167       const MachineOperand &DstOp = MI->getOperand(0);
1168       CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1169       if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1170         CS << "[";
1171         for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1172           if (i != 0)
1173             CS << ",";
1174           if (CDS->getElementType()->isIntegerTy())
1175             CS << CDS->getElementAsInteger(i);
1176           else if (CDS->getElementType()->isFloatTy())
1177             CS << CDS->getElementAsFloat(i);
1178           else if (CDS->getElementType()->isDoubleTy())
1179             CS << CDS->getElementAsDouble(i);
1180           else
1181             CS << "?";
1182         }
1183         CS << "]";
1184         OutStreamer.AddComment(CS.str());
1185       } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1186         CS << "<";
1187         for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1188           if (i != 0)
1189             CS << ",";
1190           Constant *COp = CV->getOperand(i);
1191           if (isa<UndefValue>(COp)) {
1192             CS << "u";
1193           } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1194             CS << CI->getZExtValue();
1195           } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1196             SmallString<32> Str;
1197             CF->getValueAPF().toString(Str);
1198             CS << Str;
1199           } else {
1200             CS << "?";
1201           }
1202         }
1203         CS << ">";
1204         OutStreamer.AddComment(CS.str());
1205       }
1206     }
1207     break;
1208   }
1209 
1210   MCInst TmpInst;
1211   MCInstLowering.Lower(MI, TmpInst);
1212 
1213   // Stackmap shadows cannot include branch targets, so we can count the bytes
1214   // in a call towards the shadow, but must ensure that the no thread returns
1215   // in to the stackmap shadow.  The only way to achieve this is if the call
1216   // is at the end of the shadow.
1217   if (MI->isCall()) {
1218     // Count then size of the call towards the shadow
1219     SMShadowTracker.count(TmpInst, getSubtargetInfo());
1220     // Then flush the shadow so that we fill with nops before the call, not
1221     // after it.
1222     SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
1223     // Then emit the call
1224     OutStreamer.EmitInstruction(TmpInst, getSubtargetInfo());
1225     return;
1226   }
1227 
1228   EmitAndCountInstruction(TmpInst);
1229 }
1230