1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCFixup.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCInstBuilder.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Support/TargetRegistry.h"
39 using namespace llvm;
40 
41 namespace {
42 
43 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
44 class X86MCInstLower {
45   MCContext &Ctx;
46   const MachineFunction &MF;
47   const TargetMachine &TM;
48   const MCAsmInfo &MAI;
49   X86AsmPrinter &AsmPrinter;
50 public:
51   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
52 
53   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
54 
55   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
56   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
57 
58 private:
59   MachineModuleInfoMachO &getMachOMMI() const;
60   Mangler *getMang() const {
61     return AsmPrinter.Mang;
62   }
63 };
64 
65 } // end anonymous namespace
66 
67 // Emit a minimal sequence of nops spanning NumBytes bytes.
68 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
69                      const MCSubtargetInfo &STI);
70 
71 namespace llvm {
72    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
73      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
74 
75   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
76 
77   void
78   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
79     MF = &F;
80     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
81         *MF->getSubtarget().getInstrInfo(),
82         *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
83   }
84 
85   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
86                                                    const MCSubtargetInfo &STI) {
87     if (InShadow) {
88       SmallString<256> Code;
89       SmallVector<MCFixup, 4> Fixups;
90       raw_svector_ostream VecOS(Code);
91       CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
92       VecOS.flush();
93       CurrentShadowSize += Code.size();
94       if (CurrentShadowSize >= RequiredShadowSize)
95         InShadow = false; // The shadow is big enough. Stop counting.
96     }
97   }
98 
99   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
100     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
101     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
102       InShadow = false;
103       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
104                MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
105     }
106   }
107 
108   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
109     OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
110     SMShadowTracker.count(Inst, getSubtargetInfo());
111   }
112 } // end llvm namespace
113 
114 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
115                                X86AsmPrinter &asmprinter)
116     : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
117       AsmPrinter(asmprinter) {}
118 
119 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
120   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
121 }
122 
123 
124 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
125 /// operand to an MCSymbol.
126 MCSymbol *X86MCInstLower::
127 GetSymbolFromOperand(const MachineOperand &MO) const {
128   const DataLayout *DL = TM.getDataLayout();
129   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
130 
131   MCSymbol *Sym = nullptr;
132   SmallString<128> Name;
133   StringRef Suffix;
134 
135   switch (MO.getTargetFlags()) {
136   case X86II::MO_DLLIMPORT:
137     // Handle dllimport linkage.
138     Name += "__imp_";
139     break;
140   case X86II::MO_DARWIN_STUB:
141     Suffix = "$stub";
142     break;
143   case X86II::MO_DARWIN_NONLAZY:
144   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
145   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
146     Suffix = "$non_lazy_ptr";
147     break;
148   }
149 
150   if (!Suffix.empty())
151     Name += DL->getPrivateGlobalPrefix();
152 
153   unsigned PrefixLen = Name.size();
154 
155   if (MO.isGlobal()) {
156     const GlobalValue *GV = MO.getGlobal();
157     AsmPrinter.getNameWithPrefix(Name, GV);
158   } else if (MO.isSymbol()) {
159     if (MO.getTargetFlags() == X86II::MO_NOPREFIX)
160       Name += MO.getSymbolName();
161     else
162       getMang()->getNameWithPrefix(Name, MO.getSymbolName());
163   } else if (MO.isMBB()) {
164     assert(Suffix.empty());
165     Sym = MO.getMBB()->getSymbol();
166   }
167   unsigned OrigLen = Name.size() - PrefixLen;
168 
169   Name += Suffix;
170   if (!Sym)
171     Sym = Ctx.getOrCreateSymbol(Name);
172 
173   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
174 
175   // If the target flags on the operand changes the name of the symbol, do that
176   // before we return the symbol.
177   switch (MO.getTargetFlags()) {
178   default: break;
179   case X86II::MO_DARWIN_NONLAZY:
180   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
181     MachineModuleInfoImpl::StubValueTy &StubSym =
182       getMachOMMI().getGVStubEntry(Sym);
183     if (!StubSym.getPointer()) {
184       assert(MO.isGlobal() && "Extern symbol not handled yet");
185       StubSym =
186         MachineModuleInfoImpl::
187         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
188                     !MO.getGlobal()->hasInternalLinkage());
189     }
190     break;
191   }
192   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
193     MachineModuleInfoImpl::StubValueTy &StubSym =
194       getMachOMMI().getHiddenGVStubEntry(Sym);
195     if (!StubSym.getPointer()) {
196       assert(MO.isGlobal() && "Extern symbol not handled yet");
197       StubSym =
198         MachineModuleInfoImpl::
199         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
200                     !MO.getGlobal()->hasInternalLinkage());
201     }
202     break;
203   }
204   case X86II::MO_DARWIN_STUB: {
205     MachineModuleInfoImpl::StubValueTy &StubSym =
206       getMachOMMI().getFnStubEntry(Sym);
207     if (StubSym.getPointer())
208       return Sym;
209 
210     if (MO.isGlobal()) {
211       StubSym =
212         MachineModuleInfoImpl::
213         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
214                     !MO.getGlobal()->hasInternalLinkage());
215     } else {
216       StubSym =
217         MachineModuleInfoImpl::
218         StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
219     }
220     break;
221   }
222   }
223 
224   return Sym;
225 }
226 
227 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
228                                              MCSymbol *Sym) const {
229   // FIXME: We would like an efficient form for this, so we don't have to do a
230   // lot of extra uniquing.
231   const MCExpr *Expr = nullptr;
232   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
233 
234   switch (MO.getTargetFlags()) {
235   default: llvm_unreachable("Unknown target flag on GV operand");
236   case X86II::MO_NO_FLAG:    // No flag.
237   // These affect the name of the symbol, not any suffix.
238   case X86II::MO_DARWIN_NONLAZY:
239   case X86II::MO_DLLIMPORT:
240   case X86II::MO_DARWIN_STUB:
241   case X86II::MO_NOPREFIX:
242     break;
243 
244   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
245   case X86II::MO_TLVP_PIC_BASE:
246     Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
247     // Subtract the pic base.
248     Expr = MCBinaryExpr::createSub(Expr,
249                                   MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
250                                                            Ctx),
251                                    Ctx);
252     break;
253   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
254   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
255   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
256   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
257   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
258   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
259   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
260   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
261   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
262   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
263   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
264   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
265   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
266   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
267   case X86II::MO_PIC_BASE_OFFSET:
268   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
269   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
270     Expr = MCSymbolRefExpr::create(Sym, Ctx);
271     // Subtract the pic base.
272     Expr = MCBinaryExpr::createSub(Expr,
273                             MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
274                                    Ctx);
275     if (MO.isJTI()) {
276       assert(MAI.doesSetDirectiveSuppressesReloc());
277       // If .set directive is supported, use it to reduce the number of
278       // relocations the assembler will generate for differences between
279       // local labels. This is only safe when the symbols are in the same
280       // section so we are restricting it to jumptable references.
281       MCSymbol *Label = Ctx.createTempSymbol();
282       AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
283       Expr = MCSymbolRefExpr::create(Label, Ctx);
284     }
285     break;
286   }
287 
288   if (!Expr)
289     Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
290 
291   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
292     Expr = MCBinaryExpr::createAdd(Expr,
293                                    MCConstantExpr::create(MO.getOffset(), Ctx),
294                                    Ctx);
295   return MCOperand::createExpr(Expr);
296 }
297 
298 
299 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
300 /// a short fixed-register form.
301 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
302   unsigned ImmOp = Inst.getNumOperands() - 1;
303   assert(Inst.getOperand(0).isReg() &&
304          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
305          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
306            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
307           Inst.getNumOperands() == 2) && "Unexpected instruction!");
308 
309   // Check whether the destination register can be fixed.
310   unsigned Reg = Inst.getOperand(0).getReg();
311   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
312     return;
313 
314   // If so, rewrite the instruction.
315   MCOperand Saved = Inst.getOperand(ImmOp);
316   Inst = MCInst();
317   Inst.setOpcode(Opcode);
318   Inst.addOperand(Saved);
319 }
320 
321 /// \brief If a movsx instruction has a shorter encoding for the used register
322 /// simplify the instruction to use it instead.
323 static void SimplifyMOVSX(MCInst &Inst) {
324   unsigned NewOpcode = 0;
325   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
326   switch (Inst.getOpcode()) {
327   default:
328     llvm_unreachable("Unexpected instruction!");
329   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
330     if (Op0 == X86::AX && Op1 == X86::AL)
331       NewOpcode = X86::CBW;
332     break;
333   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
334     if (Op0 == X86::EAX && Op1 == X86::AX)
335       NewOpcode = X86::CWDE;
336     break;
337   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
338     if (Op0 == X86::RAX && Op1 == X86::EAX)
339       NewOpcode = X86::CDQE;
340     break;
341   }
342 
343   if (NewOpcode != 0) {
344     Inst = MCInst();
345     Inst.setOpcode(NewOpcode);
346   }
347 }
348 
349 /// \brief Simplify things like MOV32rm to MOV32o32a.
350 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
351                                   unsigned Opcode) {
352   // Don't make these simplifications in 64-bit mode; other assemblers don't
353   // perform them because they make the code larger.
354   if (Printer.getSubtarget().is64Bit())
355     return;
356 
357   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
358   unsigned AddrBase = IsStore;
359   unsigned RegOp = IsStore ? 0 : 5;
360   unsigned AddrOp = AddrBase + 3;
361   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
362          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
363          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
364          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
365          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
366          (Inst.getOperand(AddrOp).isExpr() ||
367           Inst.getOperand(AddrOp).isImm()) &&
368          "Unexpected instruction!");
369 
370   // Check whether the destination register can be fixed.
371   unsigned Reg = Inst.getOperand(RegOp).getReg();
372   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
373     return;
374 
375   // Check whether this is an absolute address.
376   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
377   // to do this here.
378   bool Absolute = true;
379   if (Inst.getOperand(AddrOp).isExpr()) {
380     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
381     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
382       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
383         Absolute = false;
384   }
385 
386   if (Absolute &&
387       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
388        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
389        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
390     return;
391 
392   // If so, rewrite the instruction.
393   MCOperand Saved = Inst.getOperand(AddrOp);
394   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
395   Inst = MCInst();
396   Inst.setOpcode(Opcode);
397   Inst.addOperand(Saved);
398   Inst.addOperand(Seg);
399 }
400 
401 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
402   return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
403 }
404 
405 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
406   OutMI.setOpcode(MI->getOpcode());
407 
408   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
409     const MachineOperand &MO = MI->getOperand(i);
410 
411     MCOperand MCOp;
412     switch (MO.getType()) {
413     default:
414       MI->dump();
415       llvm_unreachable("unknown operand type");
416     case MachineOperand::MO_Register:
417       // Ignore all implicit register operands.
418       if (MO.isImplicit()) continue;
419       MCOp = MCOperand::createReg(MO.getReg());
420       break;
421     case MachineOperand::MO_Immediate:
422       MCOp = MCOperand::createImm(MO.getImm());
423       break;
424     case MachineOperand::MO_MachineBasicBlock:
425     case MachineOperand::MO_GlobalAddress:
426     case MachineOperand::MO_ExternalSymbol:
427       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
428       break;
429     case MachineOperand::MO_JumpTableIndex:
430       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
431       break;
432     case MachineOperand::MO_ConstantPoolIndex:
433       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
434       break;
435     case MachineOperand::MO_BlockAddress:
436       MCOp = LowerSymbolOperand(MO,
437                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
438       break;
439     case MachineOperand::MO_RegisterMask:
440       // Ignore call clobbers.
441       continue;
442     }
443 
444     OutMI.addOperand(MCOp);
445   }
446 
447   // Handle a few special cases to eliminate operand modifiers.
448 ReSimplify:
449   switch (OutMI.getOpcode()) {
450   case X86::LEA64_32r:
451   case X86::LEA64r:
452   case X86::LEA16r:
453   case X86::LEA32r:
454     // LEA should have a segment register, but it must be empty.
455     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
456            "Unexpected # of LEA operands");
457     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
458            "LEA has segment specified!");
459     break;
460 
461   case X86::MOV32ri64:
462     OutMI.setOpcode(X86::MOV32ri);
463     break;
464 
465   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
466   // if one of the registers is extended, but other isn't.
467   case X86::VMOVAPDrr:
468   case X86::VMOVAPDYrr:
469   case X86::VMOVAPSrr:
470   case X86::VMOVAPSYrr:
471   case X86::VMOVDQArr:
472   case X86::VMOVDQAYrr:
473   case X86::VMOVDQUrr:
474   case X86::VMOVDQUYrr:
475   case X86::VMOVUPDrr:
476   case X86::VMOVUPDYrr:
477   case X86::VMOVUPSrr:
478   case X86::VMOVUPSYrr: {
479     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
480         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
481       unsigned NewOpc;
482       switch (OutMI.getOpcode()) {
483       default: llvm_unreachable("Invalid opcode");
484       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
485       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
486       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
487       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
488       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
489       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
490       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
491       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
492       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
493       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
494       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
495       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
496       }
497       OutMI.setOpcode(NewOpc);
498     }
499     break;
500   }
501   case X86::VMOVSDrr:
502   case X86::VMOVSSrr: {
503     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
504         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
505       unsigned NewOpc;
506       switch (OutMI.getOpcode()) {
507       default: llvm_unreachable("Invalid opcode");
508       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
509       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
510       }
511       OutMI.setOpcode(NewOpc);
512     }
513     break;
514   }
515 
516   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
517   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
518   // off all but the first operand (the callee).  FIXME: Change isel.
519   case X86::TAILJMPr64:
520   case X86::TAILJMPr64_REX:
521   case X86::CALL64r:
522   case X86::CALL64pcrel32: {
523     unsigned Opcode = OutMI.getOpcode();
524     MCOperand Saved = OutMI.getOperand(0);
525     OutMI = MCInst();
526     OutMI.setOpcode(Opcode);
527     OutMI.addOperand(Saved);
528     break;
529   }
530 
531   case X86::EH_RETURN:
532   case X86::EH_RETURN64: {
533     OutMI = MCInst();
534     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
535     break;
536   }
537 
538   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
539   case X86::TAILJMPr:
540   case X86::TAILJMPd:
541   case X86::TAILJMPd64: {
542     unsigned Opcode;
543     switch (OutMI.getOpcode()) {
544     default: llvm_unreachable("Invalid opcode");
545     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
546     case X86::TAILJMPd:
547     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
548     }
549 
550     MCOperand Saved = OutMI.getOperand(0);
551     OutMI = MCInst();
552     OutMI.setOpcode(Opcode);
553     OutMI.addOperand(Saved);
554     break;
555   }
556 
557   case X86::DEC16r:
558   case X86::DEC32r:
559   case X86::INC16r:
560   case X86::INC32r:
561     // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
562     if (!AsmPrinter.getSubtarget().is64Bit()) {
563       unsigned Opcode;
564       switch (OutMI.getOpcode()) {
565       default: llvm_unreachable("Invalid opcode");
566       case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
567       case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
568       case X86::INC16r: Opcode = X86::INC16r_alt; break;
569       case X86::INC32r: Opcode = X86::INC32r_alt; break;
570       }
571       OutMI.setOpcode(Opcode);
572     }
573     break;
574 
575   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
576   // this with an ugly goto in case the resultant OR uses EAX and needs the
577   // short form.
578   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
579   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
580   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
581   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
582   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
583   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
584   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
585   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
586   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
587 
588   // Atomic load and store require a separate pseudo-inst because Acquire
589   // implies mayStore and Release implies mayLoad; fix these to regular MOV
590   // instructions here
591   case X86::ACQUIRE_MOV8rm:    OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
592   case X86::ACQUIRE_MOV16rm:   OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
593   case X86::ACQUIRE_MOV32rm:   OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
594   case X86::ACQUIRE_MOV64rm:   OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
595   case X86::RELEASE_MOV8mr:    OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
596   case X86::RELEASE_MOV16mr:   OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
597   case X86::RELEASE_MOV32mr:   OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
598   case X86::RELEASE_MOV64mr:   OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
599   case X86::RELEASE_MOV8mi:    OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
600   case X86::RELEASE_MOV16mi:   OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
601   case X86::RELEASE_MOV32mi:   OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
602   case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
603   case X86::RELEASE_ADD8mi:    OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
604   case X86::RELEASE_ADD32mi:   OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
605   case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
606   case X86::RELEASE_AND8mi:    OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
607   case X86::RELEASE_AND32mi:   OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
608   case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
609   case X86::RELEASE_OR8mi:     OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
610   case X86::RELEASE_OR32mi:    OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
611   case X86::RELEASE_OR64mi32:  OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
612   case X86::RELEASE_XOR8mi:    OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
613   case X86::RELEASE_XOR32mi:   OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
614   case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
615   case X86::RELEASE_INC8m:     OutMI.setOpcode(X86::INC8m); goto ReSimplify;
616   case X86::RELEASE_INC16m:    OutMI.setOpcode(X86::INC16m); goto ReSimplify;
617   case X86::RELEASE_INC32m:    OutMI.setOpcode(X86::INC32m); goto ReSimplify;
618   case X86::RELEASE_INC64m:    OutMI.setOpcode(X86::INC64m); goto ReSimplify;
619   case X86::RELEASE_DEC8m:     OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
620   case X86::RELEASE_DEC16m:    OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
621   case X86::RELEASE_DEC32m:    OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
622   case X86::RELEASE_DEC64m:    OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
623 
624   // We don't currently select the correct instruction form for instructions
625   // which have a short %eax, etc. form. Handle this by custom lowering, for
626   // now.
627   //
628   // Note, we are currently not handling the following instructions:
629   // MOV64ao8, MOV64o8a
630   // XCHG16ar, XCHG32ar, XCHG64ar
631   case X86::MOV8mr_NOREX:
632   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
633   case X86::MOV8rm_NOREX:
634   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
635   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
636   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
637   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
638   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
639 
640   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
641   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
642   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
643   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
644   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
645   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
646   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
647   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
648   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
649   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
650   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
651   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
652   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
653   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
654   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
655   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
656   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
657   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
658   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
659   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
660   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
661   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
662   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
663   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
664   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
665   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
666   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
667   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
668   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
669   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
670   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
671   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
672   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
673   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
674   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
675   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
676 
677   // Try to shrink some forms of movsx.
678   case X86::MOVSX16rr8:
679   case X86::MOVSX32rr16:
680   case X86::MOVSX64rr32:
681     SimplifyMOVSX(OutMI);
682     break;
683   }
684 }
685 
686 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
687                                  const MachineInstr &MI) {
688 
689   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
690                   MI.getOpcode() == X86::TLS_base_addr64;
691 
692   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
693 
694   MCContext &context = OutStreamer->getContext();
695 
696   if (needsPadding)
697     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
698 
699   MCSymbolRefExpr::VariantKind SRVK;
700   switch (MI.getOpcode()) {
701     case X86::TLS_addr32:
702     case X86::TLS_addr64:
703       SRVK = MCSymbolRefExpr::VK_TLSGD;
704       break;
705     case X86::TLS_base_addr32:
706       SRVK = MCSymbolRefExpr::VK_TLSLDM;
707       break;
708     case X86::TLS_base_addr64:
709       SRVK = MCSymbolRefExpr::VK_TLSLD;
710       break;
711     default:
712       llvm_unreachable("unexpected opcode");
713   }
714 
715   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
716   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
717 
718   MCInst LEA;
719   if (is64Bits) {
720     LEA.setOpcode(X86::LEA64r);
721     LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
722     LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
723     LEA.addOperand(MCOperand::createImm(1));        // scale
724     LEA.addOperand(MCOperand::createReg(0));        // index
725     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
726     LEA.addOperand(MCOperand::createReg(0));        // seg
727   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
728     LEA.setOpcode(X86::LEA32r);
729     LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
730     LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
731     LEA.addOperand(MCOperand::createImm(1));        // scale
732     LEA.addOperand(MCOperand::createReg(0));        // index
733     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
734     LEA.addOperand(MCOperand::createReg(0));        // seg
735   } else {
736     LEA.setOpcode(X86::LEA32r);
737     LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
738     LEA.addOperand(MCOperand::createReg(0));        // base
739     LEA.addOperand(MCOperand::createImm(1));        // scale
740     LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
741     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
742     LEA.addOperand(MCOperand::createReg(0));        // seg
743   }
744   EmitAndCountInstruction(LEA);
745 
746   if (needsPadding) {
747     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
748     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
749     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
750   }
751 
752   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
753   MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
754   const MCSymbolRefExpr *tlsRef =
755     MCSymbolRefExpr::create(tlsGetAddr,
756                             MCSymbolRefExpr::VK_PLT,
757                             context);
758 
759   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
760                                                  : X86::CALLpcrel32)
761                             .addExpr(tlsRef));
762 }
763 
764 /// \brief Emit the optimal amount of multi-byte nops on X86.
765 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
766   // This works only for 64bit. For 32bit we have to do additional checking if
767   // the CPU supports multi-byte nops.
768   assert(Is64Bit && "EmitNops only supports X86-64");
769   while (NumBytes) {
770     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
771     Opc = IndexReg = Displacement = SegmentReg = 0;
772     BaseReg = X86::RAX; ScaleVal = 1;
773     switch (NumBytes) {
774     case  0: llvm_unreachable("Zero nops?"); break;
775     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
776     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
777     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
778     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
779     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
780              IndexReg = X86::RAX; break;
781     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
782              IndexReg = X86::RAX; break;
783     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
784     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
785              IndexReg = X86::RAX; break;
786     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
787              IndexReg = X86::RAX; break;
788     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
789              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
790     }
791 
792     unsigned NumPrefixes = std::min(NumBytes, 5U);
793     NumBytes -= NumPrefixes;
794     for (unsigned i = 0; i != NumPrefixes; ++i)
795       OS.EmitBytes("\x66");
796 
797     switch (Opc) {
798     default: llvm_unreachable("Unexpected opcode"); break;
799     case X86::NOOP:
800       OS.EmitInstruction(MCInstBuilder(Opc), STI);
801       break;
802     case X86::XCHG16ar:
803       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
804       break;
805     case X86::NOOPL:
806     case X86::NOOPW:
807       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
808                          .addImm(ScaleVal).addReg(IndexReg)
809                          .addImm(Displacement).addReg(SegmentReg), STI);
810       break;
811     }
812   } // while (NumBytes)
813 }
814 
815 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
816                                     X86MCInstLower &MCIL) {
817   assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
818 
819   StatepointOpers SOpers(&MI);
820   if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
821     EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
822              getSubtargetInfo());
823   } else {
824     // Lower call target and choose correct opcode
825     const MachineOperand &CallTarget = SOpers.getCallTarget();
826     MCOperand CallTargetMCOp;
827     unsigned CallOpcode;
828     switch (CallTarget.getType()) {
829     case MachineOperand::MO_GlobalAddress:
830     case MachineOperand::MO_ExternalSymbol:
831       CallTargetMCOp = MCIL.LowerSymbolOperand(
832           CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
833       CallOpcode = X86::CALL64pcrel32;
834       // Currently, we only support relative addressing with statepoints.
835       // Otherwise, we'll need a scratch register to hold the target
836       // address.  You'll fail asserts during load & relocation if this
837       // symbol is to far away. (TODO: support non-relative addressing)
838       break;
839     case MachineOperand::MO_Immediate:
840       CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
841       CallOpcode = X86::CALL64pcrel32;
842       // Currently, we only support relative addressing with statepoints.
843       // Otherwise, we'll need a scratch register to hold the target
844       // immediate.  You'll fail asserts during load & relocation if this
845       // address is to far away. (TODO: support non-relative addressing)
846       break;
847     case MachineOperand::MO_Register:
848       CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
849       CallOpcode = X86::CALL64r;
850       break;
851     default:
852       llvm_unreachable("Unsupported operand type in statepoint call target");
853       break;
854     }
855 
856     // Emit call
857     MCInst CallInst;
858     CallInst.setOpcode(CallOpcode);
859     CallInst.addOperand(CallTargetMCOp);
860     OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
861   }
862 
863   // Record our statepoint node in the same section used by STACKMAP
864   // and PATCHPOINT
865   SM.recordStatepoint(MI);
866 }
867 
868 
869 // Lower a stackmap of the form:
870 // <id>, <shadowBytes>, ...
871 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
872   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
873   SM.recordStackMap(MI);
874   unsigned NumShadowBytes = MI.getOperand(1).getImm();
875   SMShadowTracker.reset(NumShadowBytes);
876 }
877 
878 // Lower a patchpoint of the form:
879 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
880 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
881                                     X86MCInstLower &MCIL) {
882   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
883 
884   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
885 
886   SM.recordPatchPoint(MI);
887 
888   PatchPointOpers opers(&MI);
889   unsigned ScratchIdx = opers.getNextScratchIdx();
890   unsigned EncodedBytes = 0;
891   const MachineOperand &CalleeMO =
892     opers.getMetaOper(PatchPointOpers::TargetPos);
893 
894   // Check for null target. If target is non-null (i.e. is non-zero or is
895   // symbolic) then emit a call.
896   if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
897     MCOperand CalleeMCOp;
898     switch (CalleeMO.getType()) {
899     default:
900       /// FIXME: Add a verifier check for bad callee types.
901       llvm_unreachable("Unrecognized callee operand type.");
902     case MachineOperand::MO_Immediate:
903       if (CalleeMO.getImm())
904         CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
905       break;
906     case MachineOperand::MO_ExternalSymbol:
907     case MachineOperand::MO_GlobalAddress:
908       CalleeMCOp =
909         MCIL.LowerSymbolOperand(CalleeMO,
910                                 MCIL.GetSymbolFromOperand(CalleeMO));
911       break;
912     }
913 
914     // Emit MOV to materialize the target address and the CALL to target.
915     // This is encoded with 12-13 bytes, depending on which register is used.
916     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
917     if (X86II::isX86_64ExtendedReg(ScratchReg))
918       EncodedBytes = 13;
919     else
920       EncodedBytes = 12;
921 
922     EmitAndCountInstruction(
923         MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
924     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
925   }
926 
927   // Emit padding.
928   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
929   assert(NumBytes >= EncodedBytes &&
930          "Patchpoint can't request size less than the length of a call.");
931 
932   EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
933            getSubtargetInfo());
934 }
935 
936 // Returns instruction preceding MBBI in MachineFunction.
937 // If MBBI is the first instruction of the first basic block, returns null.
938 static MachineBasicBlock::const_iterator
939 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
940   const MachineBasicBlock *MBB = MBBI->getParent();
941   while (MBBI == MBB->begin()) {
942     if (MBB == MBB->getParent()->begin())
943       return nullptr;
944     MBB = MBB->getPrevNode();
945     MBBI = MBB->end();
946   }
947   return --MBBI;
948 }
949 
950 static const Constant *getConstantFromPool(const MachineInstr &MI,
951                                            const MachineOperand &Op) {
952   if (!Op.isCPI())
953     return nullptr;
954 
955   ArrayRef<MachineConstantPoolEntry> Constants =
956       MI.getParent()->getParent()->getConstantPool()->getConstants();
957   const MachineConstantPoolEntry &ConstantEntry =
958       Constants[Op.getIndex()];
959 
960   // Bail if this is a machine constant pool entry, we won't be able to dig out
961   // anything useful.
962   if (ConstantEntry.isMachineConstantPoolEntry())
963     return nullptr;
964 
965   auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
966   assert((!C || ConstantEntry.getType() == C->getType()) &&
967          "Expected a constant of the same type!");
968   return C;
969 }
970 
971 static std::string getShuffleComment(const MachineOperand &DstOp,
972                                      const MachineOperand &SrcOp,
973                                      ArrayRef<int> Mask) {
974   std::string Comment;
975 
976   // Compute the name for a register. This is really goofy because we have
977   // multiple instruction printers that could (in theory) use different
978   // names. Fortunately most people use the ATT style (outside of Windows)
979   // and they actually agree on register naming here. Ultimately, this is
980   // a comment, and so its OK if it isn't perfect.
981   auto GetRegisterName = [](unsigned RegNum) -> StringRef {
982     return X86ATTInstPrinter::getRegisterName(RegNum);
983   };
984 
985   StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
986   StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
987 
988   raw_string_ostream CS(Comment);
989   CS << DstName << " = ";
990   bool NeedComma = false;
991   bool InSrc = false;
992   for (int M : Mask) {
993     // Wrap up any prior entry...
994     if (M == SM_SentinelZero && InSrc) {
995       InSrc = false;
996       CS << "]";
997     }
998     if (NeedComma)
999       CS << ",";
1000     else
1001       NeedComma = true;
1002 
1003     // Print this shuffle...
1004     if (M == SM_SentinelZero) {
1005       CS << "zero";
1006     } else {
1007       if (!InSrc) {
1008         InSrc = true;
1009         CS << SrcName << "[";
1010       }
1011       if (M == SM_SentinelUndef)
1012         CS << "u";
1013       else
1014         CS << M;
1015     }
1016   }
1017   if (InSrc)
1018     CS << "]";
1019   CS.flush();
1020 
1021   return Comment;
1022 }
1023 
1024 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1025   X86MCInstLower MCInstLowering(*MF, *this);
1026   const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1027 
1028   switch (MI->getOpcode()) {
1029   case TargetOpcode::DBG_VALUE:
1030     llvm_unreachable("Should be handled target independently");
1031 
1032   // Emit nothing here but a comment if we can.
1033   case X86::Int_MemBarrier:
1034     OutStreamer->emitRawComment("MEMBARRIER");
1035     return;
1036 
1037 
1038   case X86::EH_RETURN:
1039   case X86::EH_RETURN64: {
1040     // Lower these as normal, but add some comments.
1041     unsigned Reg = MI->getOperand(0).getReg();
1042     OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1043                             X86ATTInstPrinter::getRegisterName(Reg));
1044     break;
1045   }
1046   case X86::TAILJMPr:
1047   case X86::TAILJMPm:
1048   case X86::TAILJMPd:
1049   case X86::TAILJMPr64:
1050   case X86::TAILJMPm64:
1051   case X86::TAILJMPd64:
1052   case X86::TAILJMPr64_REX:
1053   case X86::TAILJMPm64_REX:
1054   case X86::TAILJMPd64_REX:
1055     // Lower these as normal, but add some comments.
1056     OutStreamer->AddComment("TAILCALL");
1057     break;
1058 
1059   case X86::TLS_addr32:
1060   case X86::TLS_addr64:
1061   case X86::TLS_base_addr32:
1062   case X86::TLS_base_addr64:
1063     return LowerTlsAddr(MCInstLowering, *MI);
1064 
1065   case X86::MOVPC32r: {
1066     // This is a pseudo op for a two instruction sequence with a label, which
1067     // looks like:
1068     //     call "L1$pb"
1069     // "L1$pb":
1070     //     popl %esi
1071 
1072     // Emit the call.
1073     MCSymbol *PICBase = MF->getPICBaseSymbol();
1074     // FIXME: We would like an efficient form for this, so we don't have to do a
1075     // lot of extra uniquing.
1076     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1077       .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1078 
1079     // Emit the label.
1080     OutStreamer->EmitLabel(PICBase);
1081 
1082     // popl $reg
1083     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1084                             .addReg(MI->getOperand(0).getReg()));
1085     return;
1086   }
1087 
1088   case X86::ADD32ri: {
1089     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1090     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1091       break;
1092 
1093     // Okay, we have something like:
1094     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1095 
1096     // For this, we want to print something like:
1097     //   MYGLOBAL + (. - PICBASE)
1098     // However, we can't generate a ".", so just emit a new label here and refer
1099     // to it.
1100     MCSymbol *DotSym = OutContext.createTempSymbol();
1101     OutStreamer->EmitLabel(DotSym);
1102 
1103     // Now that we have emitted the label, lower the complex operand expression.
1104     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1105 
1106     const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1107     const MCExpr *PICBase =
1108       MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1109     DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1110 
1111     DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
1112                                       DotExpr, OutContext);
1113 
1114     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1115       .addReg(MI->getOperand(0).getReg())
1116       .addReg(MI->getOperand(1).getReg())
1117       .addExpr(DotExpr));
1118     return;
1119   }
1120   case TargetOpcode::STATEPOINT:
1121     return LowerSTATEPOINT(*MI, MCInstLowering);
1122 
1123   case TargetOpcode::STACKMAP:
1124     return LowerSTACKMAP(*MI);
1125 
1126   case TargetOpcode::PATCHPOINT:
1127     return LowerPATCHPOINT(*MI, MCInstLowering);
1128 
1129   case X86::MORESTACK_RET:
1130     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1131     return;
1132 
1133   case X86::MORESTACK_RET_RESTORE_R10:
1134     // Return, then restore R10.
1135     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1136     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1137                             .addReg(X86::R10)
1138                             .addReg(X86::RAX));
1139     return;
1140 
1141   case X86::SEH_PushReg:
1142     OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1143     return;
1144 
1145   case X86::SEH_SaveReg:
1146     OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1147                                    MI->getOperand(1).getImm());
1148     return;
1149 
1150   case X86::SEH_SaveXMM:
1151     OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1152                                    MI->getOperand(1).getImm());
1153     return;
1154 
1155   case X86::SEH_StackAlloc:
1156     OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1157     return;
1158 
1159   case X86::SEH_SetFrame:
1160     OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1161                                     MI->getOperand(1).getImm());
1162     return;
1163 
1164   case X86::SEH_PushFrame:
1165     OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1166     return;
1167 
1168   case X86::SEH_EndPrologue:
1169     OutStreamer->EmitWinCFIEndProlog();
1170     return;
1171 
1172   case X86::SEH_Epilogue: {
1173     MachineBasicBlock::const_iterator MBBI(MI);
1174     // Check if preceded by a call and emit nop if so.
1175     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1176       // Conservatively assume that pseudo instructions don't emit code and keep
1177       // looking for a call. We may emit an unnecessary nop in some cases.
1178       if (!MBBI->isPseudo()) {
1179         if (MBBI->isCall())
1180           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1181         break;
1182       }
1183     }
1184     return;
1185   }
1186 
1187     // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1188     // a constant shuffle mask. We won't be able to do this at the MC layer
1189     // because the mask isn't an immediate.
1190   case X86::PSHUFBrm:
1191   case X86::VPSHUFBrm:
1192   case X86::VPSHUFBYrm: {
1193     if (!OutStreamer->isVerboseAsm())
1194       break;
1195     assert(MI->getNumOperands() > 5 &&
1196            "We should always have at least 5 operands!");
1197     const MachineOperand &DstOp = MI->getOperand(0);
1198     const MachineOperand &SrcOp = MI->getOperand(1);
1199     const MachineOperand &MaskOp = MI->getOperand(5);
1200 
1201     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1202       SmallVector<int, 16> Mask;
1203       DecodePSHUFBMask(C, Mask);
1204       if (!Mask.empty())
1205         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1206     }
1207     break;
1208   }
1209   case X86::VPERMILPSrm:
1210   case X86::VPERMILPDrm:
1211   case X86::VPERMILPSYrm:
1212   case X86::VPERMILPDYrm: {
1213     if (!OutStreamer->isVerboseAsm())
1214       break;
1215     assert(MI->getNumOperands() > 5 &&
1216            "We should always have at least 5 operands!");
1217     const MachineOperand &DstOp = MI->getOperand(0);
1218     const MachineOperand &SrcOp = MI->getOperand(1);
1219     const MachineOperand &MaskOp = MI->getOperand(5);
1220 
1221     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1222       SmallVector<int, 16> Mask;
1223       DecodeVPERMILPMask(C, Mask);
1224       if (!Mask.empty())
1225         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1226     }
1227     break;
1228   }
1229 
1230     // For loads from a constant pool to a vector register, print the constant
1231     // loaded.
1232   case X86::MOVAPDrm:
1233   case X86::VMOVAPDrm:
1234   case X86::VMOVAPDYrm:
1235   case X86::MOVUPDrm:
1236   case X86::VMOVUPDrm:
1237   case X86::VMOVUPDYrm:
1238   case X86::MOVAPSrm:
1239   case X86::VMOVAPSrm:
1240   case X86::VMOVAPSYrm:
1241   case X86::MOVUPSrm:
1242   case X86::VMOVUPSrm:
1243   case X86::VMOVUPSYrm:
1244   case X86::MOVDQArm:
1245   case X86::VMOVDQArm:
1246   case X86::VMOVDQAYrm:
1247   case X86::MOVDQUrm:
1248   case X86::VMOVDQUrm:
1249   case X86::VMOVDQUYrm:
1250     if (!OutStreamer->isVerboseAsm())
1251       break;
1252     if (MI->getNumOperands() > 4)
1253     if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1254       std::string Comment;
1255       raw_string_ostream CS(Comment);
1256       const MachineOperand &DstOp = MI->getOperand(0);
1257       CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1258       if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1259         CS << "[";
1260         for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1261           if (i != 0)
1262             CS << ",";
1263           if (CDS->getElementType()->isIntegerTy())
1264             CS << CDS->getElementAsInteger(i);
1265           else if (CDS->getElementType()->isFloatTy())
1266             CS << CDS->getElementAsFloat(i);
1267           else if (CDS->getElementType()->isDoubleTy())
1268             CS << CDS->getElementAsDouble(i);
1269           else
1270             CS << "?";
1271         }
1272         CS << "]";
1273         OutStreamer->AddComment(CS.str());
1274       } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1275         CS << "<";
1276         for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1277           if (i != 0)
1278             CS << ",";
1279           Constant *COp = CV->getOperand(i);
1280           if (isa<UndefValue>(COp)) {
1281             CS << "u";
1282           } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1283             CS << CI->getZExtValue();
1284           } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1285             SmallString<32> Str;
1286             CF->getValueAPF().toString(Str);
1287             CS << Str;
1288           } else {
1289             CS << "?";
1290           }
1291         }
1292         CS << ">";
1293         OutStreamer->AddComment(CS.str());
1294       }
1295     }
1296     break;
1297   }
1298 
1299   MCInst TmpInst;
1300   MCInstLowering.Lower(MI, TmpInst);
1301 
1302   // Stackmap shadows cannot include branch targets, so we can count the bytes
1303   // in a call towards the shadow, but must ensure that the no thread returns
1304   // in to the stackmap shadow.  The only way to achieve this is if the call
1305   // is at the end of the shadow.
1306   if (MI->isCall()) {
1307     // Count then size of the call towards the shadow
1308     SMShadowTracker.count(TmpInst, getSubtargetInfo());
1309     // Then flush the shadow so that we fill with nops before the call, not
1310     // after it.
1311     SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1312     // Then emit the call
1313     OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1314     return;
1315   }
1316 
1317   EmitAndCountInstruction(TmpInst);
1318 }
1319