1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/MC/MCInstBuilder.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/Support/TargetRegistry.h"
38 using namespace llvm;
39 
40 namespace {
41 
42 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
43 class X86MCInstLower {
44   MCContext &Ctx;
45   const MachineFunction &MF;
46   const TargetMachine &TM;
47   const MCAsmInfo &MAI;
48   X86AsmPrinter &AsmPrinter;
49 public:
50   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
51 
52   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
53 
54   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
55   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
56 
57 private:
58   MachineModuleInfoMachO &getMachOMMI() const;
59   Mangler *getMang() const {
60     return AsmPrinter.Mang;
61   }
62 };
63 
64 } // end anonymous namespace
65 
66 // Emit a minimal sequence of nops spanning NumBytes bytes.
67 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
68                      const MCSubtargetInfo &STI);
69 
70 namespace llvm {
71    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
72      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
73 
74   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
75 
76   void
77   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &MF) {
78     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
79         *TM.getSubtargetImpl()->getInstrInfo(),
80         *TM.getSubtargetImpl()->getRegisterInfo(), *TM.getSubtargetImpl(),
81         MF.getContext()));
82   }
83 
84   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
85                                                    const MCSubtargetInfo &STI) {
86     if (InShadow) {
87       SmallString<256> Code;
88       SmallVector<MCFixup, 4> Fixups;
89       raw_svector_ostream VecOS(Code);
90       CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
91       VecOS.flush();
92       CurrentShadowSize += Code.size();
93       if (CurrentShadowSize >= RequiredShadowSize)
94         InShadow = false; // The shadow is big enough. Stop counting.
95     }
96   }
97 
98   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
99     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
100     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
101       InShadow = false;
102       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
103                TM.getSubtarget<X86Subtarget>().is64Bit(), STI);
104     }
105   }
106 
107   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
108     OutStreamer.EmitInstruction(Inst, getSubtargetInfo());
109     SMShadowTracker.count(Inst, getSubtargetInfo());
110   }
111 } // end llvm namespace
112 
113 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
114                                X86AsmPrinter &asmprinter)
115 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
116   MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
117 
118 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
119   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
120 }
121 
122 
123 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
124 /// operand to an MCSymbol.
125 MCSymbol *X86MCInstLower::
126 GetSymbolFromOperand(const MachineOperand &MO) const {
127   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
128   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
129 
130   SmallString<128> Name;
131   StringRef Suffix;
132 
133   switch (MO.getTargetFlags()) {
134   case X86II::MO_DLLIMPORT:
135     // Handle dllimport linkage.
136     Name += "__imp_";
137     break;
138   case X86II::MO_DARWIN_STUB:
139     Suffix = "$stub";
140     break;
141   case X86II::MO_DARWIN_NONLAZY:
142   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
143   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
144     Suffix = "$non_lazy_ptr";
145     break;
146   }
147 
148   if (!Suffix.empty())
149     Name += DL->getPrivateGlobalPrefix();
150 
151   unsigned PrefixLen = Name.size();
152 
153   if (MO.isGlobal()) {
154     const GlobalValue *GV = MO.getGlobal();
155     AsmPrinter.getNameWithPrefix(Name, GV);
156   } else if (MO.isSymbol()) {
157     getMang()->getNameWithPrefix(Name, MO.getSymbolName());
158   } else if (MO.isMBB()) {
159     Name += MO.getMBB()->getSymbol()->getName();
160   }
161   unsigned OrigLen = Name.size() - PrefixLen;
162 
163   Name += Suffix;
164   MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
165 
166   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
167 
168   // If the target flags on the operand changes the name of the symbol, do that
169   // before we return the symbol.
170   switch (MO.getTargetFlags()) {
171   default: break;
172   case X86II::MO_DARWIN_NONLAZY:
173   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
174     MachineModuleInfoImpl::StubValueTy &StubSym =
175       getMachOMMI().getGVStubEntry(Sym);
176     if (!StubSym.getPointer()) {
177       assert(MO.isGlobal() && "Extern symbol not handled yet");
178       StubSym =
179         MachineModuleInfoImpl::
180         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
181                     !MO.getGlobal()->hasInternalLinkage());
182     }
183     break;
184   }
185   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
186     MachineModuleInfoImpl::StubValueTy &StubSym =
187       getMachOMMI().getHiddenGVStubEntry(Sym);
188     if (!StubSym.getPointer()) {
189       assert(MO.isGlobal() && "Extern symbol not handled yet");
190       StubSym =
191         MachineModuleInfoImpl::
192         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
193                     !MO.getGlobal()->hasInternalLinkage());
194     }
195     break;
196   }
197   case X86II::MO_DARWIN_STUB: {
198     MachineModuleInfoImpl::StubValueTy &StubSym =
199       getMachOMMI().getFnStubEntry(Sym);
200     if (StubSym.getPointer())
201       return Sym;
202 
203     if (MO.isGlobal()) {
204       StubSym =
205         MachineModuleInfoImpl::
206         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
207                     !MO.getGlobal()->hasInternalLinkage());
208     } else {
209       StubSym =
210         MachineModuleInfoImpl::
211         StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
212     }
213     break;
214   }
215   }
216 
217   return Sym;
218 }
219 
220 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
221                                              MCSymbol *Sym) const {
222   // FIXME: We would like an efficient form for this, so we don't have to do a
223   // lot of extra uniquing.
224   const MCExpr *Expr = nullptr;
225   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
226 
227   switch (MO.getTargetFlags()) {
228   default: llvm_unreachable("Unknown target flag on GV operand");
229   case X86II::MO_NO_FLAG:    // No flag.
230   // These affect the name of the symbol, not any suffix.
231   case X86II::MO_DARWIN_NONLAZY:
232   case X86II::MO_DLLIMPORT:
233   case X86II::MO_DARWIN_STUB:
234     break;
235 
236   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
237   case X86II::MO_TLVP_PIC_BASE:
238     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
239     // Subtract the pic base.
240     Expr = MCBinaryExpr::CreateSub(Expr,
241                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
242                                                            Ctx),
243                                    Ctx);
244     break;
245   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
246   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
247   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
248   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
249   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
250   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
251   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
252   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
253   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
254   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
255   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
256   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
257   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
258   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
259   case X86II::MO_PIC_BASE_OFFSET:
260   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
261   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
262     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
263     // Subtract the pic base.
264     Expr = MCBinaryExpr::CreateSub(Expr,
265                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
266                                    Ctx);
267     if (MO.isJTI() && MAI.hasSetDirective()) {
268       // If .set directive is supported, use it to reduce the number of
269       // relocations the assembler will generate for differences between
270       // local labels. This is only safe when the symbols are in the same
271       // section so we are restricting it to jumptable references.
272       MCSymbol *Label = Ctx.CreateTempSymbol();
273       AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
274       Expr = MCSymbolRefExpr::Create(Label, Ctx);
275     }
276     break;
277   }
278 
279   if (!Expr)
280     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
281 
282   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
283     Expr = MCBinaryExpr::CreateAdd(Expr,
284                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
285                                    Ctx);
286   return MCOperand::CreateExpr(Expr);
287 }
288 
289 
290 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
291 /// a short fixed-register form.
292 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
293   unsigned ImmOp = Inst.getNumOperands() - 1;
294   assert(Inst.getOperand(0).isReg() &&
295          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
296          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
297            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
298           Inst.getNumOperands() == 2) && "Unexpected instruction!");
299 
300   // Check whether the destination register can be fixed.
301   unsigned Reg = Inst.getOperand(0).getReg();
302   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
303     return;
304 
305   // If so, rewrite the instruction.
306   MCOperand Saved = Inst.getOperand(ImmOp);
307   Inst = MCInst();
308   Inst.setOpcode(Opcode);
309   Inst.addOperand(Saved);
310 }
311 
312 /// \brief If a movsx instruction has a shorter encoding for the used register
313 /// simplify the instruction to use it instead.
314 static void SimplifyMOVSX(MCInst &Inst) {
315   unsigned NewOpcode = 0;
316   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
317   switch (Inst.getOpcode()) {
318   default:
319     llvm_unreachable("Unexpected instruction!");
320   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
321     if (Op0 == X86::AX && Op1 == X86::AL)
322       NewOpcode = X86::CBW;
323     break;
324   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
325     if (Op0 == X86::EAX && Op1 == X86::AX)
326       NewOpcode = X86::CWDE;
327     break;
328   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
329     if (Op0 == X86::RAX && Op1 == X86::EAX)
330       NewOpcode = X86::CDQE;
331     break;
332   }
333 
334   if (NewOpcode != 0) {
335     Inst = MCInst();
336     Inst.setOpcode(NewOpcode);
337   }
338 }
339 
340 /// \brief Simplify things like MOV32rm to MOV32o32a.
341 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
342                                   unsigned Opcode) {
343   // Don't make these simplifications in 64-bit mode; other assemblers don't
344   // perform them because they make the code larger.
345   if (Printer.getSubtarget().is64Bit())
346     return;
347 
348   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
349   unsigned AddrBase = IsStore;
350   unsigned RegOp = IsStore ? 0 : 5;
351   unsigned AddrOp = AddrBase + 3;
352   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
353          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
354          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
355          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
356          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
357          (Inst.getOperand(AddrOp).isExpr() ||
358           Inst.getOperand(AddrOp).isImm()) &&
359          "Unexpected instruction!");
360 
361   // Check whether the destination register can be fixed.
362   unsigned Reg = Inst.getOperand(RegOp).getReg();
363   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
364     return;
365 
366   // Check whether this is an absolute address.
367   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
368   // to do this here.
369   bool Absolute = true;
370   if (Inst.getOperand(AddrOp).isExpr()) {
371     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
372     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
373       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
374         Absolute = false;
375   }
376 
377   if (Absolute &&
378       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
379        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
380        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
381     return;
382 
383   // If so, rewrite the instruction.
384   MCOperand Saved = Inst.getOperand(AddrOp);
385   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
386   Inst = MCInst();
387   Inst.setOpcode(Opcode);
388   Inst.addOperand(Saved);
389   Inst.addOperand(Seg);
390 }
391 
392 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
393 {
394 	return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
395 }
396 
397 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
398   OutMI.setOpcode(MI->getOpcode());
399 
400   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
401     const MachineOperand &MO = MI->getOperand(i);
402 
403     MCOperand MCOp;
404     switch (MO.getType()) {
405     default:
406       MI->dump();
407       llvm_unreachable("unknown operand type");
408     case MachineOperand::MO_Register:
409       // Ignore all implicit register operands.
410       if (MO.isImplicit()) continue;
411       MCOp = MCOperand::CreateReg(MO.getReg());
412       break;
413     case MachineOperand::MO_Immediate:
414       MCOp = MCOperand::CreateImm(MO.getImm());
415       break;
416     case MachineOperand::MO_MachineBasicBlock:
417     case MachineOperand::MO_GlobalAddress:
418     case MachineOperand::MO_ExternalSymbol:
419       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
420       break;
421     case MachineOperand::MO_JumpTableIndex:
422       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
423       break;
424     case MachineOperand::MO_ConstantPoolIndex:
425       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
426       break;
427     case MachineOperand::MO_BlockAddress:
428       MCOp = LowerSymbolOperand(MO,
429                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
430       break;
431     case MachineOperand::MO_RegisterMask:
432       // Ignore call clobbers.
433       continue;
434     }
435 
436     OutMI.addOperand(MCOp);
437   }
438 
439   // Handle a few special cases to eliminate operand modifiers.
440 ReSimplify:
441   switch (OutMI.getOpcode()) {
442   case X86::LEA64_32r:
443   case X86::LEA64r:
444   case X86::LEA16r:
445   case X86::LEA32r:
446     // LEA should have a segment register, but it must be empty.
447     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
448            "Unexpected # of LEA operands");
449     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
450            "LEA has segment specified!");
451     break;
452 
453   case X86::MOV32ri64:
454     OutMI.setOpcode(X86::MOV32ri);
455     break;
456 
457   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
458   // if one of the registers is extended, but other isn't.
459   case X86::VMOVAPDrr:
460   case X86::VMOVAPDYrr:
461   case X86::VMOVAPSrr:
462   case X86::VMOVAPSYrr:
463   case X86::VMOVDQArr:
464   case X86::VMOVDQAYrr:
465   case X86::VMOVDQUrr:
466   case X86::VMOVDQUYrr:
467   case X86::VMOVUPDrr:
468   case X86::VMOVUPDYrr:
469   case X86::VMOVUPSrr:
470   case X86::VMOVUPSYrr: {
471     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
472         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
473       unsigned NewOpc;
474       switch (OutMI.getOpcode()) {
475       default: llvm_unreachable("Invalid opcode");
476       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
477       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
478       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
479       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
480       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
481       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
482       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
483       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
484       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
485       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
486       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
487       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
488       }
489       OutMI.setOpcode(NewOpc);
490     }
491     break;
492   }
493   case X86::VMOVSDrr:
494   case X86::VMOVSSrr: {
495     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
496         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
497       unsigned NewOpc;
498       switch (OutMI.getOpcode()) {
499       default: llvm_unreachable("Invalid opcode");
500       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
501       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
502       }
503       OutMI.setOpcode(NewOpc);
504     }
505     break;
506   }
507 
508   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
509   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
510   // off all but the first operand (the callee).  FIXME: Change isel.
511   case X86::TAILJMPr64:
512   case X86::CALL64r:
513   case X86::CALL64pcrel32: {
514     unsigned Opcode = OutMI.getOpcode();
515     MCOperand Saved = OutMI.getOperand(0);
516     OutMI = MCInst();
517     OutMI.setOpcode(Opcode);
518     OutMI.addOperand(Saved);
519     break;
520   }
521 
522   case X86::EH_RETURN:
523   case X86::EH_RETURN64: {
524     OutMI = MCInst();
525     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
526     break;
527   }
528 
529   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
530   case X86::TAILJMPr:
531   case X86::TAILJMPd:
532   case X86::TAILJMPd64: {
533     unsigned Opcode;
534     switch (OutMI.getOpcode()) {
535     default: llvm_unreachable("Invalid opcode");
536     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
537     case X86::TAILJMPd:
538     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
539     }
540 
541     MCOperand Saved = OutMI.getOperand(0);
542     OutMI = MCInst();
543     OutMI.setOpcode(Opcode);
544     OutMI.addOperand(Saved);
545     break;
546   }
547 
548   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
549   // this with an ugly goto in case the resultant OR uses EAX and needs the
550   // short form.
551   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
552   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
553   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
554   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
555   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
556   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
557   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
558   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
559   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
560 
561   // The assembler backend wants to see branches in their small form and relax
562   // them to their large form.  The JIT can only handle the large form because
563   // it does not do relaxation.  For now, translate the large form to the
564   // small one here.
565   case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
566   case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
567   case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
568   case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
569   case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
570   case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
571   case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
572   case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
573   case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
574   case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
575   case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
576   case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
577   case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
578   case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
579   case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
580   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
581   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
582 
583   // Atomic load and store require a separate pseudo-inst because Acquire
584   // implies mayStore and Release implies mayLoad; fix these to regular MOV
585   // instructions here
586   case X86::ACQUIRE_MOV8rm:    OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
587   case X86::ACQUIRE_MOV16rm:   OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
588   case X86::ACQUIRE_MOV32rm:   OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
589   case X86::ACQUIRE_MOV64rm:   OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
590   case X86::RELEASE_MOV8mr:    OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
591   case X86::RELEASE_MOV16mr:   OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
592   case X86::RELEASE_MOV32mr:   OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
593   case X86::RELEASE_MOV64mr:   OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
594   case X86::RELEASE_MOV8mi:    OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
595   case X86::RELEASE_MOV16mi:   OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
596   case X86::RELEASE_MOV32mi:   OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
597   case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
598   case X86::RELEASE_ADD8mi:    OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
599   case X86::RELEASE_ADD32mi:   OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
600   case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
601   case X86::RELEASE_AND8mi:    OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
602   case X86::RELEASE_AND32mi:   OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
603   case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
604   case X86::RELEASE_OR8mi:     OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
605   case X86::RELEASE_OR32mi:    OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
606   case X86::RELEASE_OR64mi32:  OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
607   case X86::RELEASE_XOR8mi:    OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
608   case X86::RELEASE_XOR32mi:   OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
609   case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
610   case X86::RELEASE_INC8m:     OutMI.setOpcode(X86::INC8m); goto ReSimplify;
611   case X86::RELEASE_INC16m:    OutMI.setOpcode(X86::INC16m); goto ReSimplify;
612   case X86::RELEASE_INC32m:    OutMI.setOpcode(X86::INC32m); goto ReSimplify;
613   case X86::RELEASE_INC64m:    OutMI.setOpcode(X86::INC64m); goto ReSimplify;
614   case X86::RELEASE_DEC8m:     OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
615   case X86::RELEASE_DEC16m:    OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
616   case X86::RELEASE_DEC32m:    OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
617   case X86::RELEASE_DEC64m:    OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
618 
619   // We don't currently select the correct instruction form for instructions
620   // which have a short %eax, etc. form. Handle this by custom lowering, for
621   // now.
622   //
623   // Note, we are currently not handling the following instructions:
624   // MOV64ao8, MOV64o8a
625   // XCHG16ar, XCHG32ar, XCHG64ar
626   case X86::MOV8mr_NOREX:
627   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
628   case X86::MOV8rm_NOREX:
629   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
630   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
631   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
632   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
633   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
634 
635   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
636   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
637   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
638   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
639   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
640   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
641   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
642   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
643   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
644   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
645   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
646   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
647   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
648   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
649   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
650   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
651   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
652   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
653   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
654   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
655   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
656   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
657   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
658   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
659   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
660   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
661   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
662   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
663   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
664   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
665   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
666   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
667   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
668   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
669   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
670   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
671 
672   // Try to shrink some forms of movsx.
673   case X86::MOVSX16rr8:
674   case X86::MOVSX32rr16:
675   case X86::MOVSX64rr32:
676     SimplifyMOVSX(OutMI);
677     break;
678   }
679 }
680 
681 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
682                                  const MachineInstr &MI) {
683 
684   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
685                   MI.getOpcode() == X86::TLS_base_addr64;
686 
687   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
688 
689   MCContext &context = OutStreamer.getContext();
690 
691   if (needsPadding)
692     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
693 
694   MCSymbolRefExpr::VariantKind SRVK;
695   switch (MI.getOpcode()) {
696     case X86::TLS_addr32:
697     case X86::TLS_addr64:
698       SRVK = MCSymbolRefExpr::VK_TLSGD;
699       break;
700     case X86::TLS_base_addr32:
701       SRVK = MCSymbolRefExpr::VK_TLSLDM;
702       break;
703     case X86::TLS_base_addr64:
704       SRVK = MCSymbolRefExpr::VK_TLSLD;
705       break;
706     default:
707       llvm_unreachable("unexpected opcode");
708   }
709 
710   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
711   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
712 
713   MCInst LEA;
714   if (is64Bits) {
715     LEA.setOpcode(X86::LEA64r);
716     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
717     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
718     LEA.addOperand(MCOperand::CreateImm(1));        // scale
719     LEA.addOperand(MCOperand::CreateReg(0));        // index
720     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
721     LEA.addOperand(MCOperand::CreateReg(0));        // seg
722   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
723     LEA.setOpcode(X86::LEA32r);
724     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
725     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
726     LEA.addOperand(MCOperand::CreateImm(1));        // scale
727     LEA.addOperand(MCOperand::CreateReg(0));        // index
728     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
729     LEA.addOperand(MCOperand::CreateReg(0));        // seg
730   } else {
731     LEA.setOpcode(X86::LEA32r);
732     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
733     LEA.addOperand(MCOperand::CreateReg(0));        // base
734     LEA.addOperand(MCOperand::CreateImm(1));        // scale
735     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
736     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
737     LEA.addOperand(MCOperand::CreateReg(0));        // seg
738   }
739   EmitAndCountInstruction(LEA);
740 
741   if (needsPadding) {
742     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
743     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
744     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
745   }
746 
747   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
748   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
749   const MCSymbolRefExpr *tlsRef =
750     MCSymbolRefExpr::Create(tlsGetAddr,
751                             MCSymbolRefExpr::VK_PLT,
752                             context);
753 
754   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
755                                                  : X86::CALLpcrel32)
756                             .addExpr(tlsRef));
757 }
758 
759 /// \brief Emit the optimal amount of multi-byte nops on X86.
760 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
761   // This works only for 64bit. For 32bit we have to do additional checking if
762   // the CPU supports multi-byte nops.
763   assert(Is64Bit && "EmitNops only supports X86-64");
764   while (NumBytes) {
765     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
766     Opc = IndexReg = Displacement = SegmentReg = 0;
767     BaseReg = X86::RAX; ScaleVal = 1;
768     switch (NumBytes) {
769     case  0: llvm_unreachable("Zero nops?"); break;
770     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
771     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
772     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
773     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
774     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
775              IndexReg = X86::RAX; break;
776     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
777              IndexReg = X86::RAX; break;
778     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
779     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
780              IndexReg = X86::RAX; break;
781     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
782              IndexReg = X86::RAX; break;
783     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
784              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
785     }
786 
787     unsigned NumPrefixes = std::min(NumBytes, 5U);
788     NumBytes -= NumPrefixes;
789     for (unsigned i = 0; i != NumPrefixes; ++i)
790       OS.EmitBytes("\x66");
791 
792     switch (Opc) {
793     default: llvm_unreachable("Unexpected opcode"); break;
794     case X86::NOOP:
795       OS.EmitInstruction(MCInstBuilder(Opc), STI);
796       break;
797     case X86::XCHG16ar:
798       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
799       break;
800     case X86::NOOPL:
801     case X86::NOOPW:
802       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
803                          .addImm(ScaleVal).addReg(IndexReg)
804                          .addImm(Displacement).addReg(SegmentReg), STI);
805       break;
806     }
807   } // while (NumBytes)
808 }
809 
810 // Lower a stackmap of the form:
811 // <id>, <shadowBytes>, ...
812 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
813   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
814   SM.recordStackMap(MI);
815   unsigned NumShadowBytes = MI.getOperand(1).getImm();
816   SMShadowTracker.reset(NumShadowBytes);
817 }
818 
819 // Lower a patchpoint of the form:
820 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
821 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI) {
822   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
823 
824   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
825 
826   SM.recordPatchPoint(MI);
827 
828   PatchPointOpers opers(&MI);
829   unsigned ScratchIdx = opers.getNextScratchIdx();
830   unsigned EncodedBytes = 0;
831   int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
832   if (CallTarget) {
833     // Emit MOV to materialize the target address and the CALL to target.
834     // This is encoded with 12-13 bytes, depending on which register is used.
835     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
836     if (X86II::isX86_64ExtendedReg(ScratchReg))
837       EncodedBytes = 13;
838     else
839       EncodedBytes = 12;
840     EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
841                                                        .addImm(CallTarget));
842     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
843   }
844   // Emit padding.
845   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
846   assert(NumBytes >= EncodedBytes &&
847          "Patchpoint can't request size less than the length of a call.");
848 
849   EmitNops(OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
850            getSubtargetInfo());
851 }
852 
853 // Returns instruction preceding MBBI in MachineFunction.
854 // If MBBI is the first instruction of the first basic block, returns null.
855 static MachineBasicBlock::const_iterator
856 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
857   const MachineBasicBlock *MBB = MBBI->getParent();
858   while (MBBI == MBB->begin()) {
859     if (MBB == MBB->getParent()->begin())
860       return nullptr;
861     MBB = MBB->getPrevNode();
862     MBBI = MBB->end();
863   }
864   return --MBBI;
865 }
866 
867 static const Constant *getShuffleMaskConstant(const MachineInstr &MI,
868                                               const MachineOperand &DstOp,
869                                               const MachineOperand &SrcOp,
870                                               const MachineOperand &MaskOp) {
871   if (!MaskOp.isCPI())
872     return nullptr;
873 
874   ArrayRef<MachineConstantPoolEntry> Constants =
875       MI.getParent()->getParent()->getConstantPool()->getConstants();
876   const MachineConstantPoolEntry &MaskConstantEntry =
877       Constants[MaskOp.getIndex()];
878 
879   // Bail if this is a machine constant pool entry, we won't be able to dig out
880   // anything useful.
881   if (MaskConstantEntry.isMachineConstantPoolEntry())
882     return nullptr;
883 
884   auto *C = dyn_cast<Constant>(MaskConstantEntry.Val.ConstVal);
885   assert((!C || MaskConstantEntry.getType() == C->getType()) &&
886          "Expected a constant of the same type!");
887   return C;
888 }
889 
890 static std::string getShuffleComment(const MachineOperand &DstOp,
891                                      const MachineOperand &SrcOp,
892                                      ArrayRef<int> Mask) {
893   std::string Comment;
894 
895   // Compute the name for a register. This is really goofy because we have
896   // multiple instruction printers that could (in theory) use different
897   // names. Fortunately most people use the ATT style (outside of Windows)
898   // and they actually agree on register naming here. Ultimately, this is
899   // a comment, and so its OK if it isn't perfect.
900   auto GetRegisterName = [](unsigned RegNum) -> StringRef {
901     return X86ATTInstPrinter::getRegisterName(RegNum);
902   };
903 
904   StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
905   StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
906 
907   raw_string_ostream CS(Comment);
908   CS << DstName << " = ";
909   bool NeedComma = false;
910   bool InSrc = false;
911   for (int M : Mask) {
912     // Wrap up any prior entry...
913     if (M == SM_SentinelZero && InSrc) {
914       InSrc = false;
915       CS << "]";
916     }
917     if (NeedComma)
918       CS << ",";
919     else
920       NeedComma = true;
921 
922     // Print this shuffle...
923     if (M == SM_SentinelZero) {
924       CS << "zero";
925     } else {
926       if (!InSrc) {
927         InSrc = true;
928         CS << SrcName << "[";
929       }
930       if (M == SM_SentinelUndef)
931         CS << "u";
932       else
933         CS << M;
934     }
935   }
936   if (InSrc)
937     CS << "]";
938   CS.flush();
939 
940   return Comment;
941 }
942 
943 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
944   X86MCInstLower MCInstLowering(*MF, *this);
945   const X86RegisterInfo *RI = static_cast<const X86RegisterInfo *>(
946       TM.getSubtargetImpl()->getRegisterInfo());
947 
948   switch (MI->getOpcode()) {
949   case TargetOpcode::DBG_VALUE:
950     llvm_unreachable("Should be handled target independently");
951 
952   // Emit nothing here but a comment if we can.
953   case X86::Int_MemBarrier:
954     OutStreamer.emitRawComment("MEMBARRIER");
955     return;
956 
957 
958   case X86::EH_RETURN:
959   case X86::EH_RETURN64: {
960     // Lower these as normal, but add some comments.
961     unsigned Reg = MI->getOperand(0).getReg();
962     OutStreamer.AddComment(StringRef("eh_return, addr: %") +
963                            X86ATTInstPrinter::getRegisterName(Reg));
964     break;
965   }
966   case X86::TAILJMPr:
967   case X86::TAILJMPd:
968   case X86::TAILJMPd64:
969     // Lower these as normal, but add some comments.
970     OutStreamer.AddComment("TAILCALL");
971     break;
972 
973   case X86::TLS_addr32:
974   case X86::TLS_addr64:
975   case X86::TLS_base_addr32:
976   case X86::TLS_base_addr64:
977     return LowerTlsAddr(MCInstLowering, *MI);
978 
979   case X86::MOVPC32r: {
980     // This is a pseudo op for a two instruction sequence with a label, which
981     // looks like:
982     //     call "L1$pb"
983     // "L1$pb":
984     //     popl %esi
985 
986     // Emit the call.
987     MCSymbol *PICBase = MF->getPICBaseSymbol();
988     // FIXME: We would like an efficient form for this, so we don't have to do a
989     // lot of extra uniquing.
990     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
991       .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
992 
993     // Emit the label.
994     OutStreamer.EmitLabel(PICBase);
995 
996     // popl $reg
997     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
998                             .addReg(MI->getOperand(0).getReg()));
999     return;
1000   }
1001 
1002   case X86::ADD32ri: {
1003     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1004     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1005       break;
1006 
1007     // Okay, we have something like:
1008     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1009 
1010     // For this, we want to print something like:
1011     //   MYGLOBAL + (. - PICBASE)
1012     // However, we can't generate a ".", so just emit a new label here and refer
1013     // to it.
1014     MCSymbol *DotSym = OutContext.CreateTempSymbol();
1015     OutStreamer.EmitLabel(DotSym);
1016 
1017     // Now that we have emitted the label, lower the complex operand expression.
1018     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1019 
1020     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1021     const MCExpr *PICBase =
1022       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
1023     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
1024 
1025     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
1026                                       DotExpr, OutContext);
1027 
1028     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1029       .addReg(MI->getOperand(0).getReg())
1030       .addReg(MI->getOperand(1).getReg())
1031       .addExpr(DotExpr));
1032     return;
1033   }
1034 
1035   case TargetOpcode::STACKMAP:
1036     return LowerSTACKMAP(*MI);
1037 
1038   case TargetOpcode::PATCHPOINT:
1039     return LowerPATCHPOINT(*MI);
1040 
1041   case X86::MORESTACK_RET:
1042     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1043     return;
1044 
1045   case X86::MORESTACK_RET_RESTORE_R10:
1046     // Return, then restore R10.
1047     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1048     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1049                             .addReg(X86::R10)
1050                             .addReg(X86::RAX));
1051     return;
1052 
1053   case X86::SEH_PushReg:
1054     OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1055     return;
1056 
1057   case X86::SEH_SaveReg:
1058     OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1059                                   MI->getOperand(1).getImm());
1060     return;
1061 
1062   case X86::SEH_SaveXMM:
1063     OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1064                                   MI->getOperand(1).getImm());
1065     return;
1066 
1067   case X86::SEH_StackAlloc:
1068     OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1069     return;
1070 
1071   case X86::SEH_SetFrame:
1072     OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1073                                    MI->getOperand(1).getImm());
1074     return;
1075 
1076   case X86::SEH_PushFrame:
1077     OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1078     return;
1079 
1080   case X86::SEH_EndPrologue:
1081     OutStreamer.EmitWinCFIEndProlog();
1082     return;
1083 
1084   case X86::SEH_Epilogue: {
1085     MachineBasicBlock::const_iterator MBBI(MI);
1086     // Check if preceded by a call and emit nop if so.
1087     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1088       // Conservatively assume that pseudo instructions don't emit code and keep
1089       // looking for a call. We may emit an unnecessary nop in some cases.
1090       if (!MBBI->isPseudo()) {
1091         if (MBBI->isCall())
1092           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1093         break;
1094       }
1095     }
1096     return;
1097   }
1098 
1099     // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1100     // a constant shuffle mask. We won't be able to do this at the MC layer
1101     // because the mask isn't an immediate.
1102   case X86::PSHUFBrm:
1103   case X86::VPSHUFBrm: {
1104     if (!OutStreamer.isVerboseAsm())
1105       break;
1106     assert(MI->getNumOperands() > 5 &&
1107            "We should always have at least 5 operands!");
1108     const MachineOperand &DstOp = MI->getOperand(0);
1109     const MachineOperand &SrcOp = MI->getOperand(1);
1110     const MachineOperand &MaskOp = MI->getOperand(5);
1111 
1112     if (auto *C = getShuffleMaskConstant(*MI, DstOp, SrcOp, MaskOp)) {
1113       SmallVector<int, 16> Mask;
1114       DecodePSHUFBMask(C, Mask);
1115       if (!Mask.empty())
1116         OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1117     }
1118     break;
1119   }
1120   case X86::VPERMILPSrm:
1121   case X86::VPERMILPDrm:
1122   case X86::VPERMILPSYrm:
1123   case X86::VPERMILPDYrm: {
1124     if (!OutStreamer.isVerboseAsm())
1125       break;
1126     assert(MI->getNumOperands() > 5 &&
1127            "We should always have at least 5 operands!");
1128     const MachineOperand &DstOp = MI->getOperand(0);
1129     const MachineOperand &SrcOp = MI->getOperand(1);
1130     const MachineOperand &MaskOp = MI->getOperand(5);
1131 
1132     if (auto *C = getShuffleMaskConstant(*MI, DstOp, SrcOp, MaskOp)) {
1133       SmallVector<int, 16> Mask;
1134       DecodeVPERMILPMask(C, Mask);
1135       if (!Mask.empty())
1136         OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1137     }
1138     break;
1139   }
1140   }
1141 
1142   MCInst TmpInst;
1143   MCInstLowering.Lower(MI, TmpInst);
1144   EmitAndCountInstruction(TmpInst);
1145 }
1146