1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/MC/MCInstBuilder.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/Support/TargetRegistry.h"
38 using namespace llvm;
39 
40 namespace {
41 
42 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
43 class X86MCInstLower {
44   MCContext &Ctx;
45   const MachineFunction &MF;
46   const TargetMachine &TM;
47   const MCAsmInfo &MAI;
48   X86AsmPrinter &AsmPrinter;
49 public:
50   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
51 
52   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
53 
54   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
55   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
56 
57 private:
58   MachineModuleInfoMachO &getMachOMMI() const;
59   Mangler *getMang() const {
60     return AsmPrinter.Mang;
61   }
62 };
63 
64 } // end anonymous namespace
65 
66 // Emit a minimal sequence of nops spanning NumBytes bytes.
67 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
68                      const MCSubtargetInfo &STI);
69 
70 namespace llvm {
71    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
72      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
73 
74   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
75 
76   void
77   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
78     MF = &F;
79     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
80         *MF->getSubtarget().getInstrInfo(),
81         *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
82   }
83 
84   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
85                                                    const MCSubtargetInfo &STI) {
86     if (InShadow) {
87       SmallString<256> Code;
88       SmallVector<MCFixup, 4> Fixups;
89       raw_svector_ostream VecOS(Code);
90       CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
91       VecOS.flush();
92       CurrentShadowSize += Code.size();
93       if (CurrentShadowSize >= RequiredShadowSize)
94         InShadow = false; // The shadow is big enough. Stop counting.
95     }
96   }
97 
98   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
99     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
100     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
101       InShadow = false;
102       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
103                MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
104     }
105   }
106 
107   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
108     OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
109     SMShadowTracker.count(Inst, getSubtargetInfo());
110   }
111 } // end llvm namespace
112 
113 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
114                                X86AsmPrinter &asmprinter)
115     : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
116       AsmPrinter(asmprinter) {}
117 
118 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
119   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
120 }
121 
122 
123 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
124 /// operand to an MCSymbol.
125 MCSymbol *X86MCInstLower::
126 GetSymbolFromOperand(const MachineOperand &MO) const {
127   const DataLayout *DL = TM.getDataLayout();
128   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
129 
130   SmallString<128> Name;
131   StringRef Suffix;
132 
133   switch (MO.getTargetFlags()) {
134   case X86II::MO_DLLIMPORT:
135     // Handle dllimport linkage.
136     Name += "__imp_";
137     break;
138   case X86II::MO_DARWIN_STUB:
139     Suffix = "$stub";
140     break;
141   case X86II::MO_DARWIN_NONLAZY:
142   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
143   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
144     Suffix = "$non_lazy_ptr";
145     break;
146   }
147 
148   if (!Suffix.empty())
149     Name += DL->getPrivateGlobalPrefix();
150 
151   unsigned PrefixLen = Name.size();
152 
153   if (MO.isGlobal()) {
154     const GlobalValue *GV = MO.getGlobal();
155     AsmPrinter.getNameWithPrefix(Name, GV);
156   } else if (MO.isSymbol()) {
157     if (MO.getTargetFlags() == X86II::MO_NOPREFIX)
158       Name += MO.getSymbolName();
159     else
160       getMang()->getNameWithPrefix(Name, MO.getSymbolName());
161   } else if (MO.isMBB()) {
162     Name += MO.getMBB()->getSymbol()->getName();
163   }
164   unsigned OrigLen = Name.size() - PrefixLen;
165 
166   Name += Suffix;
167   MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
168 
169   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
170 
171   // If the target flags on the operand changes the name of the symbol, do that
172   // before we return the symbol.
173   switch (MO.getTargetFlags()) {
174   default: break;
175   case X86II::MO_DARWIN_NONLAZY:
176   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
177     MachineModuleInfoImpl::StubValueTy &StubSym =
178       getMachOMMI().getGVStubEntry(Sym);
179     if (!StubSym.getPointer()) {
180       assert(MO.isGlobal() && "Extern symbol not handled yet");
181       StubSym =
182         MachineModuleInfoImpl::
183         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
184                     !MO.getGlobal()->hasInternalLinkage());
185     }
186     break;
187   }
188   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
189     MachineModuleInfoImpl::StubValueTy &StubSym =
190       getMachOMMI().getHiddenGVStubEntry(Sym);
191     if (!StubSym.getPointer()) {
192       assert(MO.isGlobal() && "Extern symbol not handled yet");
193       StubSym =
194         MachineModuleInfoImpl::
195         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
196                     !MO.getGlobal()->hasInternalLinkage());
197     }
198     break;
199   }
200   case X86II::MO_DARWIN_STUB: {
201     MachineModuleInfoImpl::StubValueTy &StubSym =
202       getMachOMMI().getFnStubEntry(Sym);
203     if (StubSym.getPointer())
204       return Sym;
205 
206     if (MO.isGlobal()) {
207       StubSym =
208         MachineModuleInfoImpl::
209         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
210                     !MO.getGlobal()->hasInternalLinkage());
211     } else {
212       StubSym =
213         MachineModuleInfoImpl::
214         StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
215     }
216     break;
217   }
218   }
219 
220   return Sym;
221 }
222 
223 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
224                                              MCSymbol *Sym) const {
225   // FIXME: We would like an efficient form for this, so we don't have to do a
226   // lot of extra uniquing.
227   const MCExpr *Expr = nullptr;
228   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
229 
230   switch (MO.getTargetFlags()) {
231   default: llvm_unreachable("Unknown target flag on GV operand");
232   case X86II::MO_NO_FLAG:    // No flag.
233   // These affect the name of the symbol, not any suffix.
234   case X86II::MO_DARWIN_NONLAZY:
235   case X86II::MO_DLLIMPORT:
236   case X86II::MO_DARWIN_STUB:
237   case X86II::MO_NOPREFIX:
238     break;
239 
240   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
241   case X86II::MO_TLVP_PIC_BASE:
242     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
243     // Subtract the pic base.
244     Expr = MCBinaryExpr::CreateSub(Expr,
245                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
246                                                            Ctx),
247                                    Ctx);
248     break;
249   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
250   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
251   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
252   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
253   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
254   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
255   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
256   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
257   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
258   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
259   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
260   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
261   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
262   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
263   case X86II::MO_PIC_BASE_OFFSET:
264   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
265   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
266     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
267     // Subtract the pic base.
268     Expr = MCBinaryExpr::CreateSub(Expr,
269                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
270                                    Ctx);
271     if (MO.isJTI()) {
272       assert(MAI.doesSetDirectiveSuppressesReloc());
273       // If .set directive is supported, use it to reduce the number of
274       // relocations the assembler will generate for differences between
275       // local labels. This is only safe when the symbols are in the same
276       // section so we are restricting it to jumptable references.
277       MCSymbol *Label = Ctx.CreateTempSymbol();
278       AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
279       Expr = MCSymbolRefExpr::Create(Label, Ctx);
280     }
281     break;
282   }
283 
284   if (!Expr)
285     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
286 
287   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
288     Expr = MCBinaryExpr::CreateAdd(Expr,
289                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
290                                    Ctx);
291   return MCOperand::CreateExpr(Expr);
292 }
293 
294 
295 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
296 /// a short fixed-register form.
297 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
298   unsigned ImmOp = Inst.getNumOperands() - 1;
299   assert(Inst.getOperand(0).isReg() &&
300          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
301          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
302            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
303           Inst.getNumOperands() == 2) && "Unexpected instruction!");
304 
305   // Check whether the destination register can be fixed.
306   unsigned Reg = Inst.getOperand(0).getReg();
307   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
308     return;
309 
310   // If so, rewrite the instruction.
311   MCOperand Saved = Inst.getOperand(ImmOp);
312   Inst = MCInst();
313   Inst.setOpcode(Opcode);
314   Inst.addOperand(Saved);
315 }
316 
317 /// \brief If a movsx instruction has a shorter encoding for the used register
318 /// simplify the instruction to use it instead.
319 static void SimplifyMOVSX(MCInst &Inst) {
320   unsigned NewOpcode = 0;
321   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
322   switch (Inst.getOpcode()) {
323   default:
324     llvm_unreachable("Unexpected instruction!");
325   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
326     if (Op0 == X86::AX && Op1 == X86::AL)
327       NewOpcode = X86::CBW;
328     break;
329   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
330     if (Op0 == X86::EAX && Op1 == X86::AX)
331       NewOpcode = X86::CWDE;
332     break;
333   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
334     if (Op0 == X86::RAX && Op1 == X86::EAX)
335       NewOpcode = X86::CDQE;
336     break;
337   }
338 
339   if (NewOpcode != 0) {
340     Inst = MCInst();
341     Inst.setOpcode(NewOpcode);
342   }
343 }
344 
345 /// \brief Simplify things like MOV32rm to MOV32o32a.
346 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
347                                   unsigned Opcode) {
348   // Don't make these simplifications in 64-bit mode; other assemblers don't
349   // perform them because they make the code larger.
350   if (Printer.getSubtarget().is64Bit())
351     return;
352 
353   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
354   unsigned AddrBase = IsStore;
355   unsigned RegOp = IsStore ? 0 : 5;
356   unsigned AddrOp = AddrBase + 3;
357   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
358          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
359          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
360          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
361          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
362          (Inst.getOperand(AddrOp).isExpr() ||
363           Inst.getOperand(AddrOp).isImm()) &&
364          "Unexpected instruction!");
365 
366   // Check whether the destination register can be fixed.
367   unsigned Reg = Inst.getOperand(RegOp).getReg();
368   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
369     return;
370 
371   // Check whether this is an absolute address.
372   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
373   // to do this here.
374   bool Absolute = true;
375   if (Inst.getOperand(AddrOp).isExpr()) {
376     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
377     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
378       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
379         Absolute = false;
380   }
381 
382   if (Absolute &&
383       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
384        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
385        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
386     return;
387 
388   // If so, rewrite the instruction.
389   MCOperand Saved = Inst.getOperand(AddrOp);
390   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
391   Inst = MCInst();
392   Inst.setOpcode(Opcode);
393   Inst.addOperand(Saved);
394   Inst.addOperand(Seg);
395 }
396 
397 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
398   return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
399 }
400 
401 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
402   OutMI.setOpcode(MI->getOpcode());
403 
404   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
405     const MachineOperand &MO = MI->getOperand(i);
406 
407     MCOperand MCOp;
408     switch (MO.getType()) {
409     default:
410       MI->dump();
411       llvm_unreachable("unknown operand type");
412     case MachineOperand::MO_Register:
413       // Ignore all implicit register operands.
414       if (MO.isImplicit()) continue;
415       MCOp = MCOperand::CreateReg(MO.getReg());
416       break;
417     case MachineOperand::MO_Immediate:
418       MCOp = MCOperand::CreateImm(MO.getImm());
419       break;
420     case MachineOperand::MO_MachineBasicBlock:
421     case MachineOperand::MO_GlobalAddress:
422     case MachineOperand::MO_ExternalSymbol:
423       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
424       break;
425     case MachineOperand::MO_JumpTableIndex:
426       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
427       break;
428     case MachineOperand::MO_ConstantPoolIndex:
429       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
430       break;
431     case MachineOperand::MO_BlockAddress:
432       MCOp = LowerSymbolOperand(MO,
433                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
434       break;
435     case MachineOperand::MO_RegisterMask:
436       // Ignore call clobbers.
437       continue;
438     }
439 
440     OutMI.addOperand(MCOp);
441   }
442 
443   // Handle a few special cases to eliminate operand modifiers.
444 ReSimplify:
445   switch (OutMI.getOpcode()) {
446   case X86::LEA64_32r:
447   case X86::LEA64r:
448   case X86::LEA16r:
449   case X86::LEA32r:
450     // LEA should have a segment register, but it must be empty.
451     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
452            "Unexpected # of LEA operands");
453     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
454            "LEA has segment specified!");
455     break;
456 
457   case X86::MOV32ri64:
458     OutMI.setOpcode(X86::MOV32ri);
459     break;
460 
461   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
462   // if one of the registers is extended, but other isn't.
463   case X86::VMOVAPDrr:
464   case X86::VMOVAPDYrr:
465   case X86::VMOVAPSrr:
466   case X86::VMOVAPSYrr:
467   case X86::VMOVDQArr:
468   case X86::VMOVDQAYrr:
469   case X86::VMOVDQUrr:
470   case X86::VMOVDQUYrr:
471   case X86::VMOVUPDrr:
472   case X86::VMOVUPDYrr:
473   case X86::VMOVUPSrr:
474   case X86::VMOVUPSYrr: {
475     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
476         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
477       unsigned NewOpc;
478       switch (OutMI.getOpcode()) {
479       default: llvm_unreachable("Invalid opcode");
480       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
481       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
482       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
483       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
484       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
485       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
486       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
487       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
488       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
489       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
490       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
491       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
492       }
493       OutMI.setOpcode(NewOpc);
494     }
495     break;
496   }
497   case X86::VMOVSDrr:
498   case X86::VMOVSSrr: {
499     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
500         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
501       unsigned NewOpc;
502       switch (OutMI.getOpcode()) {
503       default: llvm_unreachable("Invalid opcode");
504       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
505       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
506       }
507       OutMI.setOpcode(NewOpc);
508     }
509     break;
510   }
511 
512   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
513   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
514   // off all but the first operand (the callee).  FIXME: Change isel.
515   case X86::TAILJMPr64:
516   case X86::TAILJMPr64_REX:
517   case X86::CALL64r:
518   case X86::CALL64pcrel32: {
519     unsigned Opcode = OutMI.getOpcode();
520     MCOperand Saved = OutMI.getOperand(0);
521     OutMI = MCInst();
522     OutMI.setOpcode(Opcode);
523     OutMI.addOperand(Saved);
524     break;
525   }
526 
527   case X86::EH_RETURN:
528   case X86::EH_RETURN64: {
529     OutMI = MCInst();
530     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
531     break;
532   }
533 
534   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
535   case X86::TAILJMPr:
536   case X86::TAILJMPd:
537   case X86::TAILJMPd64: {
538     unsigned Opcode;
539     switch (OutMI.getOpcode()) {
540     default: llvm_unreachable("Invalid opcode");
541     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
542     case X86::TAILJMPd:
543     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
544     }
545 
546     MCOperand Saved = OutMI.getOperand(0);
547     OutMI = MCInst();
548     OutMI.setOpcode(Opcode);
549     OutMI.addOperand(Saved);
550     break;
551   }
552 
553   case X86::DEC16r:
554   case X86::DEC32r:
555   case X86::INC16r:
556   case X86::INC32r:
557     // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
558     if (!AsmPrinter.getSubtarget().is64Bit()) {
559       unsigned Opcode;
560       switch (OutMI.getOpcode()) {
561       default: llvm_unreachable("Invalid opcode");
562       case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
563       case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
564       case X86::INC16r: Opcode = X86::INC16r_alt; break;
565       case X86::INC32r: Opcode = X86::INC32r_alt; break;
566       }
567       OutMI.setOpcode(Opcode);
568     }
569     break;
570 
571   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
572   // this with an ugly goto in case the resultant OR uses EAX and needs the
573   // short form.
574   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
575   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
576   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
577   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
578   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
579   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
580   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
581   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
582   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
583 
584   // Atomic load and store require a separate pseudo-inst because Acquire
585   // implies mayStore and Release implies mayLoad; fix these to regular MOV
586   // instructions here
587   case X86::ACQUIRE_MOV8rm:    OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
588   case X86::ACQUIRE_MOV16rm:   OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
589   case X86::ACQUIRE_MOV32rm:   OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
590   case X86::ACQUIRE_MOV64rm:   OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
591   case X86::RELEASE_MOV8mr:    OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
592   case X86::RELEASE_MOV16mr:   OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
593   case X86::RELEASE_MOV32mr:   OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
594   case X86::RELEASE_MOV64mr:   OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
595   case X86::RELEASE_MOV8mi:    OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
596   case X86::RELEASE_MOV16mi:   OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
597   case X86::RELEASE_MOV32mi:   OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
598   case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
599   case X86::RELEASE_ADD8mi:    OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
600   case X86::RELEASE_ADD32mi:   OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
601   case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
602   case X86::RELEASE_AND8mi:    OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
603   case X86::RELEASE_AND32mi:   OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
604   case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
605   case X86::RELEASE_OR8mi:     OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
606   case X86::RELEASE_OR32mi:    OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
607   case X86::RELEASE_OR64mi32:  OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
608   case X86::RELEASE_XOR8mi:    OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
609   case X86::RELEASE_XOR32mi:   OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
610   case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
611   case X86::RELEASE_INC8m:     OutMI.setOpcode(X86::INC8m); goto ReSimplify;
612   case X86::RELEASE_INC16m:    OutMI.setOpcode(X86::INC16m); goto ReSimplify;
613   case X86::RELEASE_INC32m:    OutMI.setOpcode(X86::INC32m); goto ReSimplify;
614   case X86::RELEASE_INC64m:    OutMI.setOpcode(X86::INC64m); goto ReSimplify;
615   case X86::RELEASE_DEC8m:     OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
616   case X86::RELEASE_DEC16m:    OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
617   case X86::RELEASE_DEC32m:    OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
618   case X86::RELEASE_DEC64m:    OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
619 
620   // We don't currently select the correct instruction form for instructions
621   // which have a short %eax, etc. form. Handle this by custom lowering, for
622   // now.
623   //
624   // Note, we are currently not handling the following instructions:
625   // MOV64ao8, MOV64o8a
626   // XCHG16ar, XCHG32ar, XCHG64ar
627   case X86::MOV8mr_NOREX:
628   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
629   case X86::MOV8rm_NOREX:
630   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
631   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
632   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
633   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
634   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
635 
636   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
637   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
638   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
639   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
640   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
641   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
642   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
643   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
644   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
645   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
646   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
647   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
648   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
649   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
650   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
651   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
652   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
653   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
654   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
655   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
656   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
657   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
658   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
659   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
660   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
661   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
662   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
663   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
664   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
665   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
666   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
667   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
668   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
669   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
670   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
671   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
672 
673   // Try to shrink some forms of movsx.
674   case X86::MOVSX16rr8:
675   case X86::MOVSX32rr16:
676   case X86::MOVSX64rr32:
677     SimplifyMOVSX(OutMI);
678     break;
679   }
680 }
681 
682 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
683                                  const MachineInstr &MI) {
684 
685   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
686                   MI.getOpcode() == X86::TLS_base_addr64;
687 
688   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
689 
690   MCContext &context = OutStreamer->getContext();
691 
692   if (needsPadding)
693     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
694 
695   MCSymbolRefExpr::VariantKind SRVK;
696   switch (MI.getOpcode()) {
697     case X86::TLS_addr32:
698     case X86::TLS_addr64:
699       SRVK = MCSymbolRefExpr::VK_TLSGD;
700       break;
701     case X86::TLS_base_addr32:
702       SRVK = MCSymbolRefExpr::VK_TLSLDM;
703       break;
704     case X86::TLS_base_addr64:
705       SRVK = MCSymbolRefExpr::VK_TLSLD;
706       break;
707     default:
708       llvm_unreachable("unexpected opcode");
709   }
710 
711   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
712   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
713 
714   MCInst LEA;
715   if (is64Bits) {
716     LEA.setOpcode(X86::LEA64r);
717     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
718     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
719     LEA.addOperand(MCOperand::CreateImm(1));        // scale
720     LEA.addOperand(MCOperand::CreateReg(0));        // index
721     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
722     LEA.addOperand(MCOperand::CreateReg(0));        // seg
723   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
724     LEA.setOpcode(X86::LEA32r);
725     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
726     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
727     LEA.addOperand(MCOperand::CreateImm(1));        // scale
728     LEA.addOperand(MCOperand::CreateReg(0));        // index
729     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
730     LEA.addOperand(MCOperand::CreateReg(0));        // seg
731   } else {
732     LEA.setOpcode(X86::LEA32r);
733     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
734     LEA.addOperand(MCOperand::CreateReg(0));        // base
735     LEA.addOperand(MCOperand::CreateImm(1));        // scale
736     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
737     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
738     LEA.addOperand(MCOperand::CreateReg(0));        // seg
739   }
740   EmitAndCountInstruction(LEA);
741 
742   if (needsPadding) {
743     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
744     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
745     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
746   }
747 
748   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
749   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
750   const MCSymbolRefExpr *tlsRef =
751     MCSymbolRefExpr::Create(tlsGetAddr,
752                             MCSymbolRefExpr::VK_PLT,
753                             context);
754 
755   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
756                                                  : X86::CALLpcrel32)
757                             .addExpr(tlsRef));
758 }
759 
760 /// \brief Emit the optimal amount of multi-byte nops on X86.
761 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
762   // This works only for 64bit. For 32bit we have to do additional checking if
763   // the CPU supports multi-byte nops.
764   assert(Is64Bit && "EmitNops only supports X86-64");
765   while (NumBytes) {
766     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
767     Opc = IndexReg = Displacement = SegmentReg = 0;
768     BaseReg = X86::RAX; ScaleVal = 1;
769     switch (NumBytes) {
770     case  0: llvm_unreachable("Zero nops?"); break;
771     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
772     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
773     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
774     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
775     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
776              IndexReg = X86::RAX; break;
777     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
778              IndexReg = X86::RAX; break;
779     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
780     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
781              IndexReg = X86::RAX; break;
782     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
783              IndexReg = X86::RAX; break;
784     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
785              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
786     }
787 
788     unsigned NumPrefixes = std::min(NumBytes, 5U);
789     NumBytes -= NumPrefixes;
790     for (unsigned i = 0; i != NumPrefixes; ++i)
791       OS.EmitBytes("\x66");
792 
793     switch (Opc) {
794     default: llvm_unreachable("Unexpected opcode"); break;
795     case X86::NOOP:
796       OS.EmitInstruction(MCInstBuilder(Opc), STI);
797       break;
798     case X86::XCHG16ar:
799       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
800       break;
801     case X86::NOOPL:
802     case X86::NOOPW:
803       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
804                          .addImm(ScaleVal).addReg(IndexReg)
805                          .addImm(Displacement).addReg(SegmentReg), STI);
806       break;
807     }
808   } // while (NumBytes)
809 }
810 
811 static void LowerSTATEPOINT(MCStreamer &OS, StackMaps &SM,
812                             const MachineInstr &MI, bool Is64Bit,
813                             const TargetMachine& TM,
814                             const MCSubtargetInfo& STI,
815                             X86MCInstLower &MCInstLowering) {
816   assert(Is64Bit && "Statepoint currently only supports X86-64");
817 
818   // Lower call target and choose correct opcode
819   const MachineOperand &call_target = StatepointOpers(&MI).getCallTarget();
820   MCOperand call_target_mcop;
821   unsigned call_opcode;
822   switch (call_target.getType()) {
823   case MachineOperand::MO_GlobalAddress:
824   case MachineOperand::MO_ExternalSymbol:
825     call_target_mcop = MCInstLowering.LowerSymbolOperand(
826       call_target,
827       MCInstLowering.GetSymbolFromOperand(call_target));
828     call_opcode = X86::CALL64pcrel32;
829     // Currently, we only support relative addressing with statepoints.
830     // Otherwise, we'll need a scratch register to hold the target
831     // address.  You'll fail asserts during load & relocation if this
832     // symbol is to far away. (TODO: support non-relative addressing)
833     break;
834   case MachineOperand::MO_Immediate:
835     call_target_mcop = MCOperand::CreateImm(call_target.getImm());
836     call_opcode = X86::CALL64pcrel32;
837     // Currently, we only support relative addressing with statepoints.
838     // Otherwise, we'll need a scratch register to hold the target
839     // immediate.  You'll fail asserts during load & relocation if this
840     // address is to far away. (TODO: support non-relative addressing)
841     break;
842   case MachineOperand::MO_Register:
843     call_target_mcop = MCOperand::CreateReg(call_target.getReg());
844     call_opcode = X86::CALL64r;
845     break;
846   default:
847     llvm_unreachable("Unsupported operand type in statepoint call target");
848     break;
849   }
850 
851   // Emit call
852   MCInst call_inst;
853   call_inst.setOpcode(call_opcode);
854   call_inst.addOperand(call_target_mcop);
855   OS.EmitInstruction(call_inst, STI);
856 
857   // Record our statepoint node in the same section used by STACKMAP
858   // and PATCHPOINT
859   SM.recordStatepoint(MI);
860 }
861 
862 
863 // Lower a stackmap of the form:
864 // <id>, <shadowBytes>, ...
865 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
866   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
867   SM.recordStackMap(MI);
868   unsigned NumShadowBytes = MI.getOperand(1).getImm();
869   SMShadowTracker.reset(NumShadowBytes);
870 }
871 
872 // Lower a patchpoint of the form:
873 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
874 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
875                                     X86MCInstLower &MCIL) {
876   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
877 
878   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
879 
880   SM.recordPatchPoint(MI);
881 
882   PatchPointOpers opers(&MI);
883   unsigned ScratchIdx = opers.getNextScratchIdx();
884   unsigned EncodedBytes = 0;
885   const MachineOperand &CalleeMO =
886     opers.getMetaOper(PatchPointOpers::TargetPos);
887 
888   // Check for null target. If target is non-null (i.e. is non-zero or is
889   // symbolic) then emit a call.
890   if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
891     MCOperand CalleeMCOp;
892     switch (CalleeMO.getType()) {
893     default:
894       /// FIXME: Add a verifier check for bad callee types.
895       llvm_unreachable("Unrecognized callee operand type.");
896     case MachineOperand::MO_Immediate:
897       if (CalleeMO.getImm())
898         CalleeMCOp = MCOperand::CreateImm(CalleeMO.getImm());
899       break;
900     case MachineOperand::MO_ExternalSymbol:
901     case MachineOperand::MO_GlobalAddress:
902       CalleeMCOp =
903         MCIL.LowerSymbolOperand(CalleeMO,
904                                 MCIL.GetSymbolFromOperand(CalleeMO));
905       break;
906     }
907 
908     // Emit MOV to materialize the target address and the CALL to target.
909     // This is encoded with 12-13 bytes, depending on which register is used.
910     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
911     if (X86II::isX86_64ExtendedReg(ScratchReg))
912       EncodedBytes = 13;
913     else
914       EncodedBytes = 12;
915 
916     EmitAndCountInstruction(
917         MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
918     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
919   }
920 
921   // Emit padding.
922   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
923   assert(NumBytes >= EncodedBytes &&
924          "Patchpoint can't request size less than the length of a call.");
925 
926   EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
927            getSubtargetInfo());
928 }
929 
930 // Returns instruction preceding MBBI in MachineFunction.
931 // If MBBI is the first instruction of the first basic block, returns null.
932 static MachineBasicBlock::const_iterator
933 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
934   const MachineBasicBlock *MBB = MBBI->getParent();
935   while (MBBI == MBB->begin()) {
936     if (MBB == MBB->getParent()->begin())
937       return nullptr;
938     MBB = MBB->getPrevNode();
939     MBBI = MBB->end();
940   }
941   return --MBBI;
942 }
943 
944 static const Constant *getConstantFromPool(const MachineInstr &MI,
945                                            const MachineOperand &Op) {
946   if (!Op.isCPI())
947     return nullptr;
948 
949   ArrayRef<MachineConstantPoolEntry> Constants =
950       MI.getParent()->getParent()->getConstantPool()->getConstants();
951   const MachineConstantPoolEntry &ConstantEntry =
952       Constants[Op.getIndex()];
953 
954   // Bail if this is a machine constant pool entry, we won't be able to dig out
955   // anything useful.
956   if (ConstantEntry.isMachineConstantPoolEntry())
957     return nullptr;
958 
959   auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
960   assert((!C || ConstantEntry.getType() == C->getType()) &&
961          "Expected a constant of the same type!");
962   return C;
963 }
964 
965 static std::string getShuffleComment(const MachineOperand &DstOp,
966                                      const MachineOperand &SrcOp,
967                                      ArrayRef<int> Mask) {
968   std::string Comment;
969 
970   // Compute the name for a register. This is really goofy because we have
971   // multiple instruction printers that could (in theory) use different
972   // names. Fortunately most people use the ATT style (outside of Windows)
973   // and they actually agree on register naming here. Ultimately, this is
974   // a comment, and so its OK if it isn't perfect.
975   auto GetRegisterName = [](unsigned RegNum) -> StringRef {
976     return X86ATTInstPrinter::getRegisterName(RegNum);
977   };
978 
979   StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
980   StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
981 
982   raw_string_ostream CS(Comment);
983   CS << DstName << " = ";
984   bool NeedComma = false;
985   bool InSrc = false;
986   for (int M : Mask) {
987     // Wrap up any prior entry...
988     if (M == SM_SentinelZero && InSrc) {
989       InSrc = false;
990       CS << "]";
991     }
992     if (NeedComma)
993       CS << ",";
994     else
995       NeedComma = true;
996 
997     // Print this shuffle...
998     if (M == SM_SentinelZero) {
999       CS << "zero";
1000     } else {
1001       if (!InSrc) {
1002         InSrc = true;
1003         CS << SrcName << "[";
1004       }
1005       if (M == SM_SentinelUndef)
1006         CS << "u";
1007       else
1008         CS << M;
1009     }
1010   }
1011   if (InSrc)
1012     CS << "]";
1013   CS.flush();
1014 
1015   return Comment;
1016 }
1017 
1018 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1019   X86MCInstLower MCInstLowering(*MF, *this);
1020   const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1021 
1022   switch (MI->getOpcode()) {
1023   case TargetOpcode::DBG_VALUE:
1024     llvm_unreachable("Should be handled target independently");
1025 
1026   // Emit nothing here but a comment if we can.
1027   case X86::Int_MemBarrier:
1028     OutStreamer->emitRawComment("MEMBARRIER");
1029     return;
1030 
1031 
1032   case X86::EH_RETURN:
1033   case X86::EH_RETURN64: {
1034     // Lower these as normal, but add some comments.
1035     unsigned Reg = MI->getOperand(0).getReg();
1036     OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1037                             X86ATTInstPrinter::getRegisterName(Reg));
1038     break;
1039   }
1040   case X86::TAILJMPr:
1041   case X86::TAILJMPm:
1042   case X86::TAILJMPd:
1043   case X86::TAILJMPr64:
1044   case X86::TAILJMPm64:
1045   case X86::TAILJMPd64:
1046   case X86::TAILJMPr64_REX:
1047   case X86::TAILJMPm64_REX:
1048   case X86::TAILJMPd64_REX:
1049     // Lower these as normal, but add some comments.
1050     OutStreamer->AddComment("TAILCALL");
1051     break;
1052 
1053   case X86::TLS_addr32:
1054   case X86::TLS_addr64:
1055   case X86::TLS_base_addr32:
1056   case X86::TLS_base_addr64:
1057     return LowerTlsAddr(MCInstLowering, *MI);
1058 
1059   case X86::MOVPC32r: {
1060     // This is a pseudo op for a two instruction sequence with a label, which
1061     // looks like:
1062     //     call "L1$pb"
1063     // "L1$pb":
1064     //     popl %esi
1065 
1066     // Emit the call.
1067     MCSymbol *PICBase = MF->getPICBaseSymbol();
1068     // FIXME: We would like an efficient form for this, so we don't have to do a
1069     // lot of extra uniquing.
1070     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1071       .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
1072 
1073     // Emit the label.
1074     OutStreamer->EmitLabel(PICBase);
1075 
1076     // popl $reg
1077     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1078                             .addReg(MI->getOperand(0).getReg()));
1079     return;
1080   }
1081 
1082   case X86::ADD32ri: {
1083     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1084     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1085       break;
1086 
1087     // Okay, we have something like:
1088     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1089 
1090     // For this, we want to print something like:
1091     //   MYGLOBAL + (. - PICBASE)
1092     // However, we can't generate a ".", so just emit a new label here and refer
1093     // to it.
1094     MCSymbol *DotSym = OutContext.CreateTempSymbol();
1095     OutStreamer->EmitLabel(DotSym);
1096 
1097     // Now that we have emitted the label, lower the complex operand expression.
1098     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1099 
1100     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1101     const MCExpr *PICBase =
1102       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
1103     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
1104 
1105     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
1106                                       DotExpr, OutContext);
1107 
1108     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1109       .addReg(MI->getOperand(0).getReg())
1110       .addReg(MI->getOperand(1).getReg())
1111       .addExpr(DotExpr));
1112     return;
1113   }
1114   case TargetOpcode::STATEPOINT:
1115     return LowerSTATEPOINT(*OutStreamer, SM, *MI, Subtarget->is64Bit(), TM,
1116                            getSubtargetInfo(), MCInstLowering);
1117 
1118   case TargetOpcode::STACKMAP:
1119     return LowerSTACKMAP(*MI);
1120 
1121   case TargetOpcode::PATCHPOINT:
1122     return LowerPATCHPOINT(*MI, MCInstLowering);
1123 
1124   case X86::MORESTACK_RET:
1125     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1126     return;
1127 
1128   case X86::MORESTACK_RET_RESTORE_R10:
1129     // Return, then restore R10.
1130     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1131     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1132                             .addReg(X86::R10)
1133                             .addReg(X86::RAX));
1134     return;
1135 
1136   case X86::SEH_PushReg:
1137     OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1138     return;
1139 
1140   case X86::SEH_SaveReg:
1141     OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1142                                    MI->getOperand(1).getImm());
1143     return;
1144 
1145   case X86::SEH_SaveXMM:
1146     OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1147                                    MI->getOperand(1).getImm());
1148     return;
1149 
1150   case X86::SEH_StackAlloc:
1151     OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1152     return;
1153 
1154   case X86::SEH_SetFrame:
1155     OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1156                                     MI->getOperand(1).getImm());
1157     return;
1158 
1159   case X86::SEH_PushFrame:
1160     OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1161     return;
1162 
1163   case X86::SEH_EndPrologue:
1164     OutStreamer->EmitWinCFIEndProlog();
1165     return;
1166 
1167   case X86::SEH_Epilogue: {
1168     MachineBasicBlock::const_iterator MBBI(MI);
1169     // Check if preceded by a call and emit nop if so.
1170     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1171       // Conservatively assume that pseudo instructions don't emit code and keep
1172       // looking for a call. We may emit an unnecessary nop in some cases.
1173       if (!MBBI->isPseudo()) {
1174         if (MBBI->isCall())
1175           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1176         break;
1177       }
1178     }
1179     return;
1180   }
1181 
1182     // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1183     // a constant shuffle mask. We won't be able to do this at the MC layer
1184     // because the mask isn't an immediate.
1185   case X86::PSHUFBrm:
1186   case X86::VPSHUFBrm:
1187   case X86::VPSHUFBYrm: {
1188     if (!OutStreamer->isVerboseAsm())
1189       break;
1190     assert(MI->getNumOperands() > 5 &&
1191            "We should always have at least 5 operands!");
1192     const MachineOperand &DstOp = MI->getOperand(0);
1193     const MachineOperand &SrcOp = MI->getOperand(1);
1194     const MachineOperand &MaskOp = MI->getOperand(5);
1195 
1196     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1197       SmallVector<int, 16> Mask;
1198       DecodePSHUFBMask(C, Mask);
1199       if (!Mask.empty())
1200         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1201     }
1202     break;
1203   }
1204   case X86::VPERMILPSrm:
1205   case X86::VPERMILPDrm:
1206   case X86::VPERMILPSYrm:
1207   case X86::VPERMILPDYrm: {
1208     if (!OutStreamer->isVerboseAsm())
1209       break;
1210     assert(MI->getNumOperands() > 5 &&
1211            "We should always have at least 5 operands!");
1212     const MachineOperand &DstOp = MI->getOperand(0);
1213     const MachineOperand &SrcOp = MI->getOperand(1);
1214     const MachineOperand &MaskOp = MI->getOperand(5);
1215 
1216     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1217       SmallVector<int, 16> Mask;
1218       DecodeVPERMILPMask(C, Mask);
1219       if (!Mask.empty())
1220         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1221     }
1222     break;
1223   }
1224 
1225     // For loads from a constant pool to a vector register, print the constant
1226     // loaded.
1227   case X86::MOVAPDrm:
1228   case X86::VMOVAPDrm:
1229   case X86::VMOVAPDYrm:
1230   case X86::MOVUPDrm:
1231   case X86::VMOVUPDrm:
1232   case X86::VMOVUPDYrm:
1233   case X86::MOVAPSrm:
1234   case X86::VMOVAPSrm:
1235   case X86::VMOVAPSYrm:
1236   case X86::MOVUPSrm:
1237   case X86::VMOVUPSrm:
1238   case X86::VMOVUPSYrm:
1239   case X86::MOVDQArm:
1240   case X86::VMOVDQArm:
1241   case X86::VMOVDQAYrm:
1242   case X86::MOVDQUrm:
1243   case X86::VMOVDQUrm:
1244   case X86::VMOVDQUYrm:
1245     if (!OutStreamer->isVerboseAsm())
1246       break;
1247     if (MI->getNumOperands() > 4)
1248     if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1249       std::string Comment;
1250       raw_string_ostream CS(Comment);
1251       const MachineOperand &DstOp = MI->getOperand(0);
1252       CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1253       if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1254         CS << "[";
1255         for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1256           if (i != 0)
1257             CS << ",";
1258           if (CDS->getElementType()->isIntegerTy())
1259             CS << CDS->getElementAsInteger(i);
1260           else if (CDS->getElementType()->isFloatTy())
1261             CS << CDS->getElementAsFloat(i);
1262           else if (CDS->getElementType()->isDoubleTy())
1263             CS << CDS->getElementAsDouble(i);
1264           else
1265             CS << "?";
1266         }
1267         CS << "]";
1268         OutStreamer->AddComment(CS.str());
1269       } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1270         CS << "<";
1271         for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1272           if (i != 0)
1273             CS << ",";
1274           Constant *COp = CV->getOperand(i);
1275           if (isa<UndefValue>(COp)) {
1276             CS << "u";
1277           } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1278             CS << CI->getZExtValue();
1279           } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1280             SmallString<32> Str;
1281             CF->getValueAPF().toString(Str);
1282             CS << Str;
1283           } else {
1284             CS << "?";
1285           }
1286         }
1287         CS << ">";
1288         OutStreamer->AddComment(CS.str());
1289       }
1290     }
1291     break;
1292   }
1293 
1294   MCInst TmpInst;
1295   MCInstLowering.Lower(MI, TmpInst);
1296 
1297   // Stackmap shadows cannot include branch targets, so we can count the bytes
1298   // in a call towards the shadow, but must ensure that the no thread returns
1299   // in to the stackmap shadow.  The only way to achieve this is if the call
1300   // is at the end of the shadow.
1301   if (MI->isCall()) {
1302     // Count then size of the call towards the shadow
1303     SMShadowTracker.count(TmpInst, getSubtargetInfo());
1304     // Then flush the shadow so that we fill with nops before the call, not
1305     // after it.
1306     SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1307     // Then emit the call
1308     OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1309     return;
1310   }
1311 
1312   EmitAndCountInstruction(TmpInst);
1313 }
1314