1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower X86 MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "InstPrinter/X86ATTInstPrinter.h" 16 #include "InstPrinter/X86InstComments.h" 17 #include "MCTargetDesc/X86BaseInfo.h" 18 #include "MCTargetDesc/X86TargetStreamer.h" 19 #include "Utils/X86ShuffleDecode.h" 20 #include "X86AsmPrinter.h" 21 #include "X86RegisterInfo.h" 22 #include "X86ShuffleDecodeConstantPool.h" 23 #include "llvm/ADT/Optional.h" 24 #include "llvm/ADT/SmallString.h" 25 #include "llvm/ADT/iterator_range.h" 26 #include "llvm/CodeGen/MachineConstantPool.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 29 #include "llvm/CodeGen/MachineOperand.h" 30 #include "llvm/CodeGen/StackMaps.h" 31 #include "llvm/IR/DataLayout.h" 32 #include "llvm/IR/GlobalValue.h" 33 #include "llvm/IR/Mangler.h" 34 #include "llvm/MC/MCAsmInfo.h" 35 #include "llvm/MC/MCCodeEmitter.h" 36 #include "llvm/MC/MCContext.h" 37 #include "llvm/MC/MCExpr.h" 38 #include "llvm/MC/MCFixup.h" 39 #include "llvm/MC/MCInst.h" 40 #include "llvm/MC/MCInstBuilder.h" 41 #include "llvm/MC/MCSection.h" 42 #include "llvm/MC/MCSectionELF.h" 43 #include "llvm/MC/MCStreamer.h" 44 #include "llvm/MC/MCSymbol.h" 45 #include "llvm/MC/MCSymbolELF.h" 46 #include "llvm/Target/TargetLoweringObjectFile.h" 47 48 using namespace llvm; 49 50 namespace { 51 52 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 53 class X86MCInstLower { 54 MCContext &Ctx; 55 const MachineFunction &MF; 56 const TargetMachine &TM; 57 const MCAsmInfo &MAI; 58 X86AsmPrinter &AsmPrinter; 59 60 public: 61 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter); 62 63 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI, 64 const MachineOperand &MO) const; 65 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 66 67 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 68 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 69 70 private: 71 MachineModuleInfoMachO &getMachOMMI() const; 72 }; 73 74 } // end anonymous namespace 75 76 // Emit a minimal sequence of nops spanning NumBytes bytes. 77 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 78 const MCSubtargetInfo &STI); 79 80 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst, 81 const MCSubtargetInfo &STI, 82 MCCodeEmitter *CodeEmitter) { 83 if (InShadow) { 84 SmallString<256> Code; 85 SmallVector<MCFixup, 4> Fixups; 86 raw_svector_ostream VecOS(Code); 87 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI); 88 CurrentShadowSize += Code.size(); 89 if (CurrentShadowSize >= RequiredShadowSize) 90 InShadow = false; // The shadow is big enough. Stop counting. 91 } 92 } 93 94 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding( 95 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { 96 if (InShadow && CurrentShadowSize < RequiredShadowSize) { 97 InShadow = false; 98 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize, 99 MF->getSubtarget<X86Subtarget>().is64Bit(), STI); 100 } 101 } 102 103 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) { 104 OutStreamer->EmitInstruction(Inst, getSubtargetInfo(), 105 EnablePrintSchedInfo && 106 !(Inst.getFlags() & X86::NO_SCHED_INFO)); 107 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get()); 108 } 109 110 X86MCInstLower::X86MCInstLower(const MachineFunction &mf, 111 X86AsmPrinter &asmprinter) 112 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()), 113 AsmPrinter(asmprinter) {} 114 115 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 116 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 117 } 118 119 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 120 /// operand to an MCSymbol. 121 MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const { 122 const DataLayout &DL = MF.getDataLayout(); 123 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && 124 "Isn't a symbol reference"); 125 126 MCSymbol *Sym = nullptr; 127 SmallString<128> Name; 128 StringRef Suffix; 129 130 switch (MO.getTargetFlags()) { 131 case X86II::MO_DLLIMPORT: 132 // Handle dllimport linkage. 133 Name += "__imp_"; 134 break; 135 case X86II::MO_DARWIN_NONLAZY: 136 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 137 Suffix = "$non_lazy_ptr"; 138 break; 139 } 140 141 if (!Suffix.empty()) 142 Name += DL.getPrivateGlobalPrefix(); 143 144 if (MO.isGlobal()) { 145 const GlobalValue *GV = MO.getGlobal(); 146 AsmPrinter.getNameWithPrefix(Name, GV); 147 } else if (MO.isSymbol()) { 148 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL); 149 } else if (MO.isMBB()) { 150 assert(Suffix.empty()); 151 Sym = MO.getMBB()->getSymbol(); 152 } 153 154 Name += Suffix; 155 if (!Sym) 156 Sym = Ctx.getOrCreateSymbol(Name); 157 158 // If the target flags on the operand changes the name of the symbol, do that 159 // before we return the symbol. 160 switch (MO.getTargetFlags()) { 161 default: 162 break; 163 case X86II::MO_DARWIN_NONLAZY: 164 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 165 MachineModuleInfoImpl::StubValueTy &StubSym = 166 getMachOMMI().getGVStubEntry(Sym); 167 if (!StubSym.getPointer()) { 168 assert(MO.isGlobal() && "Extern symbol not handled yet"); 169 StubSym = MachineModuleInfoImpl::StubValueTy( 170 AsmPrinter.getSymbol(MO.getGlobal()), 171 !MO.getGlobal()->hasInternalLinkage()); 172 } 173 break; 174 } 175 } 176 177 return Sym; 178 } 179 180 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 181 MCSymbol *Sym) const { 182 // FIXME: We would like an efficient form for this, so we don't have to do a 183 // lot of extra uniquing. 184 const MCExpr *Expr = nullptr; 185 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 186 187 switch (MO.getTargetFlags()) { 188 default: 189 llvm_unreachable("Unknown target flag on GV operand"); 190 case X86II::MO_NO_FLAG: // No flag. 191 // These affect the name of the symbol, not any suffix. 192 case X86II::MO_DARWIN_NONLAZY: 193 case X86II::MO_DLLIMPORT: 194 break; 195 196 case X86II::MO_TLVP: 197 RefKind = MCSymbolRefExpr::VK_TLVP; 198 break; 199 case X86II::MO_TLVP_PIC_BASE: 200 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 201 // Subtract the pic base. 202 Expr = MCBinaryExpr::createSub( 203 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx); 204 break; 205 case X86II::MO_SECREL: 206 RefKind = MCSymbolRefExpr::VK_SECREL; 207 break; 208 case X86II::MO_TLSGD: 209 RefKind = MCSymbolRefExpr::VK_TLSGD; 210 break; 211 case X86II::MO_TLSLD: 212 RefKind = MCSymbolRefExpr::VK_TLSLD; 213 break; 214 case X86II::MO_TLSLDM: 215 RefKind = MCSymbolRefExpr::VK_TLSLDM; 216 break; 217 case X86II::MO_GOTTPOFF: 218 RefKind = MCSymbolRefExpr::VK_GOTTPOFF; 219 break; 220 case X86II::MO_INDNTPOFF: 221 RefKind = MCSymbolRefExpr::VK_INDNTPOFF; 222 break; 223 case X86II::MO_TPOFF: 224 RefKind = MCSymbolRefExpr::VK_TPOFF; 225 break; 226 case X86II::MO_DTPOFF: 227 RefKind = MCSymbolRefExpr::VK_DTPOFF; 228 break; 229 case X86II::MO_NTPOFF: 230 RefKind = MCSymbolRefExpr::VK_NTPOFF; 231 break; 232 case X86II::MO_GOTNTPOFF: 233 RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; 234 break; 235 case X86II::MO_GOTPCREL: 236 RefKind = MCSymbolRefExpr::VK_GOTPCREL; 237 break; 238 case X86II::MO_GOT: 239 RefKind = MCSymbolRefExpr::VK_GOT; 240 break; 241 case X86II::MO_GOTOFF: 242 RefKind = MCSymbolRefExpr::VK_GOTOFF; 243 break; 244 case X86II::MO_PLT: 245 RefKind = MCSymbolRefExpr::VK_PLT; 246 break; 247 case X86II::MO_ABS8: 248 RefKind = MCSymbolRefExpr::VK_X86_ABS8; 249 break; 250 case X86II::MO_PIC_BASE_OFFSET: 251 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 252 Expr = MCSymbolRefExpr::create(Sym, Ctx); 253 // Subtract the pic base. 254 Expr = MCBinaryExpr::createSub( 255 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx); 256 if (MO.isJTI()) { 257 assert(MAI.doesSetDirectiveSuppressReloc()); 258 // If .set directive is supported, use it to reduce the number of 259 // relocations the assembler will generate for differences between 260 // local labels. This is only safe when the symbols are in the same 261 // section so we are restricting it to jumptable references. 262 MCSymbol *Label = Ctx.createTempSymbol(); 263 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr); 264 Expr = MCSymbolRefExpr::create(Label, Ctx); 265 } 266 break; 267 } 268 269 if (!Expr) 270 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx); 271 272 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 273 Expr = MCBinaryExpr::createAdd( 274 Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); 275 return MCOperand::createExpr(Expr); 276 } 277 278 /// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 279 /// a short fixed-register form. 280 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 281 unsigned ImmOp = Inst.getNumOperands() - 1; 282 assert(Inst.getOperand(0).isReg() && 283 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 284 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 285 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 286 Inst.getNumOperands() == 2) && 287 "Unexpected instruction!"); 288 289 // Check whether the destination register can be fixed. 290 unsigned Reg = Inst.getOperand(0).getReg(); 291 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 292 return; 293 294 // If so, rewrite the instruction. 295 MCOperand Saved = Inst.getOperand(ImmOp); 296 Inst = MCInst(); 297 Inst.setOpcode(Opcode); 298 Inst.addOperand(Saved); 299 } 300 301 /// If a movsx instruction has a shorter encoding for the used register 302 /// simplify the instruction to use it instead. 303 static void SimplifyMOVSX(MCInst &Inst) { 304 unsigned NewOpcode = 0; 305 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 306 switch (Inst.getOpcode()) { 307 default: 308 llvm_unreachable("Unexpected instruction!"); 309 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 310 if (Op0 == X86::AX && Op1 == X86::AL) 311 NewOpcode = X86::CBW; 312 break; 313 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 314 if (Op0 == X86::EAX && Op1 == X86::AX) 315 NewOpcode = X86::CWDE; 316 break; 317 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 318 if (Op0 == X86::RAX && Op1 == X86::EAX) 319 NewOpcode = X86::CDQE; 320 break; 321 } 322 323 if (NewOpcode != 0) { 324 Inst = MCInst(); 325 Inst.setOpcode(NewOpcode); 326 } 327 } 328 329 /// Simplify things like MOV32rm to MOV32o32a. 330 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 331 unsigned Opcode) { 332 // Don't make these simplifications in 64-bit mode; other assemblers don't 333 // perform them because they make the code larger. 334 if (Printer.getSubtarget().is64Bit()) 335 return; 336 337 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 338 unsigned AddrBase = IsStore; 339 unsigned RegOp = IsStore ? 0 : 5; 340 unsigned AddrOp = AddrBase + 3; 341 assert( 342 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 343 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && 344 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && 345 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && 346 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && 347 (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) && 348 "Unexpected instruction!"); 349 350 // Check whether the destination register can be fixed. 351 unsigned Reg = Inst.getOperand(RegOp).getReg(); 352 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 353 return; 354 355 // Check whether this is an absolute address. 356 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 357 // to do this here. 358 bool Absolute = true; 359 if (Inst.getOperand(AddrOp).isExpr()) { 360 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 361 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 362 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 363 Absolute = false; 364 } 365 366 if (Absolute && 367 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || 368 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || 369 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) 370 return; 371 372 // If so, rewrite the instruction. 373 MCOperand Saved = Inst.getOperand(AddrOp); 374 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); 375 Inst = MCInst(); 376 Inst.setOpcode(Opcode); 377 Inst.addOperand(Saved); 378 Inst.addOperand(Seg); 379 } 380 381 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { 382 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 383 } 384 385 Optional<MCOperand> 386 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI, 387 const MachineOperand &MO) const { 388 switch (MO.getType()) { 389 default: 390 MI->print(errs()); 391 llvm_unreachable("unknown operand type"); 392 case MachineOperand::MO_Register: 393 // Ignore all implicit register operands. 394 if (MO.isImplicit()) 395 return None; 396 return MCOperand::createReg(MO.getReg()); 397 case MachineOperand::MO_Immediate: 398 return MCOperand::createImm(MO.getImm()); 399 case MachineOperand::MO_MachineBasicBlock: 400 case MachineOperand::MO_GlobalAddress: 401 case MachineOperand::MO_ExternalSymbol: 402 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 403 case MachineOperand::MO_MCSymbol: 404 return LowerSymbolOperand(MO, MO.getMCSymbol()); 405 case MachineOperand::MO_JumpTableIndex: 406 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 407 case MachineOperand::MO_ConstantPoolIndex: 408 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 409 case MachineOperand::MO_BlockAddress: 410 return LowerSymbolOperand( 411 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 412 case MachineOperand::MO_RegisterMask: 413 // Ignore call clobbers. 414 return None; 415 } 416 } 417 418 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 419 OutMI.setOpcode(MI->getOpcode()); 420 421 for (const MachineOperand &MO : MI->operands()) 422 if (auto MaybeMCOp = LowerMachineOperand(MI, MO)) 423 OutMI.addOperand(MaybeMCOp.getValue()); 424 425 // Handle a few special cases to eliminate operand modifiers. 426 ReSimplify: 427 switch (OutMI.getOpcode()) { 428 case X86::LEA64_32r: 429 case X86::LEA64r: 430 case X86::LEA16r: 431 case X86::LEA32r: 432 // LEA should have a segment register, but it must be empty. 433 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands && 434 "Unexpected # of LEA operands"); 435 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && 436 "LEA has segment specified!"); 437 break; 438 439 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 440 // if one of the registers is extended, but other isn't. 441 case X86::VMOVZPQILo2PQIrr: 442 case X86::VMOVAPDrr: 443 case X86::VMOVAPDYrr: 444 case X86::VMOVAPSrr: 445 case X86::VMOVAPSYrr: 446 case X86::VMOVDQArr: 447 case X86::VMOVDQAYrr: 448 case X86::VMOVDQUrr: 449 case X86::VMOVDQUYrr: 450 case X86::VMOVUPDrr: 451 case X86::VMOVUPDYrr: 452 case X86::VMOVUPSrr: 453 case X86::VMOVUPSYrr: { 454 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 455 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 456 unsigned NewOpc; 457 switch (OutMI.getOpcode()) { 458 default: llvm_unreachable("Invalid opcode"); 459 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; 460 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 461 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 462 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 463 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 464 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 465 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 466 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 467 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 468 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 469 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 470 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 471 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 472 } 473 OutMI.setOpcode(NewOpc); 474 } 475 break; 476 } 477 case X86::VMOVSDrr: 478 case X86::VMOVSSrr: { 479 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 480 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 481 unsigned NewOpc; 482 switch (OutMI.getOpcode()) { 483 default: llvm_unreachable("Invalid opcode"); 484 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 485 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 486 } 487 OutMI.setOpcode(NewOpc); 488 } 489 break; 490 } 491 492 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 493 // inputs modeled as normal uses instead of implicit uses. As such, truncate 494 // off all but the first operand (the callee). FIXME: Change isel. 495 case X86::TAILJMPr64: 496 case X86::TAILJMPr64_REX: 497 case X86::CALL64r: 498 case X86::CALL64pcrel32: { 499 unsigned Opcode = OutMI.getOpcode(); 500 MCOperand Saved = OutMI.getOperand(0); 501 OutMI = MCInst(); 502 OutMI.setOpcode(Opcode); 503 OutMI.addOperand(Saved); 504 break; 505 } 506 507 case X86::EH_RETURN: 508 case X86::EH_RETURN64: { 509 OutMI = MCInst(); 510 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 511 break; 512 } 513 514 case X86::CLEANUPRET: { 515 // Replace CATCHRET with the appropriate RET. 516 OutMI = MCInst(); 517 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 518 break; 519 } 520 521 case X86::CATCHRET: { 522 // Replace CATCHRET with the appropriate RET. 523 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); 524 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 525 OutMI = MCInst(); 526 OutMI.setOpcode(getRetOpcode(Subtarget)); 527 OutMI.addOperand(MCOperand::createReg(ReturnReg)); 528 break; 529 } 530 531 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump 532 // instruction. 533 { 534 unsigned Opcode; 535 case X86::TAILJMPr: 536 Opcode = X86::JMP32r; 537 goto SetTailJmpOpcode; 538 case X86::TAILJMPd: 539 case X86::TAILJMPd64: 540 Opcode = X86::JMP_1; 541 goto SetTailJmpOpcode; 542 case X86::TAILJMPd_CC: 543 case X86::TAILJMPd64_CC: 544 Opcode = X86::GetCondBranchFromCond( 545 static_cast<X86::CondCode>(MI->getOperand(1).getImm())); 546 goto SetTailJmpOpcode; 547 548 SetTailJmpOpcode: 549 MCOperand Saved = OutMI.getOperand(0); 550 OutMI = MCInst(); 551 OutMI.setOpcode(Opcode); 552 OutMI.addOperand(Saved); 553 break; 554 } 555 556 case X86::DEC16r: 557 case X86::DEC32r: 558 case X86::INC16r: 559 case X86::INC32r: 560 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions. 561 if (!AsmPrinter.getSubtarget().is64Bit()) { 562 unsigned Opcode; 563 switch (OutMI.getOpcode()) { 564 default: llvm_unreachable("Invalid opcode"); 565 case X86::DEC16r: Opcode = X86::DEC16r_alt; break; 566 case X86::DEC32r: Opcode = X86::DEC32r_alt; break; 567 case X86::INC16r: Opcode = X86::INC16r_alt; break; 568 case X86::INC32r: Opcode = X86::INC32r_alt; break; 569 } 570 OutMI.setOpcode(Opcode); 571 } 572 break; 573 574 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 575 // this with an ugly goto in case the resultant OR uses EAX and needs the 576 // short form. 577 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 578 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 579 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 580 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 581 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 582 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 583 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 584 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 585 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 586 587 // We don't currently select the correct instruction form for instructions 588 // which have a short %eax, etc. form. Handle this by custom lowering, for 589 // now. 590 // 591 // Note, we are currently not handling the following instructions: 592 // MOV64ao8, MOV64o8a 593 // XCHG16ar, XCHG32ar, XCHG64ar 594 case X86::MOV8mr_NOREX: 595 case X86::MOV8mr: 596 case X86::MOV8rm_NOREX: 597 case X86::MOV8rm: 598 case X86::MOV16mr: 599 case X86::MOV16rm: 600 case X86::MOV32mr: 601 case X86::MOV32rm: { 602 unsigned NewOpc; 603 switch (OutMI.getOpcode()) { 604 default: llvm_unreachable("Invalid opcode"); 605 case X86::MOV8mr_NOREX: 606 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; 607 case X86::MOV8rm_NOREX: 608 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; 609 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; 610 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; 611 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break; 612 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break; 613 } 614 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc); 615 break; 616 } 617 618 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32: 619 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32: 620 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32: 621 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32: 622 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32: 623 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32: 624 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32: 625 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32: 626 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: { 627 unsigned NewOpc; 628 switch (OutMI.getOpcode()) { 629 default: llvm_unreachable("Invalid opcode"); 630 case X86::ADC8ri: NewOpc = X86::ADC8i8; break; 631 case X86::ADC16ri: NewOpc = X86::ADC16i16; break; 632 case X86::ADC32ri: NewOpc = X86::ADC32i32; break; 633 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break; 634 case X86::ADD8ri: NewOpc = X86::ADD8i8; break; 635 case X86::ADD16ri: NewOpc = X86::ADD16i16; break; 636 case X86::ADD32ri: NewOpc = X86::ADD32i32; break; 637 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break; 638 case X86::AND8ri: NewOpc = X86::AND8i8; break; 639 case X86::AND16ri: NewOpc = X86::AND16i16; break; 640 case X86::AND32ri: NewOpc = X86::AND32i32; break; 641 case X86::AND64ri32: NewOpc = X86::AND64i32; break; 642 case X86::CMP8ri: NewOpc = X86::CMP8i8; break; 643 case X86::CMP16ri: NewOpc = X86::CMP16i16; break; 644 case X86::CMP32ri: NewOpc = X86::CMP32i32; break; 645 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break; 646 case X86::OR8ri: NewOpc = X86::OR8i8; break; 647 case X86::OR16ri: NewOpc = X86::OR16i16; break; 648 case X86::OR32ri: NewOpc = X86::OR32i32; break; 649 case X86::OR64ri32: NewOpc = X86::OR64i32; break; 650 case X86::SBB8ri: NewOpc = X86::SBB8i8; break; 651 case X86::SBB16ri: NewOpc = X86::SBB16i16; break; 652 case X86::SBB32ri: NewOpc = X86::SBB32i32; break; 653 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break; 654 case X86::SUB8ri: NewOpc = X86::SUB8i8; break; 655 case X86::SUB16ri: NewOpc = X86::SUB16i16; break; 656 case X86::SUB32ri: NewOpc = X86::SUB32i32; break; 657 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break; 658 case X86::TEST8ri: NewOpc = X86::TEST8i8; break; 659 case X86::TEST16ri: NewOpc = X86::TEST16i16; break; 660 case X86::TEST32ri: NewOpc = X86::TEST32i32; break; 661 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break; 662 case X86::XOR8ri: NewOpc = X86::XOR8i8; break; 663 case X86::XOR16ri: NewOpc = X86::XOR16i16; break; 664 case X86::XOR32ri: NewOpc = X86::XOR32i32; break; 665 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break; 666 } 667 SimplifyShortImmForm(OutMI, NewOpc); 668 break; 669 } 670 671 // Try to shrink some forms of movsx. 672 case X86::MOVSX16rr8: 673 case X86::MOVSX32rr16: 674 case X86::MOVSX64rr32: 675 SimplifyMOVSX(OutMI); 676 break; 677 } 678 } 679 680 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering, 681 const MachineInstr &MI) { 682 683 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || 684 MI.getOpcode() == X86::TLS_base_addr64; 685 686 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; 687 688 MCContext &context = OutStreamer->getContext(); 689 690 if (needsPadding) 691 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 692 693 MCSymbolRefExpr::VariantKind SRVK; 694 switch (MI.getOpcode()) { 695 case X86::TLS_addr32: 696 case X86::TLS_addr64: 697 SRVK = MCSymbolRefExpr::VK_TLSGD; 698 break; 699 case X86::TLS_base_addr32: 700 SRVK = MCSymbolRefExpr::VK_TLSLDM; 701 break; 702 case X86::TLS_base_addr64: 703 SRVK = MCSymbolRefExpr::VK_TLSLD; 704 break; 705 default: 706 llvm_unreachable("unexpected opcode"); 707 } 708 709 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 710 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context); 711 712 MCInst LEA; 713 if (is64Bits) { 714 LEA.setOpcode(X86::LEA64r); 715 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest 716 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base 717 LEA.addOperand(MCOperand::createImm(1)); // scale 718 LEA.addOperand(MCOperand::createReg(0)); // index 719 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 720 LEA.addOperand(MCOperand::createReg(0)); // seg 721 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) { 722 LEA.setOpcode(X86::LEA32r); 723 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 724 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base 725 LEA.addOperand(MCOperand::createImm(1)); // scale 726 LEA.addOperand(MCOperand::createReg(0)); // index 727 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 728 LEA.addOperand(MCOperand::createReg(0)); // seg 729 } else { 730 LEA.setOpcode(X86::LEA32r); 731 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 732 LEA.addOperand(MCOperand::createReg(0)); // base 733 LEA.addOperand(MCOperand::createImm(1)); // scale 734 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index 735 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 736 LEA.addOperand(MCOperand::createReg(0)); // seg 737 } 738 EmitAndCountInstruction(LEA); 739 740 if (needsPadding) { 741 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 742 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 743 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX)); 744 } 745 746 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 747 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name); 748 const MCSymbolRefExpr *tlsRef = 749 MCSymbolRefExpr::create(tlsGetAddr, MCSymbolRefExpr::VK_PLT, context); 750 751 EmitAndCountInstruction( 752 MCInstBuilder(is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32) 753 .addExpr(tlsRef)); 754 } 755 756 /// Emit the largest nop instruction smaller than or equal to \p NumBytes 757 /// bytes. Return the size of nop emitted. 758 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 759 const MCSubtargetInfo &STI) { 760 // This works only for 64bit. For 32bit we have to do additional checking if 761 // the CPU supports multi-byte nops. 762 assert(Is64Bit && "EmitNops only supports X86-64"); 763 764 unsigned NopSize; 765 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; 766 Opc = IndexReg = Displacement = SegmentReg = 0; 767 BaseReg = X86::RAX; 768 ScaleVal = 1; 769 switch (NumBytes) { 770 case 0: 771 llvm_unreachable("Zero nops?"); 772 break; 773 case 1: 774 NopSize = 1; 775 Opc = X86::NOOP; 776 break; 777 case 2: 778 NopSize = 2; 779 Opc = X86::XCHG16ar; 780 break; 781 case 3: 782 NopSize = 3; 783 Opc = X86::NOOPL; 784 break; 785 case 4: 786 NopSize = 4; 787 Opc = X86::NOOPL; 788 Displacement = 8; 789 break; 790 case 5: 791 NopSize = 5; 792 Opc = X86::NOOPL; 793 Displacement = 8; 794 IndexReg = X86::RAX; 795 break; 796 case 6: 797 NopSize = 6; 798 Opc = X86::NOOPW; 799 Displacement = 8; 800 IndexReg = X86::RAX; 801 break; 802 case 7: 803 NopSize = 7; 804 Opc = X86::NOOPL; 805 Displacement = 512; 806 break; 807 case 8: 808 NopSize = 8; 809 Opc = X86::NOOPL; 810 Displacement = 512; 811 IndexReg = X86::RAX; 812 break; 813 case 9: 814 NopSize = 9; 815 Opc = X86::NOOPW; 816 Displacement = 512; 817 IndexReg = X86::RAX; 818 break; 819 default: 820 NopSize = 10; 821 Opc = X86::NOOPW; 822 Displacement = 512; 823 IndexReg = X86::RAX; 824 SegmentReg = X86::CS; 825 break; 826 } 827 828 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U); 829 NopSize += NumPrefixes; 830 for (unsigned i = 0; i != NumPrefixes; ++i) 831 OS.EmitBytes("\x66"); 832 833 switch (Opc) { 834 default: llvm_unreachable("Unexpected opcode"); 835 case X86::NOOP: 836 OS.EmitInstruction(MCInstBuilder(Opc), STI); 837 break; 838 case X86::XCHG16ar: 839 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI); 840 break; 841 case X86::NOOPL: 842 case X86::NOOPW: 843 OS.EmitInstruction(MCInstBuilder(Opc) 844 .addReg(BaseReg) 845 .addImm(ScaleVal) 846 .addReg(IndexReg) 847 .addImm(Displacement) 848 .addReg(SegmentReg), 849 STI); 850 break; 851 } 852 assert(NopSize <= NumBytes && "We overemitted?"); 853 return NopSize; 854 } 855 856 /// Emit the optimal amount of multi-byte nops on X86. 857 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 858 const MCSubtargetInfo &STI) { 859 unsigned NopsToEmit = NumBytes; 860 (void)NopsToEmit; 861 while (NumBytes) { 862 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI); 863 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!"); 864 } 865 } 866 867 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI, 868 X86MCInstLower &MCIL) { 869 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); 870 871 StatepointOpers SOpers(&MI); 872 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) { 873 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(), 874 getSubtargetInfo()); 875 } else { 876 // Lower call target and choose correct opcode 877 const MachineOperand &CallTarget = SOpers.getCallTarget(); 878 MCOperand CallTargetMCOp; 879 unsigned CallOpcode; 880 switch (CallTarget.getType()) { 881 case MachineOperand::MO_GlobalAddress: 882 case MachineOperand::MO_ExternalSymbol: 883 CallTargetMCOp = MCIL.LowerSymbolOperand( 884 CallTarget, MCIL.GetSymbolFromOperand(CallTarget)); 885 CallOpcode = X86::CALL64pcrel32; 886 // Currently, we only support relative addressing with statepoints. 887 // Otherwise, we'll need a scratch register to hold the target 888 // address. You'll fail asserts during load & relocation if this 889 // symbol is to far away. (TODO: support non-relative addressing) 890 break; 891 case MachineOperand::MO_Immediate: 892 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); 893 CallOpcode = X86::CALL64pcrel32; 894 // Currently, we only support relative addressing with statepoints. 895 // Otherwise, we'll need a scratch register to hold the target 896 // immediate. You'll fail asserts during load & relocation if this 897 // address is to far away. (TODO: support non-relative addressing) 898 break; 899 case MachineOperand::MO_Register: 900 // FIXME: Add retpoline support and remove this. 901 if (Subtarget->useRetpolineIndirectCalls()) 902 report_fatal_error("Lowering register statepoints with retpoline not " 903 "yet implemented."); 904 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); 905 CallOpcode = X86::CALL64r; 906 break; 907 default: 908 llvm_unreachable("Unsupported operand type in statepoint call target"); 909 break; 910 } 911 912 // Emit call 913 MCInst CallInst; 914 CallInst.setOpcode(CallOpcode); 915 CallInst.addOperand(CallTargetMCOp); 916 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo()); 917 } 918 919 // Record our statepoint node in the same section used by STACKMAP 920 // and PATCHPOINT 921 SM.recordStatepoint(MI); 922 } 923 924 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI, 925 X86MCInstLower &MCIL) { 926 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>, 927 // <opcode>, <operands> 928 929 unsigned DefRegister = FaultingMI.getOperand(0).getReg(); 930 FaultMaps::FaultKind FK = 931 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm()); 932 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol(); 933 unsigned Opcode = FaultingMI.getOperand(3).getImm(); 934 unsigned OperandsBeginIdx = 4; 935 936 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!"); 937 FM.recordFaultingOp(FK, HandlerLabel); 938 939 MCInst MI; 940 MI.setOpcode(Opcode); 941 942 if (DefRegister != X86::NoRegister) 943 MI.addOperand(MCOperand::createReg(DefRegister)); 944 945 for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx, 946 E = FaultingMI.operands_end(); 947 I != E; ++I) 948 if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *I)) 949 MI.addOperand(MaybeOperand.getValue()); 950 951 OutStreamer->EmitInstruction(MI, getSubtargetInfo()); 952 } 953 954 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI, 955 X86MCInstLower &MCIL) { 956 bool Is64Bits = Subtarget->is64Bit(); 957 MCContext &Ctx = OutStreamer->getContext(); 958 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__"); 959 const MCSymbolRefExpr *Op = 960 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_None, Ctx); 961 962 EmitAndCountInstruction( 963 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32) 964 .addExpr(Op)); 965 } 966 967 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, 968 X86MCInstLower &MCIL) { 969 // PATCHABLE_OP minsize, opcode, operands 970 971 unsigned MinSize = MI.getOperand(0).getImm(); 972 unsigned Opcode = MI.getOperand(1).getImm(); 973 974 MCInst MCI; 975 MCI.setOpcode(Opcode); 976 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end())) 977 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 978 MCI.addOperand(MaybeOperand.getValue()); 979 980 SmallString<256> Code; 981 SmallVector<MCFixup, 4> Fixups; 982 raw_svector_ostream VecOS(Code); 983 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo()); 984 985 if (Code.size() < MinSize) { 986 if (MinSize == 2 && Opcode == X86::PUSH64r) { 987 // This is an optimization that lets us get away without emitting a nop in 988 // many cases. 989 // 990 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two 991 // bytes too, so the check on MinSize is important. 992 MCI.setOpcode(X86::PUSH64rmr); 993 } else { 994 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(), 995 getSubtargetInfo()); 996 assert(NopSize == MinSize && "Could not implement MinSize!"); 997 (void)NopSize; 998 } 999 } 1000 1001 OutStreamer->EmitInstruction(MCI, getSubtargetInfo()); 1002 } 1003 1004 // Lower a stackmap of the form: 1005 // <id>, <shadowBytes>, ... 1006 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { 1007 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 1008 SM.recordStackMap(MI); 1009 unsigned NumShadowBytes = MI.getOperand(1).getImm(); 1010 SMShadowTracker.reset(NumShadowBytes); 1011 } 1012 1013 // Lower a patchpoint of the form: 1014 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ... 1015 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI, 1016 X86MCInstLower &MCIL) { 1017 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); 1018 1019 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 1020 1021 SM.recordPatchPoint(MI); 1022 1023 PatchPointOpers opers(&MI); 1024 unsigned ScratchIdx = opers.getNextScratchIdx(); 1025 unsigned EncodedBytes = 0; 1026 const MachineOperand &CalleeMO = opers.getCallTarget(); 1027 1028 // Check for null target. If target is non-null (i.e. is non-zero or is 1029 // symbolic) then emit a call. 1030 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) { 1031 MCOperand CalleeMCOp; 1032 switch (CalleeMO.getType()) { 1033 default: 1034 /// FIXME: Add a verifier check for bad callee types. 1035 llvm_unreachable("Unrecognized callee operand type."); 1036 case MachineOperand::MO_Immediate: 1037 if (CalleeMO.getImm()) 1038 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm()); 1039 break; 1040 case MachineOperand::MO_ExternalSymbol: 1041 case MachineOperand::MO_GlobalAddress: 1042 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO, 1043 MCIL.GetSymbolFromOperand(CalleeMO)); 1044 break; 1045 } 1046 1047 // Emit MOV to materialize the target address and the CALL to target. 1048 // This is encoded with 12-13 bytes, depending on which register is used. 1049 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg(); 1050 if (X86II::isX86_64ExtendedReg(ScratchReg)) 1051 EncodedBytes = 13; 1052 else 1053 EncodedBytes = 12; 1054 1055 EmitAndCountInstruction( 1056 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); 1057 // FIXME: Add retpoline support and remove this. 1058 if (Subtarget->useRetpolineIndirectCalls()) 1059 report_fatal_error( 1060 "Lowering patchpoint with retpoline not yet implemented."); 1061 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); 1062 } 1063 1064 // Emit padding. 1065 unsigned NumBytes = opers.getNumPatchBytes(); 1066 assert(NumBytes >= EncodedBytes && 1067 "Patchpoint can't request size less than the length of a call."); 1068 1069 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(), 1070 getSubtargetInfo()); 1071 } 1072 1073 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, 1074 X86MCInstLower &MCIL) { 1075 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64"); 1076 1077 // We want to emit the following pattern, which follows the x86 calling 1078 // convention to prepare for the trampoline call to be patched in. 1079 // 1080 // .p2align 1, ... 1081 // .Lxray_event_sled_N: 1082 // jmp +N // jump across the instrumentation sled 1083 // ... // set up arguments in register 1084 // callq __xray_CustomEvent@plt // force dependency to symbol 1085 // ... 1086 // <jump here> 1087 // 1088 // After patching, it would look something like: 1089 // 1090 // nopw (2-byte nop) 1091 // ... 1092 // callq __xrayCustomEvent // already lowered 1093 // ... 1094 // 1095 // --- 1096 // First we emit the label and the jump. 1097 auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true); 1098 OutStreamer->AddComment("# XRay Custom Event Log"); 1099 OutStreamer->EmitCodeAlignment(2); 1100 OutStreamer->EmitLabel(CurSled); 1101 1102 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1103 // an operand (computed as an offset from the jmp instruction). 1104 // FIXME: Find another less hacky way do force the relative jump. 1105 OutStreamer->EmitBinaryData("\xeb\x0f"); 1106 1107 // The default C calling convention will place two arguments into %rcx and 1108 // %rdx -- so we only work with those. 1109 unsigned DestRegs[] = {X86::RDI, X86::RSI}; 1110 bool UsedMask[] = {false, false}; 1111 // Filled out in loop. 1112 unsigned SrcRegs[] = {0, 0}; 1113 1114 // Then we put the operands in the %rdi and %rsi registers. We spill the 1115 // values in the register before we clobber them, and mark them as used in 1116 // UsedMask. In case the arguments are already in the correct register, we use 1117 // emit nops appropriately sized to keep the sled the same size in every 1118 // situation. 1119 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1120 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) { 1121 assert(Op->isReg() && "Only support arguments in registers"); 1122 SrcRegs[I] = Op->getReg(); 1123 if (SrcRegs[I] != DestRegs[I]) { 1124 UsedMask[I] = true; 1125 EmitAndCountInstruction( 1126 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); 1127 } else { 1128 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo()); 1129 } 1130 } 1131 1132 // Now that the register values are stashed, mov arguments into place. 1133 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1134 if (SrcRegs[I] != DestRegs[I]) 1135 EmitAndCountInstruction( 1136 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1137 1138 // We emit a hard dependency on the __xray_CustomEvent symbol, which is the 1139 // name of the trampoline to be implemented by the XRay runtime. 1140 auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent"); 1141 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym); 1142 if (isPositionIndependent()) 1143 TOp.setTargetFlags(X86II::MO_PLT); 1144 1145 // Emit the call instruction. 1146 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32) 1147 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym))); 1148 1149 // Restore caller-saved and used registers. 1150 for (unsigned I = sizeof UsedMask; I-- > 0;) 1151 if (UsedMask[I]) 1152 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); 1153 else 1154 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo()); 1155 1156 OutStreamer->AddComment("xray custom event end."); 1157 1158 // Record the sled version. Older versions of this sled were spelled 1159 // differently, so we let the runtime handle the different offsets we're 1160 // using. 1161 recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 1); 1162 } 1163 1164 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI, 1165 X86MCInstLower &MCIL) { 1166 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64"); 1167 1168 // We want to emit the following pattern, which follows the x86 calling 1169 // convention to prepare for the trampoline call to be patched in. 1170 // 1171 // .p2align 1, ... 1172 // .Lxray_event_sled_N: 1173 // jmp +N // jump across the instrumentation sled 1174 // ... // set up arguments in register 1175 // callq __xray_TypedEvent@plt // force dependency to symbol 1176 // ... 1177 // <jump here> 1178 // 1179 // After patching, it would look something like: 1180 // 1181 // nopw (2-byte nop) 1182 // ... 1183 // callq __xrayTypedEvent // already lowered 1184 // ... 1185 // 1186 // --- 1187 // First we emit the label and the jump. 1188 auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true); 1189 OutStreamer->AddComment("# XRay Typed Event Log"); 1190 OutStreamer->EmitCodeAlignment(2); 1191 OutStreamer->EmitLabel(CurSled); 1192 1193 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1194 // an operand (computed as an offset from the jmp instruction). 1195 // FIXME: Find another less hacky way do force the relative jump. 1196 OutStreamer->EmitBinaryData("\xeb\x14"); 1197 1198 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8, 1199 // so we'll work with those. Or we may be called via SystemV, in which case 1200 // we don't have to do any translation. 1201 unsigned DestRegs[] = {X86::RDI, X86::RSI, X86::RDX}; 1202 bool UsedMask[] = {false, false, false}; 1203 1204 // Will fill out src regs in the loop. 1205 unsigned SrcRegs[] = {0, 0, 0}; 1206 1207 // Then we put the operands in the SystemV registers. We spill the values in 1208 // the registers before we clobber them, and mark them as used in UsedMask. 1209 // In case the arguments are already in the correct register, we emit nops 1210 // appropriately sized to keep the sled the same size in every situation. 1211 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1212 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) { 1213 // TODO: Is register only support adequate? 1214 assert(Op->isReg() && "Only supports arguments in registers"); 1215 SrcRegs[I] = Op->getReg(); 1216 if (SrcRegs[I] != DestRegs[I]) { 1217 UsedMask[I] = true; 1218 EmitAndCountInstruction( 1219 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); 1220 } else { 1221 EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo()); 1222 } 1223 } 1224 1225 // In the above loop we only stash all of the destination registers or emit 1226 // nops if the arguments are already in the right place. Doing the actually 1227 // moving is postponed until after all the registers are stashed so nothing 1228 // is clobbers. We've already added nops to account for the size of mov and 1229 // push if the register is in the right place, so we only have to worry about 1230 // emitting movs. 1231 for (unsigned I = 0; I < MI.getNumOperands(); ++I) 1232 if (UsedMask[I]) 1233 EmitAndCountInstruction( 1234 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1235 1236 // We emit a hard dependency on the __xray_TypedEvent symbol, which is the 1237 // name of the trampoline to be implemented by the XRay runtime. 1238 auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent"); 1239 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym); 1240 if (isPositionIndependent()) 1241 TOp.setTargetFlags(X86II::MO_PLT); 1242 1243 // Emit the call instruction. 1244 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32) 1245 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym))); 1246 1247 // Restore caller-saved and used registers. 1248 for (unsigned I = sizeof UsedMask; I-- > 0;) 1249 if (UsedMask[I]) 1250 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); 1251 else 1252 EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo()); 1253 1254 OutStreamer->AddComment("xray typed event end."); 1255 1256 // Record the sled version. 1257 recordSled(CurSled, MI, SledKind::TYPED_EVENT, 0); 1258 } 1259 1260 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI, 1261 X86MCInstLower &MCIL) { 1262 // We want to emit the following pattern: 1263 // 1264 // .p2align 1, ... 1265 // .Lxray_sled_N: 1266 // jmp .tmpN 1267 // # 9 bytes worth of noops 1268 // 1269 // We need the 9 bytes because at runtime, we'd be patching over the full 11 1270 // bytes with the following pattern: 1271 // 1272 // mov %r10, <function id, 32-bit> // 6 bytes 1273 // call <relative offset, 32-bits> // 5 bytes 1274 // 1275 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1276 OutStreamer->EmitCodeAlignment(2); 1277 OutStreamer->EmitLabel(CurSled); 1278 1279 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1280 // an operand (computed as an offset from the jmp instruction). 1281 // FIXME: Find another less hacky way do force the relative jump. 1282 OutStreamer->EmitBytes("\xeb\x09"); 1283 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1284 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER); 1285 } 1286 1287 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI, 1288 X86MCInstLower &MCIL) { 1289 // Since PATCHABLE_RET takes the opcode of the return statement as an 1290 // argument, we use that to emit the correct form of the RET that we want. 1291 // i.e. when we see this: 1292 // 1293 // PATCHABLE_RET X86::RET ... 1294 // 1295 // We should emit the RET followed by sleds. 1296 // 1297 // .p2align 1, ... 1298 // .Lxray_sled_N: 1299 // ret # or equivalent instruction 1300 // # 10 bytes worth of noops 1301 // 1302 // This just makes sure that the alignment for the next instruction is 2. 1303 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1304 OutStreamer->EmitCodeAlignment(2); 1305 OutStreamer->EmitLabel(CurSled); 1306 unsigned OpCode = MI.getOperand(0).getImm(); 1307 MCInst Ret; 1308 Ret.setOpcode(OpCode); 1309 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1310 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1311 Ret.addOperand(MaybeOperand.getValue()); 1312 OutStreamer->EmitInstruction(Ret, getSubtargetInfo()); 1313 EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo()); 1314 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT); 1315 } 1316 1317 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, 1318 X86MCInstLower &MCIL) { 1319 // Like PATCHABLE_RET, we have the actual instruction in the operands to this 1320 // instruction so we lower that particular instruction and its operands. 1321 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how 1322 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to 1323 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual 1324 // tail call much like how we have it in PATCHABLE_RET. 1325 auto CurSled = OutContext.createTempSymbol("xray_sled_", true); 1326 OutStreamer->EmitCodeAlignment(2); 1327 OutStreamer->EmitLabel(CurSled); 1328 auto Target = OutContext.createTempSymbol(); 1329 1330 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as 1331 // an operand (computed as an offset from the jmp instruction). 1332 // FIXME: Find another less hacky way do force the relative jump. 1333 OutStreamer->EmitBytes("\xeb\x09"); 1334 EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo()); 1335 OutStreamer->EmitLabel(Target); 1336 recordSled(CurSled, MI, SledKind::TAIL_CALL); 1337 1338 unsigned OpCode = MI.getOperand(0).getImm(); 1339 MCInst TC; 1340 TC.setOpcode(OpCode); 1341 1342 // Before emitting the instruction, add a comment to indicate that this is 1343 // indeed a tail call. 1344 OutStreamer->AddComment("TAILCALL"); 1345 for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) 1346 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 1347 TC.addOperand(MaybeOperand.getValue()); 1348 OutStreamer->EmitInstruction(TC, getSubtargetInfo()); 1349 } 1350 1351 // Returns instruction preceding MBBI in MachineFunction. 1352 // If MBBI is the first instruction of the first basic block, returns null. 1353 static MachineBasicBlock::const_iterator 1354 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) { 1355 const MachineBasicBlock *MBB = MBBI->getParent(); 1356 while (MBBI == MBB->begin()) { 1357 if (MBB == &MBB->getParent()->front()) 1358 return MachineBasicBlock::const_iterator(); 1359 MBB = MBB->getPrevNode(); 1360 MBBI = MBB->end(); 1361 } 1362 return --MBBI; 1363 } 1364 1365 static const Constant *getConstantFromPool(const MachineInstr &MI, 1366 const MachineOperand &Op) { 1367 if (!Op.isCPI()) 1368 return nullptr; 1369 1370 ArrayRef<MachineConstantPoolEntry> Constants = 1371 MI.getParent()->getParent()->getConstantPool()->getConstants(); 1372 const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()]; 1373 1374 // Bail if this is a machine constant pool entry, we won't be able to dig out 1375 // anything useful. 1376 if (ConstantEntry.isMachineConstantPoolEntry()) 1377 return nullptr; 1378 1379 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal); 1380 assert((!C || ConstantEntry.getType() == C->getType()) && 1381 "Expected a constant of the same type!"); 1382 return C; 1383 } 1384 1385 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, 1386 unsigned SrcOp2Idx, ArrayRef<int> Mask) { 1387 std::string Comment; 1388 1389 // Compute the name for a register. This is really goofy because we have 1390 // multiple instruction printers that could (in theory) use different 1391 // names. Fortunately most people use the ATT style (outside of Windows) 1392 // and they actually agree on register naming here. Ultimately, this is 1393 // a comment, and so its OK if it isn't perfect. 1394 auto GetRegisterName = [](unsigned RegNum) -> StringRef { 1395 return X86ATTInstPrinter::getRegisterName(RegNum); 1396 }; 1397 1398 const MachineOperand &DstOp = MI->getOperand(0); 1399 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); 1400 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); 1401 1402 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; 1403 StringRef Src1Name = 1404 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; 1405 StringRef Src2Name = 1406 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; 1407 1408 // One source operand, fix the mask to print all elements in one span. 1409 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end()); 1410 if (Src1Name == Src2Name) 1411 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) 1412 if (ShuffleMask[i] >= e) 1413 ShuffleMask[i] -= e; 1414 1415 raw_string_ostream CS(Comment); 1416 CS << DstName; 1417 1418 // Handle AVX512 MASK/MASXZ write mask comments. 1419 // MASK: zmmX {%kY} 1420 // MASKZ: zmmX {%kY} {z} 1421 if (SrcOp1Idx > 1) { 1422 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask"); 1423 1424 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1); 1425 if (WriteMaskOp.isReg()) { 1426 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}"; 1427 1428 if (SrcOp1Idx == 2) { 1429 CS << " {z}"; 1430 } 1431 } 1432 } 1433 1434 CS << " = "; 1435 1436 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) { 1437 if (i != 0) 1438 CS << ","; 1439 if (ShuffleMask[i] == SM_SentinelZero) { 1440 CS << "zero"; 1441 continue; 1442 } 1443 1444 // Otherwise, it must come from src1 or src2. Print the span of elements 1445 // that comes from this src. 1446 bool isSrc1 = ShuffleMask[i] < (int)e; 1447 CS << (isSrc1 ? Src1Name : Src2Name) << '['; 1448 1449 bool IsFirst = true; 1450 while (i != e && ShuffleMask[i] != SM_SentinelZero && 1451 (ShuffleMask[i] < (int)e) == isSrc1) { 1452 if (!IsFirst) 1453 CS << ','; 1454 else 1455 IsFirst = false; 1456 if (ShuffleMask[i] == SM_SentinelUndef) 1457 CS << "u"; 1458 else 1459 CS << ShuffleMask[i] % (int)e; 1460 ++i; 1461 } 1462 CS << ']'; 1463 --i; // For loop increments element #. 1464 } 1465 CS.flush(); 1466 1467 return Comment; 1468 } 1469 1470 static void printConstant(const Constant *COp, raw_ostream &CS) { 1471 if (isa<UndefValue>(COp)) { 1472 CS << "u"; 1473 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) { 1474 if (CI->getBitWidth() <= 64) { 1475 CS << CI->getZExtValue(); 1476 } else { 1477 // print multi-word constant as (w0,w1) 1478 const auto &Val = CI->getValue(); 1479 CS << "("; 1480 for (int i = 0, N = Val.getNumWords(); i < N; ++i) { 1481 if (i > 0) 1482 CS << ","; 1483 CS << Val.getRawData()[i]; 1484 } 1485 CS << ")"; 1486 } 1487 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) { 1488 SmallString<32> Str; 1489 CF->getValueAPF().toString(Str); 1490 CS << Str; 1491 } else { 1492 CS << "?"; 1493 } 1494 } 1495 1496 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) { 1497 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1498 assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only"); 1499 const X86RegisterInfo *RI = 1500 MF->getSubtarget<X86Subtarget>().getRegisterInfo(); 1501 1502 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86. 1503 if (EmitFPOData) { 1504 X86TargetStreamer *XTS = 1505 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer()); 1506 switch (MI->getOpcode()) { 1507 case X86::SEH_PushReg: 1508 XTS->emitFPOPushReg(MI->getOperand(0).getImm()); 1509 break; 1510 case X86::SEH_StackAlloc: 1511 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm()); 1512 break; 1513 case X86::SEH_SetFrame: 1514 assert(MI->getOperand(1).getImm() == 0 && 1515 ".cv_fpo_setframe takes no offset"); 1516 XTS->emitFPOSetFrame(MI->getOperand(0).getImm()); 1517 break; 1518 case X86::SEH_EndPrologue: 1519 XTS->emitFPOEndPrologue(); 1520 break; 1521 case X86::SEH_SaveReg: 1522 case X86::SEH_SaveXMM: 1523 case X86::SEH_PushFrame: 1524 llvm_unreachable("SEH_ directive incompatible with FPO"); 1525 break; 1526 default: 1527 llvm_unreachable("expected SEH_ instruction"); 1528 } 1529 return; 1530 } 1531 1532 // Otherwise, use the .seh_ directives for all other Windows platforms. 1533 switch (MI->getOpcode()) { 1534 case X86::SEH_PushReg: 1535 OutStreamer->EmitWinCFIPushReg( 1536 RI->getSEHRegNum(MI->getOperand(0).getImm())); 1537 break; 1538 1539 case X86::SEH_SaveReg: 1540 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1541 MI->getOperand(1).getImm()); 1542 break; 1543 1544 case X86::SEH_SaveXMM: 1545 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1546 MI->getOperand(1).getImm()); 1547 break; 1548 1549 case X86::SEH_StackAlloc: 1550 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm()); 1551 break; 1552 1553 case X86::SEH_SetFrame: 1554 OutStreamer->EmitWinCFISetFrame( 1555 RI->getSEHRegNum(MI->getOperand(0).getImm()), 1556 MI->getOperand(1).getImm()); 1557 break; 1558 1559 case X86::SEH_PushFrame: 1560 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm()); 1561 break; 1562 1563 case X86::SEH_EndPrologue: 1564 OutStreamer->EmitWinCFIEndProlog(); 1565 break; 1566 1567 default: 1568 llvm_unreachable("expected SEH_ instruction"); 1569 } 1570 } 1571 1572 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 1573 X86MCInstLower MCInstLowering(*MF, *this); 1574 const X86RegisterInfo *RI = 1575 MF->getSubtarget<X86Subtarget>().getRegisterInfo(); 1576 1577 // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that 1578 // are compressed from EVEX encoding to VEX encoding. 1579 if (TM.Options.MCOptions.ShowMCEncoding) { 1580 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) 1581 OutStreamer->AddComment("EVEX TO VEX Compression ", false); 1582 } 1583 1584 switch (MI->getOpcode()) { 1585 case TargetOpcode::DBG_VALUE: 1586 llvm_unreachable("Should be handled target independently"); 1587 1588 // Emit nothing here but a comment if we can. 1589 case X86::Int_MemBarrier: 1590 OutStreamer->emitRawComment("MEMBARRIER"); 1591 return; 1592 1593 case X86::EH_RETURN: 1594 case X86::EH_RETURN64: { 1595 // Lower these as normal, but add some comments. 1596 unsigned Reg = MI->getOperand(0).getReg(); 1597 OutStreamer->AddComment(StringRef("eh_return, addr: %") + 1598 X86ATTInstPrinter::getRegisterName(Reg)); 1599 break; 1600 } 1601 case X86::CLEANUPRET: { 1602 // Lower these as normal, but add some comments. 1603 OutStreamer->AddComment("CLEANUPRET"); 1604 break; 1605 } 1606 1607 case X86::CATCHRET: { 1608 // Lower these as normal, but add some comments. 1609 OutStreamer->AddComment("CATCHRET"); 1610 break; 1611 } 1612 1613 case X86::TAILJMPr: 1614 case X86::TAILJMPm: 1615 case X86::TAILJMPd: 1616 case X86::TAILJMPd_CC: 1617 case X86::TAILJMPr64: 1618 case X86::TAILJMPm64: 1619 case X86::TAILJMPd64: 1620 case X86::TAILJMPd64_CC: 1621 case X86::TAILJMPr64_REX: 1622 case X86::TAILJMPm64_REX: 1623 // Lower these as normal, but add some comments. 1624 OutStreamer->AddComment("TAILCALL"); 1625 break; 1626 1627 case X86::TLS_addr32: 1628 case X86::TLS_addr64: 1629 case X86::TLS_base_addr32: 1630 case X86::TLS_base_addr64: 1631 return LowerTlsAddr(MCInstLowering, *MI); 1632 1633 case X86::MOVPC32r: { 1634 // This is a pseudo op for a two instruction sequence with a label, which 1635 // looks like: 1636 // call "L1$pb" 1637 // "L1$pb": 1638 // popl %esi 1639 1640 // Emit the call. 1641 MCSymbol *PICBase = MF->getPICBaseSymbol(); 1642 // FIXME: We would like an efficient form for this, so we don't have to do a 1643 // lot of extra uniquing. 1644 EmitAndCountInstruction( 1645 MCInstBuilder(X86::CALLpcrel32) 1646 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext))); 1647 1648 const X86FrameLowering *FrameLowering = 1649 MF->getSubtarget<X86Subtarget>().getFrameLowering(); 1650 bool hasFP = FrameLowering->hasFP(*MF); 1651 1652 // TODO: This is needed only if we require precise CFA. 1653 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() && 1654 !OutStreamer->getDwarfFrameInfos().back().End; 1655 1656 int stackGrowth = -RI->getSlotSize(); 1657 1658 if (HasActiveDwarfFrame && !hasFP) { 1659 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth); 1660 } 1661 1662 // Emit the label. 1663 OutStreamer->EmitLabel(PICBase); 1664 1665 // popl $reg 1666 EmitAndCountInstruction( 1667 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg())); 1668 1669 if (HasActiveDwarfFrame && !hasFP) { 1670 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth); 1671 } 1672 return; 1673 } 1674 1675 case X86::MOVGOT64r: { 1676 // Materializes the GOT for the 64-bit large code model. 1677 MCSymbol *DotSym = OutContext.createTempSymbol(); 1678 OutStreamer->EmitLabel(DotSym); 1679 1680 unsigned DstReg = MI->getOperand(0).getReg(); 1681 unsigned ScratchReg = MI->getOperand(1).getReg(); 1682 MCSymbol *GOTSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 1683 1684 // .LtmpN: leaq .LtmpN(%rip), %dst 1685 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext); 1686 EmitAndCountInstruction(MCInstBuilder(X86::LEA64r) 1687 .addReg(DstReg) // dest 1688 .addReg(X86::RIP) // base 1689 .addImm(1) // scale 1690 .addReg(0) // index 1691 .addExpr(DotExpr) // disp 1692 .addReg(0)); // seg 1693 1694 // movq $_GLOBAL_OFFSET_TABLE_ - .LtmpN, %scratch 1695 const MCExpr *GOTSymExpr = MCSymbolRefExpr::create(GOTSym, OutContext); 1696 const MCExpr *GOTDiffExpr = 1697 MCBinaryExpr::createSub(GOTSymExpr, DotExpr, OutContext); 1698 EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri) 1699 .addReg(ScratchReg) // dest 1700 .addExpr(GOTDiffExpr)); // disp 1701 1702 // addq %scratch, %dst 1703 EmitAndCountInstruction(MCInstBuilder(X86::ADD64rr) 1704 .addReg(DstReg) // dest 1705 .addReg(DstReg) // dest 1706 .addReg(ScratchReg)); // src 1707 return; 1708 } 1709 1710 case X86::ADD32ri: { 1711 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 1712 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 1713 break; 1714 1715 // Okay, we have something like: 1716 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 1717 1718 // For this, we want to print something like: 1719 // MYGLOBAL + (. - PICBASE) 1720 // However, we can't generate a ".", so just emit a new label here and refer 1721 // to it. 1722 MCSymbol *DotSym = OutContext.createTempSymbol(); 1723 OutStreamer->EmitLabel(DotSym); 1724 1725 // Now that we have emitted the label, lower the complex operand expression. 1726 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 1727 1728 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext); 1729 const MCExpr *PICBase = 1730 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext); 1731 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext); 1732 1733 DotExpr = MCBinaryExpr::createAdd( 1734 MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext); 1735 1736 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri) 1737 .addReg(MI->getOperand(0).getReg()) 1738 .addReg(MI->getOperand(1).getReg()) 1739 .addExpr(DotExpr)); 1740 return; 1741 } 1742 case TargetOpcode::STATEPOINT: 1743 return LowerSTATEPOINT(*MI, MCInstLowering); 1744 1745 case TargetOpcode::FAULTING_OP: 1746 return LowerFAULTING_OP(*MI, MCInstLowering); 1747 1748 case TargetOpcode::FENTRY_CALL: 1749 return LowerFENTRY_CALL(*MI, MCInstLowering); 1750 1751 case TargetOpcode::PATCHABLE_OP: 1752 return LowerPATCHABLE_OP(*MI, MCInstLowering); 1753 1754 case TargetOpcode::STACKMAP: 1755 return LowerSTACKMAP(*MI); 1756 1757 case TargetOpcode::PATCHPOINT: 1758 return LowerPATCHPOINT(*MI, MCInstLowering); 1759 1760 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: 1761 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering); 1762 1763 case TargetOpcode::PATCHABLE_RET: 1764 return LowerPATCHABLE_RET(*MI, MCInstLowering); 1765 1766 case TargetOpcode::PATCHABLE_TAIL_CALL: 1767 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering); 1768 1769 case TargetOpcode::PATCHABLE_EVENT_CALL: 1770 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering); 1771 1772 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL: 1773 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering); 1774 1775 case X86::MORESTACK_RET: 1776 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1777 return; 1778 1779 case X86::MORESTACK_RET_RESTORE_R10: 1780 // Return, then restore R10. 1781 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1782 EmitAndCountInstruction( 1783 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX)); 1784 return; 1785 1786 case X86::SEH_PushReg: 1787 case X86::SEH_SaveReg: 1788 case X86::SEH_SaveXMM: 1789 case X86::SEH_StackAlloc: 1790 case X86::SEH_SetFrame: 1791 case X86::SEH_PushFrame: 1792 case X86::SEH_EndPrologue: 1793 EmitSEHInstruction(MI); 1794 return; 1795 1796 case X86::SEH_Epilogue: { 1797 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); 1798 MachineBasicBlock::const_iterator MBBI(MI); 1799 // Check if preceded by a call and emit nop if so. 1800 for (MBBI = PrevCrossBBInst(MBBI); 1801 MBBI != MachineBasicBlock::const_iterator(); 1802 MBBI = PrevCrossBBInst(MBBI)) { 1803 // Conservatively assume that pseudo instructions don't emit code and keep 1804 // looking for a call. We may emit an unnecessary nop in some cases. 1805 if (!MBBI->isPseudo()) { 1806 if (MBBI->isCall()) 1807 EmitAndCountInstruction(MCInstBuilder(X86::NOOP)); 1808 break; 1809 } 1810 } 1811 return; 1812 } 1813 1814 // Lower PSHUFB and VPERMILP normally but add a comment if we can find 1815 // a constant shuffle mask. We won't be able to do this at the MC layer 1816 // because the mask isn't an immediate. 1817 case X86::PSHUFBrm: 1818 case X86::VPSHUFBrm: 1819 case X86::VPSHUFBYrm: 1820 case X86::VPSHUFBZ128rm: 1821 case X86::VPSHUFBZ128rmk: 1822 case X86::VPSHUFBZ128rmkz: 1823 case X86::VPSHUFBZ256rm: 1824 case X86::VPSHUFBZ256rmk: 1825 case X86::VPSHUFBZ256rmkz: 1826 case X86::VPSHUFBZrm: 1827 case X86::VPSHUFBZrmk: 1828 case X86::VPSHUFBZrmkz: { 1829 if (!OutStreamer->isVerboseAsm()) 1830 break; 1831 unsigned SrcIdx, MaskIdx; 1832 switch (MI->getOpcode()) { 1833 default: llvm_unreachable("Invalid opcode"); 1834 case X86::PSHUFBrm: 1835 case X86::VPSHUFBrm: 1836 case X86::VPSHUFBYrm: 1837 case X86::VPSHUFBZ128rm: 1838 case X86::VPSHUFBZ256rm: 1839 case X86::VPSHUFBZrm: 1840 SrcIdx = 1; MaskIdx = 5; break; 1841 case X86::VPSHUFBZ128rmkz: 1842 case X86::VPSHUFBZ256rmkz: 1843 case X86::VPSHUFBZrmkz: 1844 SrcIdx = 2; MaskIdx = 6; break; 1845 case X86::VPSHUFBZ128rmk: 1846 case X86::VPSHUFBZ256rmk: 1847 case X86::VPSHUFBZrmk: 1848 SrcIdx = 3; MaskIdx = 7; break; 1849 } 1850 1851 assert(MI->getNumOperands() >= 6 && 1852 "We should always have at least 6 operands!"); 1853 1854 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 1855 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1856 SmallVector<int, 64> Mask; 1857 DecodePSHUFBMask(C, Mask); 1858 if (!Mask.empty()) 1859 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask), 1860 !EnablePrintSchedInfo); 1861 } 1862 break; 1863 } 1864 1865 case X86::VPERMILPSrm: 1866 case X86::VPERMILPSYrm: 1867 case X86::VPERMILPSZ128rm: 1868 case X86::VPERMILPSZ128rmk: 1869 case X86::VPERMILPSZ128rmkz: 1870 case X86::VPERMILPSZ256rm: 1871 case X86::VPERMILPSZ256rmk: 1872 case X86::VPERMILPSZ256rmkz: 1873 case X86::VPERMILPSZrm: 1874 case X86::VPERMILPSZrmk: 1875 case X86::VPERMILPSZrmkz: 1876 case X86::VPERMILPDrm: 1877 case X86::VPERMILPDYrm: 1878 case X86::VPERMILPDZ128rm: 1879 case X86::VPERMILPDZ128rmk: 1880 case X86::VPERMILPDZ128rmkz: 1881 case X86::VPERMILPDZ256rm: 1882 case X86::VPERMILPDZ256rmk: 1883 case X86::VPERMILPDZ256rmkz: 1884 case X86::VPERMILPDZrm: 1885 case X86::VPERMILPDZrmk: 1886 case X86::VPERMILPDZrmkz: { 1887 if (!OutStreamer->isVerboseAsm()) 1888 break; 1889 unsigned SrcIdx, MaskIdx; 1890 unsigned ElSize; 1891 switch (MI->getOpcode()) { 1892 default: llvm_unreachable("Invalid opcode"); 1893 case X86::VPERMILPSrm: 1894 case X86::VPERMILPSYrm: 1895 case X86::VPERMILPSZ128rm: 1896 case X86::VPERMILPSZ256rm: 1897 case X86::VPERMILPSZrm: 1898 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; 1899 case X86::VPERMILPSZ128rmkz: 1900 case X86::VPERMILPSZ256rmkz: 1901 case X86::VPERMILPSZrmkz: 1902 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; 1903 case X86::VPERMILPSZ128rmk: 1904 case X86::VPERMILPSZ256rmk: 1905 case X86::VPERMILPSZrmk: 1906 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; 1907 case X86::VPERMILPDrm: 1908 case X86::VPERMILPDYrm: 1909 case X86::VPERMILPDZ128rm: 1910 case X86::VPERMILPDZ256rm: 1911 case X86::VPERMILPDZrm: 1912 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; 1913 case X86::VPERMILPDZ128rmkz: 1914 case X86::VPERMILPDZ256rmkz: 1915 case X86::VPERMILPDZrmkz: 1916 SrcIdx = 2; MaskIdx = 6; ElSize = 64; break; 1917 case X86::VPERMILPDZ128rmk: 1918 case X86::VPERMILPDZ256rmk: 1919 case X86::VPERMILPDZrmk: 1920 SrcIdx = 3; MaskIdx = 7; ElSize = 64; break; 1921 } 1922 1923 assert(MI->getNumOperands() >= 6 && 1924 "We should always have at least 6 operands!"); 1925 1926 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 1927 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1928 SmallVector<int, 16> Mask; 1929 DecodeVPERMILPMask(C, ElSize, Mask); 1930 if (!Mask.empty()) 1931 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask), 1932 !EnablePrintSchedInfo); 1933 } 1934 break; 1935 } 1936 1937 case X86::VPERMIL2PDrm: 1938 case X86::VPERMIL2PSrm: 1939 case X86::VPERMIL2PDYrm: 1940 case X86::VPERMIL2PSYrm: { 1941 if (!OutStreamer->isVerboseAsm()) 1942 break; 1943 assert(MI->getNumOperands() >= 8 && 1944 "We should always have at least 8 operands!"); 1945 1946 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); 1947 if (!CtrlOp.isImm()) 1948 break; 1949 1950 unsigned ElSize; 1951 switch (MI->getOpcode()) { 1952 default: llvm_unreachable("Invalid opcode"); 1953 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break; 1954 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break; 1955 } 1956 1957 const MachineOperand &MaskOp = MI->getOperand(6); 1958 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1959 SmallVector<int, 16> Mask; 1960 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask); 1961 if (!Mask.empty()) 1962 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask), 1963 !EnablePrintSchedInfo); 1964 } 1965 break; 1966 } 1967 1968 case X86::VPPERMrrm: { 1969 if (!OutStreamer->isVerboseAsm()) 1970 break; 1971 assert(MI->getNumOperands() >= 7 && 1972 "We should always have at least 7 operands!"); 1973 1974 const MachineOperand &MaskOp = MI->getOperand(6); 1975 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1976 SmallVector<int, 16> Mask; 1977 DecodeVPPERMMask(C, Mask); 1978 if (!Mask.empty()) 1979 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask), 1980 !EnablePrintSchedInfo); 1981 } 1982 break; 1983 } 1984 1985 case X86::MMX_MOVQ64rm: { 1986 if (!OutStreamer->isVerboseAsm()) 1987 break; 1988 if (MI->getNumOperands() <= 4) 1989 break; 1990 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 1991 std::string Comment; 1992 raw_string_ostream CS(Comment); 1993 const MachineOperand &DstOp = MI->getOperand(0); 1994 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 1995 if (auto *CF = dyn_cast<ConstantFP>(C)) { 1996 CS << "0x" << CF->getValueAPF().bitcastToAPInt().toString(16, false); 1997 OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo); 1998 } 1999 } 2000 break; 2001 } 2002 2003 #define MOV_CASE(Prefix, Suffix) \ 2004 case X86::Prefix##MOVAPD##Suffix##rm: \ 2005 case X86::Prefix##MOVAPS##Suffix##rm: \ 2006 case X86::Prefix##MOVUPD##Suffix##rm: \ 2007 case X86::Prefix##MOVUPS##Suffix##rm: \ 2008 case X86::Prefix##MOVDQA##Suffix##rm: \ 2009 case X86::Prefix##MOVDQU##Suffix##rm: 2010 2011 #define MOV_AVX512_CASE(Suffix) \ 2012 case X86::VMOVDQA64##Suffix##rm: \ 2013 case X86::VMOVDQA32##Suffix##rm: \ 2014 case X86::VMOVDQU64##Suffix##rm: \ 2015 case X86::VMOVDQU32##Suffix##rm: \ 2016 case X86::VMOVDQU16##Suffix##rm: \ 2017 case X86::VMOVDQU8##Suffix##rm: \ 2018 case X86::VMOVAPS##Suffix##rm: \ 2019 case X86::VMOVAPD##Suffix##rm: \ 2020 case X86::VMOVUPS##Suffix##rm: \ 2021 case X86::VMOVUPD##Suffix##rm: 2022 2023 #define CASE_ALL_MOV_RM() \ 2024 MOV_CASE(, ) /* SSE */ \ 2025 MOV_CASE(V, ) /* AVX-128 */ \ 2026 MOV_CASE(V, Y) /* AVX-256 */ \ 2027 MOV_AVX512_CASE(Z) \ 2028 MOV_AVX512_CASE(Z256) \ 2029 MOV_AVX512_CASE(Z128) 2030 2031 // For loads from a constant pool to a vector register, print the constant 2032 // loaded. 2033 CASE_ALL_MOV_RM() 2034 case X86::VBROADCASTF128: 2035 case X86::VBROADCASTI128: 2036 case X86::VBROADCASTF32X4Z256rm: 2037 case X86::VBROADCASTF32X4rm: 2038 case X86::VBROADCASTF32X8rm: 2039 case X86::VBROADCASTF64X2Z128rm: 2040 case X86::VBROADCASTF64X2rm: 2041 case X86::VBROADCASTF64X4rm: 2042 case X86::VBROADCASTI32X4Z256rm: 2043 case X86::VBROADCASTI32X4rm: 2044 case X86::VBROADCASTI32X8rm: 2045 case X86::VBROADCASTI64X2Z128rm: 2046 case X86::VBROADCASTI64X2rm: 2047 case X86::VBROADCASTI64X4rm: 2048 if (!OutStreamer->isVerboseAsm()) 2049 break; 2050 if (MI->getNumOperands() <= 4) 2051 break; 2052 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2053 int NumLanes = 1; 2054 // Override NumLanes for the broadcast instructions. 2055 switch (MI->getOpcode()) { 2056 case X86::VBROADCASTF128: NumLanes = 2; break; 2057 case X86::VBROADCASTI128: NumLanes = 2; break; 2058 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break; 2059 case X86::VBROADCASTF32X4rm: NumLanes = 4; break; 2060 case X86::VBROADCASTF32X8rm: NumLanes = 2; break; 2061 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break; 2062 case X86::VBROADCASTF64X2rm: NumLanes = 4; break; 2063 case X86::VBROADCASTF64X4rm: NumLanes = 2; break; 2064 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break; 2065 case X86::VBROADCASTI32X4rm: NumLanes = 4; break; 2066 case X86::VBROADCASTI32X8rm: NumLanes = 2; break; 2067 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break; 2068 case X86::VBROADCASTI64X2rm: NumLanes = 4; break; 2069 case X86::VBROADCASTI64X4rm: NumLanes = 2; break; 2070 } 2071 2072 std::string Comment; 2073 raw_string_ostream CS(Comment); 2074 const MachineOperand &DstOp = MI->getOperand(0); 2075 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 2076 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) { 2077 CS << "["; 2078 for (int l = 0; l != NumLanes; ++l) { 2079 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; 2080 ++i) { 2081 if (i != 0 || l != 0) 2082 CS << ","; 2083 if (CDS->getElementType()->isIntegerTy()) 2084 CS << CDS->getElementAsInteger(i); 2085 else if (CDS->getElementType()->isFloatTy()) 2086 CS << CDS->getElementAsFloat(i); 2087 else if (CDS->getElementType()->isDoubleTy()) 2088 CS << CDS->getElementAsDouble(i); 2089 else 2090 CS << "?"; 2091 } 2092 } 2093 CS << "]"; 2094 OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo); 2095 } else if (auto *CV = dyn_cast<ConstantVector>(C)) { 2096 CS << "<"; 2097 for (int l = 0; l != NumLanes; ++l) { 2098 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; 2099 ++i) { 2100 if (i != 0 || l != 0) 2101 CS << ","; 2102 printConstant(CV->getOperand(i), CS); 2103 } 2104 } 2105 CS << ">"; 2106 OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo); 2107 } 2108 } 2109 break; 2110 case X86::VBROADCASTSSrm: 2111 case X86::VBROADCASTSSYrm: 2112 case X86::VBROADCASTSSZ128m: 2113 case X86::VBROADCASTSSZ256m: 2114 case X86::VBROADCASTSSZm: 2115 case X86::VBROADCASTSDYrm: 2116 case X86::VBROADCASTSDZ256m: 2117 case X86::VBROADCASTSDZm: 2118 case X86::VPBROADCASTBrm: 2119 case X86::VPBROADCASTBYrm: 2120 case X86::VPBROADCASTBZ128m: 2121 case X86::VPBROADCASTBZ256m: 2122 case X86::VPBROADCASTBZm: 2123 case X86::VPBROADCASTDrm: 2124 case X86::VPBROADCASTDYrm: 2125 case X86::VPBROADCASTDZ128m: 2126 case X86::VPBROADCASTDZ256m: 2127 case X86::VPBROADCASTDZm: 2128 case X86::VPBROADCASTQrm: 2129 case X86::VPBROADCASTQYrm: 2130 case X86::VPBROADCASTQZ128m: 2131 case X86::VPBROADCASTQZ256m: 2132 case X86::VPBROADCASTQZm: 2133 case X86::VPBROADCASTWrm: 2134 case X86::VPBROADCASTWYrm: 2135 case X86::VPBROADCASTWZ128m: 2136 case X86::VPBROADCASTWZ256m: 2137 case X86::VPBROADCASTWZm: 2138 if (!OutStreamer->isVerboseAsm()) 2139 break; 2140 if (MI->getNumOperands() <= 4) 2141 break; 2142 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2143 int NumElts; 2144 switch (MI->getOpcode()) { 2145 default: llvm_unreachable("Invalid opcode"); 2146 case X86::VBROADCASTSSrm: NumElts = 4; break; 2147 case X86::VBROADCASTSSYrm: NumElts = 8; break; 2148 case X86::VBROADCASTSSZ128m: NumElts = 4; break; 2149 case X86::VBROADCASTSSZ256m: NumElts = 8; break; 2150 case X86::VBROADCASTSSZm: NumElts = 16; break; 2151 case X86::VBROADCASTSDYrm: NumElts = 4; break; 2152 case X86::VBROADCASTSDZ256m: NumElts = 4; break; 2153 case X86::VBROADCASTSDZm: NumElts = 8; break; 2154 case X86::VPBROADCASTBrm: NumElts = 16; break; 2155 case X86::VPBROADCASTBYrm: NumElts = 32; break; 2156 case X86::VPBROADCASTBZ128m: NumElts = 16; break; 2157 case X86::VPBROADCASTBZ256m: NumElts = 32; break; 2158 case X86::VPBROADCASTBZm: NumElts = 64; break; 2159 case X86::VPBROADCASTDrm: NumElts = 4; break; 2160 case X86::VPBROADCASTDYrm: NumElts = 8; break; 2161 case X86::VPBROADCASTDZ128m: NumElts = 4; break; 2162 case X86::VPBROADCASTDZ256m: NumElts = 8; break; 2163 case X86::VPBROADCASTDZm: NumElts = 16; break; 2164 case X86::VPBROADCASTQrm: NumElts = 2; break; 2165 case X86::VPBROADCASTQYrm: NumElts = 4; break; 2166 case X86::VPBROADCASTQZ128m: NumElts = 2; break; 2167 case X86::VPBROADCASTQZ256m: NumElts = 4; break; 2168 case X86::VPBROADCASTQZm: NumElts = 8; break; 2169 case X86::VPBROADCASTWrm: NumElts = 8; break; 2170 case X86::VPBROADCASTWYrm: NumElts = 16; break; 2171 case X86::VPBROADCASTWZ128m: NumElts = 8; break; 2172 case X86::VPBROADCASTWZ256m: NumElts = 16; break; 2173 case X86::VPBROADCASTWZm: NumElts = 32; break; 2174 } 2175 2176 std::string Comment; 2177 raw_string_ostream CS(Comment); 2178 const MachineOperand &DstOp = MI->getOperand(0); 2179 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 2180 CS << "["; 2181 for (int i = 0; i != NumElts; ++i) { 2182 if (i != 0) 2183 CS << ","; 2184 printConstant(C, CS); 2185 } 2186 CS << "]"; 2187 OutStreamer->AddComment(CS.str(), !EnablePrintSchedInfo); 2188 } 2189 } 2190 2191 MCInst TmpInst; 2192 MCInstLowering.Lower(MI, TmpInst); 2193 if (MI->getAsmPrinterFlag(MachineInstr::NoSchedComment)) 2194 TmpInst.setFlags(TmpInst.getFlags() | X86::NO_SCHED_INFO); 2195 2196 // Stackmap shadows cannot include branch targets, so we can count the bytes 2197 // in a call towards the shadow, but must ensure that the no thread returns 2198 // in to the stackmap shadow. The only way to achieve this is if the call 2199 // is at the end of the shadow. 2200 if (MI->isCall()) { 2201 // Count then size of the call towards the shadow 2202 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get()); 2203 // Then flush the shadow so that we fill with nops before the call, not 2204 // after it. 2205 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 2206 // Then emit the call 2207 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo()); 2208 return; 2209 } 2210 2211 EmitAndCountInstruction(TmpInst); 2212 } 2213