1 //===- X86InstructionSelector.cpp -----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// X86.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/X86BaseInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86InstrInfo.h"
18 #include "X86RegisterBankInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
24 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25 #include "llvm/CodeGen/GlobalISel/Utils.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/TargetOpcodes.h"
35 #include "llvm/CodeGen/TargetRegisterInfo.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/InstrTypes.h"
38 #include "llvm/IR/IntrinsicsX86.h"
39 #include "llvm/Support/AtomicOrdering.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include <cassert>
47 #include <cstdint>
48 #include <tuple>
49 
50 #define DEBUG_TYPE "X86-isel"
51 
52 using namespace llvm;
53 
54 namespace {
55 
56 #define GET_GLOBALISEL_PREDICATE_BITSET
57 #include "X86GenGlobalISel.inc"
58 #undef GET_GLOBALISEL_PREDICATE_BITSET
59 
60 class X86InstructionSelector : public InstructionSelector {
61 public:
62   X86InstructionSelector(const X86TargetMachine &TM, const X86Subtarget &STI,
63                          const X86RegisterBankInfo &RBI);
64 
65   bool select(MachineInstr &I) override;
66   static const char *getName() { return DEBUG_TYPE; }
67 
68 private:
69   /// tblgen-erated 'select' implementation, used as the initial selector for
70   /// the patterns that don't require complex C++.
71   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
72 
73   // TODO: remove after supported by Tablegen-erated instruction selection.
74   unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
75                           Align Alignment) const;
76 
77   bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
78                          MachineFunction &MF) const;
79   bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
80                              MachineFunction &MF) const;
81   bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
82                          MachineFunction &MF) const;
83   bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
84                       MachineFunction &MF) const;
85   bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
86                              MachineFunction &MF) const;
87   bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
88                   MachineFunction &MF) const;
89   bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
90                     MachineFunction &MF) const;
91   bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
92                  MachineFunction &MF) const;
93   bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
94                   MachineFunction &MF) const;
95   bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
96                    MachineFunction &MF) const;
97   bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
98   bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
99                            MachineFunction &MF);
100   bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
101                          MachineFunction &MF);
102   bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
103                     MachineFunction &MF) const;
104   bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
105                      MachineFunction &MF) const;
106   bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
107                         MachineFunction &MF) const;
108   bool selectTurnIntoCOPY(MachineInstr &I, MachineRegisterInfo &MRI,
109                           const unsigned DstReg,
110                           const TargetRegisterClass *DstRC,
111                           const unsigned SrcReg,
112                           const TargetRegisterClass *SrcRC) const;
113   bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
114                      MachineFunction &MF) const;
115   bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
116   bool selectDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
117                     MachineFunction &MF) const;
118   bool selectIntrinsicWSideEffects(MachineInstr &I, MachineRegisterInfo &MRI,
119                                    MachineFunction &MF) const;
120 
121   // emit insert subreg instruction and insert it before MachineInstr &I
122   bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
123                         MachineRegisterInfo &MRI, MachineFunction &MF) const;
124   // emit extract subreg instruction and insert it before MachineInstr &I
125   bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
126                          MachineRegisterInfo &MRI, MachineFunction &MF) const;
127 
128   const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
129   const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
130                                          MachineRegisterInfo &MRI) const;
131 
132   const X86TargetMachine &TM;
133   const X86Subtarget &STI;
134   const X86InstrInfo &TII;
135   const X86RegisterInfo &TRI;
136   const X86RegisterBankInfo &RBI;
137 
138 #define GET_GLOBALISEL_PREDICATES_DECL
139 #include "X86GenGlobalISel.inc"
140 #undef GET_GLOBALISEL_PREDICATES_DECL
141 
142 #define GET_GLOBALISEL_TEMPORARIES_DECL
143 #include "X86GenGlobalISel.inc"
144 #undef GET_GLOBALISEL_TEMPORARIES_DECL
145 };
146 
147 } // end anonymous namespace
148 
149 #define GET_GLOBALISEL_IMPL
150 #include "X86GenGlobalISel.inc"
151 #undef GET_GLOBALISEL_IMPL
152 
153 X86InstructionSelector::X86InstructionSelector(const X86TargetMachine &TM,
154                                                const X86Subtarget &STI,
155                                                const X86RegisterBankInfo &RBI)
156     : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
157       TRI(*STI.getRegisterInfo()), RBI(RBI),
158 #define GET_GLOBALISEL_PREDICATES_INIT
159 #include "X86GenGlobalISel.inc"
160 #undef GET_GLOBALISEL_PREDICATES_INIT
161 #define GET_GLOBALISEL_TEMPORARIES_INIT
162 #include "X86GenGlobalISel.inc"
163 #undef GET_GLOBALISEL_TEMPORARIES_INIT
164 {
165 }
166 
167 // FIXME: This should be target-independent, inferred from the types declared
168 // for each class in the bank.
169 const TargetRegisterClass *
170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
171   if (RB.getID() == X86::GPRRegBankID) {
172     if (Ty.getSizeInBits() <= 8)
173       return &X86::GR8RegClass;
174     if (Ty.getSizeInBits() == 16)
175       return &X86::GR16RegClass;
176     if (Ty.getSizeInBits() == 32)
177       return &X86::GR32RegClass;
178     if (Ty.getSizeInBits() == 64)
179       return &X86::GR64RegClass;
180   }
181   if (RB.getID() == X86::VECRRegBankID) {
182     if (Ty.getSizeInBits() == 32)
183       return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
184     if (Ty.getSizeInBits() == 64)
185       return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
186     if (Ty.getSizeInBits() == 128)
187       return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass;
188     if (Ty.getSizeInBits() == 256)
189       return STI.hasAVX512() ? &X86::VR256XRegClass : &X86::VR256RegClass;
190     if (Ty.getSizeInBits() == 512)
191       return &X86::VR512RegClass;
192   }
193 
194   llvm_unreachable("Unknown RegBank!");
195 }
196 
197 const TargetRegisterClass *
198 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
199                                     MachineRegisterInfo &MRI) const {
200   const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
201   return getRegClass(Ty, RegBank);
202 }
203 
204 static unsigned getSubRegIndex(const TargetRegisterClass *RC) {
205   unsigned SubIdx = X86::NoSubRegister;
206   if (RC == &X86::GR32RegClass) {
207     SubIdx = X86::sub_32bit;
208   } else if (RC == &X86::GR16RegClass) {
209     SubIdx = X86::sub_16bit;
210   } else if (RC == &X86::GR8RegClass) {
211     SubIdx = X86::sub_8bit;
212   }
213 
214   return SubIdx;
215 }
216 
217 static const TargetRegisterClass *getRegClassFromGRPhysReg(unsigned Reg) {
218   assert(Register::isPhysicalRegister(Reg));
219   if (X86::GR64RegClass.contains(Reg))
220     return &X86::GR64RegClass;
221   if (X86::GR32RegClass.contains(Reg))
222     return &X86::GR32RegClass;
223   if (X86::GR16RegClass.contains(Reg))
224     return &X86::GR16RegClass;
225   if (X86::GR8RegClass.contains(Reg))
226     return &X86::GR8RegClass;
227 
228   llvm_unreachable("Unknown RegClass for PhysReg!");
229 }
230 
231 // Set X86 Opcode and constrain DestReg.
232 bool X86InstructionSelector::selectCopy(MachineInstr &I,
233                                         MachineRegisterInfo &MRI) const {
234   Register DstReg = I.getOperand(0).getReg();
235   const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
236   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
237 
238   Register SrcReg = I.getOperand(1).getReg();
239   const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
240   const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
241 
242   if (Register::isPhysicalRegister(DstReg)) {
243     assert(I.isCopy() && "Generic operators do not allow physical registers");
244 
245     if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID &&
246         DstRegBank.getID() == X86::GPRRegBankID) {
247 
248       const TargetRegisterClass *SrcRC =
249           getRegClass(MRI.getType(SrcReg), SrcRegBank);
250       const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg);
251 
252       if (SrcRC != DstRC) {
253         // This case can be generated by ABI lowering, performe anyext
254         Register ExtSrc = MRI.createVirtualRegister(DstRC);
255         BuildMI(*I.getParent(), I, I.getDebugLoc(),
256                 TII.get(TargetOpcode::SUBREG_TO_REG))
257             .addDef(ExtSrc)
258             .addImm(0)
259             .addReg(SrcReg)
260             .addImm(getSubRegIndex(SrcRC));
261 
262         I.getOperand(1).setReg(ExtSrc);
263       }
264     }
265 
266     return true;
267   }
268 
269   assert((!Register::isPhysicalRegister(SrcReg) || I.isCopy()) &&
270          "No phys reg on generic operators");
271   assert((DstSize == SrcSize ||
272           // Copies are a mean to setup initial types, the number of
273           // bits may not exactly match.
274           (Register::isPhysicalRegister(SrcReg) &&
275            DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
276          "Copy with different width?!");
277 
278   const TargetRegisterClass *DstRC =
279       getRegClass(MRI.getType(DstReg), DstRegBank);
280 
281   if (SrcRegBank.getID() == X86::GPRRegBankID &&
282       DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize &&
283       Register::isPhysicalRegister(SrcReg)) {
284     // Change the physical register to performe truncate.
285 
286     const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
287 
288     if (DstRC != SrcRC) {
289       I.getOperand(1).setSubReg(getSubRegIndex(DstRC));
290       I.getOperand(1).substPhysReg(SrcReg, TRI);
291     }
292   }
293 
294   // No need to constrain SrcReg. It will get constrained when
295   // we hit another of its use or its defs.
296   // Copies do not have constraints.
297   const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
298   if (!OldRC || !DstRC->hasSubClassEq(OldRC)) {
299     if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
300       LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
301                         << " operand\n");
302       return false;
303     }
304   }
305   I.setDesc(TII.get(X86::COPY));
306   return true;
307 }
308 
309 bool X86InstructionSelector::select(MachineInstr &I) {
310   assert(I.getParent() && "Instruction should be in a basic block!");
311   assert(I.getParent()->getParent() && "Instruction should be in a function!");
312 
313   MachineBasicBlock &MBB = *I.getParent();
314   MachineFunction &MF = *MBB.getParent();
315   MachineRegisterInfo &MRI = MF.getRegInfo();
316 
317   unsigned Opcode = I.getOpcode();
318   if (!isPreISelGenericOpcode(Opcode)) {
319     // Certain non-generic instructions also need some special handling.
320 
321     if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
322       return false;
323 
324     if (I.isCopy())
325       return selectCopy(I, MRI);
326 
327     return true;
328   }
329 
330   assert(I.getNumOperands() == I.getNumExplicitOperands() &&
331          "Generic instruction has unexpected implicit operands\n");
332 
333   if (selectImpl(I, *CoverageInfo))
334     return true;
335 
336   LLVM_DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs()));
337 
338   // TODO: This should be implemented by tblgen.
339   switch (I.getOpcode()) {
340   default:
341     return false;
342   case TargetOpcode::G_STORE:
343   case TargetOpcode::G_LOAD:
344     return selectLoadStoreOp(I, MRI, MF);
345   case TargetOpcode::G_PTR_ADD:
346   case TargetOpcode::G_FRAME_INDEX:
347     return selectFrameIndexOrGep(I, MRI, MF);
348   case TargetOpcode::G_GLOBAL_VALUE:
349     return selectGlobalValue(I, MRI, MF);
350   case TargetOpcode::G_CONSTANT:
351     return selectConstant(I, MRI, MF);
352   case TargetOpcode::G_FCONSTANT:
353     return materializeFP(I, MRI, MF);
354   case TargetOpcode::G_PTRTOINT:
355   case TargetOpcode::G_TRUNC:
356     return selectTruncOrPtrToInt(I, MRI, MF);
357   case TargetOpcode::G_INTTOPTR:
358     return selectCopy(I, MRI);
359   case TargetOpcode::G_ZEXT:
360     return selectZext(I, MRI, MF);
361   case TargetOpcode::G_ANYEXT:
362     return selectAnyext(I, MRI, MF);
363   case TargetOpcode::G_ICMP:
364     return selectCmp(I, MRI, MF);
365   case TargetOpcode::G_FCMP:
366     return selectFCmp(I, MRI, MF);
367   case TargetOpcode::G_UADDE:
368     return selectUadde(I, MRI, MF);
369   case TargetOpcode::G_UNMERGE_VALUES:
370     return selectUnmergeValues(I, MRI, MF);
371   case TargetOpcode::G_MERGE_VALUES:
372   case TargetOpcode::G_CONCAT_VECTORS:
373     return selectMergeValues(I, MRI, MF);
374   case TargetOpcode::G_EXTRACT:
375     return selectExtract(I, MRI, MF);
376   case TargetOpcode::G_INSERT:
377     return selectInsert(I, MRI, MF);
378   case TargetOpcode::G_BRCOND:
379     return selectCondBranch(I, MRI, MF);
380   case TargetOpcode::G_IMPLICIT_DEF:
381   case TargetOpcode::G_PHI:
382     return selectImplicitDefOrPHI(I, MRI);
383   case TargetOpcode::G_SDIV:
384   case TargetOpcode::G_UDIV:
385   case TargetOpcode::G_SREM:
386   case TargetOpcode::G_UREM:
387     return selectDivRem(I, MRI, MF);
388   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
389     return selectIntrinsicWSideEffects(I, MRI, MF);
390   }
391 
392   return false;
393 }
394 
395 unsigned X86InstructionSelector::getLoadStoreOp(const LLT &Ty,
396                                                 const RegisterBank &RB,
397                                                 unsigned Opc,
398                                                 Align Alignment) const {
399   bool Isload = (Opc == TargetOpcode::G_LOAD);
400   bool HasAVX = STI.hasAVX();
401   bool HasAVX512 = STI.hasAVX512();
402   bool HasVLX = STI.hasVLX();
403 
404   if (Ty == LLT::scalar(8)) {
405     if (X86::GPRRegBankID == RB.getID())
406       return Isload ? X86::MOV8rm : X86::MOV8mr;
407   } else if (Ty == LLT::scalar(16)) {
408     if (X86::GPRRegBankID == RB.getID())
409       return Isload ? X86::MOV16rm : X86::MOV16mr;
410   } else if (Ty == LLT::scalar(32) || Ty == LLT::pointer(0, 32)) {
411     if (X86::GPRRegBankID == RB.getID())
412       return Isload ? X86::MOV32rm : X86::MOV32mr;
413     if (X86::VECRRegBankID == RB.getID())
414       return Isload ? (HasAVX512 ? X86::VMOVSSZrm_alt :
415                        HasAVX    ? X86::VMOVSSrm_alt :
416                                    X86::MOVSSrm_alt)
417                     : (HasAVX512 ? X86::VMOVSSZmr :
418                        HasAVX    ? X86::VMOVSSmr :
419                                    X86::MOVSSmr);
420   } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
421     if (X86::GPRRegBankID == RB.getID())
422       return Isload ? X86::MOV64rm : X86::MOV64mr;
423     if (X86::VECRRegBankID == RB.getID())
424       return Isload ? (HasAVX512 ? X86::VMOVSDZrm_alt :
425                        HasAVX    ? X86::VMOVSDrm_alt :
426                                    X86::MOVSDrm_alt)
427                     : (HasAVX512 ? X86::VMOVSDZmr :
428                        HasAVX    ? X86::VMOVSDmr :
429                                    X86::MOVSDmr);
430   } else if (Ty.isVector() && Ty.getSizeInBits() == 128) {
431     if (Alignment >= Align(16))
432       return Isload ? (HasVLX ? X86::VMOVAPSZ128rm
433                               : HasAVX512
434                                     ? X86::VMOVAPSZ128rm_NOVLX
435                                     : HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
436                     : (HasVLX ? X86::VMOVAPSZ128mr
437                               : HasAVX512
438                                     ? X86::VMOVAPSZ128mr_NOVLX
439                                     : HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
440     else
441       return Isload ? (HasVLX ? X86::VMOVUPSZ128rm
442                               : HasAVX512
443                                     ? X86::VMOVUPSZ128rm_NOVLX
444                                     : HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
445                     : (HasVLX ? X86::VMOVUPSZ128mr
446                               : HasAVX512
447                                     ? X86::VMOVUPSZ128mr_NOVLX
448                                     : HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
449   } else if (Ty.isVector() && Ty.getSizeInBits() == 256) {
450     if (Alignment >= Align(32))
451       return Isload ? (HasVLX ? X86::VMOVAPSZ256rm
452                               : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
453                                           : X86::VMOVAPSYrm)
454                     : (HasVLX ? X86::VMOVAPSZ256mr
455                               : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
456                                           : X86::VMOVAPSYmr);
457     else
458       return Isload ? (HasVLX ? X86::VMOVUPSZ256rm
459                               : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
460                                           : X86::VMOVUPSYrm)
461                     : (HasVLX ? X86::VMOVUPSZ256mr
462                               : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
463                                           : X86::VMOVUPSYmr);
464   } else if (Ty.isVector() && Ty.getSizeInBits() == 512) {
465     if (Alignment >= Align(64))
466       return Isload ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
467     else
468       return Isload ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
469   }
470   return Opc;
471 }
472 
473 // Fill in an address from the given instruction.
474 static void X86SelectAddress(const MachineInstr &I,
475                              const MachineRegisterInfo &MRI,
476                              X86AddressMode &AM) {
477   assert(I.getOperand(0).isReg() && "unsupported opperand.");
478   assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
479          "unsupported type.");
480 
481   if (I.getOpcode() == TargetOpcode::G_PTR_ADD) {
482     if (auto COff = getConstantVRegVal(I.getOperand(2).getReg(), MRI)) {
483       int64_t Imm = *COff;
484       if (isInt<32>(Imm)) { // Check for displacement overflow.
485         AM.Disp = static_cast<int32_t>(Imm);
486         AM.Base.Reg = I.getOperand(1).getReg();
487         return;
488       }
489     }
490   } else if (I.getOpcode() == TargetOpcode::G_FRAME_INDEX) {
491     AM.Base.FrameIndex = I.getOperand(1).getIndex();
492     AM.BaseType = X86AddressMode::FrameIndexBase;
493     return;
494   }
495 
496   // Default behavior.
497   AM.Base.Reg = I.getOperand(0).getReg();
498 }
499 
500 bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
501                                                MachineRegisterInfo &MRI,
502                                                MachineFunction &MF) const {
503   unsigned Opc = I.getOpcode();
504 
505   assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) &&
506          "unexpected instruction");
507 
508   const Register DefReg = I.getOperand(0).getReg();
509   LLT Ty = MRI.getType(DefReg);
510   const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
511 
512   assert(I.hasOneMemOperand());
513   auto &MemOp = **I.memoperands_begin();
514   if (MemOp.isAtomic()) {
515     // Note: for unordered operations, we rely on the fact the appropriate MMO
516     // is already on the instruction we're mutating, and thus we don't need to
517     // make any changes.  So long as we select an opcode which is capable of
518     // loading or storing the appropriate size atomically, the rest of the
519     // backend is required to respect the MMO state.
520     if (!MemOp.isUnordered()) {
521       LLVM_DEBUG(dbgs() << "Atomic ordering not supported yet\n");
522       return false;
523     }
524     if (MemOp.getAlign() < Ty.getSizeInBits() / 8) {
525       LLVM_DEBUG(dbgs() << "Unaligned atomics not supported yet\n");
526       return false;
527     }
528   }
529 
530   unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign());
531   if (NewOpc == Opc)
532     return false;
533 
534   X86AddressMode AM;
535   X86SelectAddress(*MRI.getVRegDef(I.getOperand(1).getReg()), MRI, AM);
536 
537   I.setDesc(TII.get(NewOpc));
538   MachineInstrBuilder MIB(MF, I);
539   if (Opc == TargetOpcode::G_LOAD) {
540     I.RemoveOperand(1);
541     addFullAddress(MIB, AM);
542   } else {
543     // G_STORE (VAL, Addr), X86Store instruction (Addr, VAL)
544     I.RemoveOperand(1);
545     I.RemoveOperand(0);
546     addFullAddress(MIB, AM).addUse(DefReg);
547   }
548   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
549 }
550 
551 static unsigned getLeaOP(LLT Ty, const X86Subtarget &STI) {
552   if (Ty == LLT::pointer(0, 64))
553     return X86::LEA64r;
554   else if (Ty == LLT::pointer(0, 32))
555     return STI.isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r;
556   else
557     llvm_unreachable("Can't get LEA opcode. Unsupported type.");
558 }
559 
560 bool X86InstructionSelector::selectFrameIndexOrGep(MachineInstr &I,
561                                                    MachineRegisterInfo &MRI,
562                                                    MachineFunction &MF) const {
563   unsigned Opc = I.getOpcode();
564 
565   assert((Opc == TargetOpcode::G_FRAME_INDEX || Opc == TargetOpcode::G_PTR_ADD) &&
566          "unexpected instruction");
567 
568   const Register DefReg = I.getOperand(0).getReg();
569   LLT Ty = MRI.getType(DefReg);
570 
571   // Use LEA to calculate frame index and GEP
572   unsigned NewOpc = getLeaOP(Ty, STI);
573   I.setDesc(TII.get(NewOpc));
574   MachineInstrBuilder MIB(MF, I);
575 
576   if (Opc == TargetOpcode::G_FRAME_INDEX) {
577     addOffset(MIB, 0);
578   } else {
579     MachineOperand &InxOp = I.getOperand(2);
580     I.addOperand(InxOp);        // set IndexReg
581     InxOp.ChangeToImmediate(1); // set Scale
582     MIB.addImm(0).addReg(0);
583   }
584 
585   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
586 }
587 
588 bool X86InstructionSelector::selectGlobalValue(MachineInstr &I,
589                                                MachineRegisterInfo &MRI,
590                                                MachineFunction &MF) const {
591   assert((I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE) &&
592          "unexpected instruction");
593 
594   auto GV = I.getOperand(1).getGlobal();
595   if (GV->isThreadLocal()) {
596     return false; // TODO: we don't support TLS yet.
597   }
598 
599   // Can't handle alternate code models yet.
600   if (TM.getCodeModel() != CodeModel::Small)
601     return false;
602 
603   X86AddressMode AM;
604   AM.GV = GV;
605   AM.GVOpFlags = STI.classifyGlobalReference(GV);
606 
607   // TODO: The ABI requires an extra load. not supported yet.
608   if (isGlobalStubReference(AM.GVOpFlags))
609     return false;
610 
611   // TODO: This reference is relative to the pic base. not supported yet.
612   if (isGlobalRelativeToPICBase(AM.GVOpFlags))
613     return false;
614 
615   if (STI.isPICStyleRIPRel()) {
616     // Use rip-relative addressing.
617     assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
618     AM.Base.Reg = X86::RIP;
619   }
620 
621   const Register DefReg = I.getOperand(0).getReg();
622   LLT Ty = MRI.getType(DefReg);
623   unsigned NewOpc = getLeaOP(Ty, STI);
624 
625   I.setDesc(TII.get(NewOpc));
626   MachineInstrBuilder MIB(MF, I);
627 
628   I.RemoveOperand(1);
629   addFullAddress(MIB, AM);
630 
631   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
632 }
633 
634 bool X86InstructionSelector::selectConstant(MachineInstr &I,
635                                             MachineRegisterInfo &MRI,
636                                             MachineFunction &MF) const {
637   assert((I.getOpcode() == TargetOpcode::G_CONSTANT) &&
638          "unexpected instruction");
639 
640   const Register DefReg = I.getOperand(0).getReg();
641   LLT Ty = MRI.getType(DefReg);
642 
643   if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
644     return false;
645 
646   uint64_t Val = 0;
647   if (I.getOperand(1).isCImm()) {
648     Val = I.getOperand(1).getCImm()->getZExtValue();
649     I.getOperand(1).ChangeToImmediate(Val);
650   } else if (I.getOperand(1).isImm()) {
651     Val = I.getOperand(1).getImm();
652   } else
653     llvm_unreachable("Unsupported operand type.");
654 
655   unsigned NewOpc;
656   switch (Ty.getSizeInBits()) {
657   case 8:
658     NewOpc = X86::MOV8ri;
659     break;
660   case 16:
661     NewOpc = X86::MOV16ri;
662     break;
663   case 32:
664     NewOpc = X86::MOV32ri;
665     break;
666   case 64:
667     // TODO: in case isUInt<32>(Val), X86::MOV32ri can be used
668     if (isInt<32>(Val))
669       NewOpc = X86::MOV64ri32;
670     else
671       NewOpc = X86::MOV64ri;
672     break;
673   default:
674     llvm_unreachable("Can't select G_CONSTANT, unsupported type.");
675   }
676 
677   I.setDesc(TII.get(NewOpc));
678   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
679 }
680 
681 // Helper function for selectTruncOrPtrToInt and selectAnyext.
682 // Returns true if DstRC lives on a floating register class and
683 // SrcRC lives on a 128-bit vector class.
684 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC,
685                             const TargetRegisterClass *SrcRC) {
686   return (DstRC == &X86::FR32RegClass || DstRC == &X86::FR32XRegClass ||
687           DstRC == &X86::FR64RegClass || DstRC == &X86::FR64XRegClass) &&
688          (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass);
689 }
690 
691 bool X86InstructionSelector::selectTurnIntoCOPY(
692     MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
693     const TargetRegisterClass *DstRC, const unsigned SrcReg,
694     const TargetRegisterClass *SrcRC) const {
695 
696   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
697       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
698     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
699                       << " operand\n");
700     return false;
701   }
702   I.setDesc(TII.get(X86::COPY));
703   return true;
704 }
705 
706 bool X86InstructionSelector::selectTruncOrPtrToInt(MachineInstr &I,
707                                                    MachineRegisterInfo &MRI,
708                                                    MachineFunction &MF) const {
709   assert((I.getOpcode() == TargetOpcode::G_TRUNC ||
710           I.getOpcode() == TargetOpcode::G_PTRTOINT) &&
711          "unexpected instruction");
712 
713   const Register DstReg = I.getOperand(0).getReg();
714   const Register SrcReg = I.getOperand(1).getReg();
715 
716   const LLT DstTy = MRI.getType(DstReg);
717   const LLT SrcTy = MRI.getType(SrcReg);
718 
719   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
720   const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
721 
722   if (DstRB.getID() != SrcRB.getID()) {
723     LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode())
724                       << " input/output on different banks\n");
725     return false;
726   }
727 
728   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
729   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
730 
731   if (!DstRC || !SrcRC)
732     return false;
733 
734   // If that's truncation of the value that lives on the vector class and goes
735   // into the floating class, just replace it with copy, as we are able to
736   // select it as a regular move.
737   if (canTurnIntoCOPY(DstRC, SrcRC))
738     return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
739 
740   if (DstRB.getID() != X86::GPRRegBankID)
741     return false;
742 
743   unsigned SubIdx;
744   if (DstRC == SrcRC) {
745     // Nothing to be done
746     SubIdx = X86::NoSubRegister;
747   } else if (DstRC == &X86::GR32RegClass) {
748     SubIdx = X86::sub_32bit;
749   } else if (DstRC == &X86::GR16RegClass) {
750     SubIdx = X86::sub_16bit;
751   } else if (DstRC == &X86::GR8RegClass) {
752     SubIdx = X86::sub_8bit;
753   } else {
754     return false;
755   }
756 
757   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
758 
759   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
760       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
761     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
762                       << "\n");
763     return false;
764   }
765 
766   I.getOperand(1).setSubReg(SubIdx);
767 
768   I.setDesc(TII.get(X86::COPY));
769   return true;
770 }
771 
772 bool X86InstructionSelector::selectZext(MachineInstr &I,
773                                         MachineRegisterInfo &MRI,
774                                         MachineFunction &MF) const {
775   assert((I.getOpcode() == TargetOpcode::G_ZEXT) && "unexpected instruction");
776 
777   const Register DstReg = I.getOperand(0).getReg();
778   const Register SrcReg = I.getOperand(1).getReg();
779 
780   const LLT DstTy = MRI.getType(DstReg);
781   const LLT SrcTy = MRI.getType(SrcReg);
782 
783   assert(!(SrcTy == LLT::scalar(8) && DstTy == LLT::scalar(16)) &&
784          "8=>16 Zext is handled by tablegen");
785   assert(!(SrcTy == LLT::scalar(8) && DstTy == LLT::scalar(32)) &&
786          "8=>32 Zext is handled by tablegen");
787   assert(!(SrcTy == LLT::scalar(16) && DstTy == LLT::scalar(32)) &&
788          "16=>32 Zext is handled by tablegen");
789   assert(!(SrcTy == LLT::scalar(8) && DstTy == LLT::scalar(64)) &&
790          "8=>64 Zext is handled by tablegen");
791   assert(!(SrcTy == LLT::scalar(16) && DstTy == LLT::scalar(64)) &&
792          "16=>64 Zext is handled by tablegen");
793   assert(!(SrcTy == LLT::scalar(32) && DstTy == LLT::scalar(64)) &&
794          "32=>64 Zext is handled by tablegen");
795 
796   if (SrcTy != LLT::scalar(1))
797     return false;
798 
799   unsigned AndOpc;
800   if (DstTy == LLT::scalar(8))
801     AndOpc = X86::AND8ri;
802   else if (DstTy == LLT::scalar(16))
803     AndOpc = X86::AND16ri8;
804   else if (DstTy == LLT::scalar(32))
805     AndOpc = X86::AND32ri8;
806   else if (DstTy == LLT::scalar(64))
807     AndOpc = X86::AND64ri8;
808   else
809     return false;
810 
811   unsigned DefReg = SrcReg;
812   if (DstTy != LLT::scalar(8)) {
813     DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
814     BuildMI(*I.getParent(), I, I.getDebugLoc(),
815             TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
816         .addImm(0)
817         .addReg(SrcReg)
818         .addImm(X86::sub_8bit);
819   }
820 
821   MachineInstr &AndInst =
822       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
823            .addReg(DefReg)
824            .addImm(1);
825 
826   constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI);
827 
828   I.eraseFromParent();
829   return true;
830 }
831 
832 bool X86InstructionSelector::selectAnyext(MachineInstr &I,
833                                           MachineRegisterInfo &MRI,
834                                           MachineFunction &MF) const {
835   assert((I.getOpcode() == TargetOpcode::G_ANYEXT) && "unexpected instruction");
836 
837   const Register DstReg = I.getOperand(0).getReg();
838   const Register SrcReg = I.getOperand(1).getReg();
839 
840   const LLT DstTy = MRI.getType(DstReg);
841   const LLT SrcTy = MRI.getType(SrcReg);
842 
843   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
844   const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
845 
846   assert(DstRB.getID() == SrcRB.getID() &&
847          "G_ANYEXT input/output on different banks\n");
848 
849   assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
850          "G_ANYEXT incorrect operand size");
851 
852   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
853   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
854 
855   // If that's ANY_EXT of the value that lives on the floating class and goes
856   // into the vector class, just replace it with copy, as we are able to select
857   // it as a regular move.
858   if (canTurnIntoCOPY(SrcRC, DstRC))
859     return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
860 
861   if (DstRB.getID() != X86::GPRRegBankID)
862     return false;
863 
864   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
865       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
866     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
867                       << " operand\n");
868     return false;
869   }
870 
871   if (SrcRC == DstRC) {
872     I.setDesc(TII.get(X86::COPY));
873     return true;
874   }
875 
876   BuildMI(*I.getParent(), I, I.getDebugLoc(),
877           TII.get(TargetOpcode::SUBREG_TO_REG))
878       .addDef(DstReg)
879       .addImm(0)
880       .addReg(SrcReg)
881       .addImm(getSubRegIndex(SrcRC));
882 
883   I.eraseFromParent();
884   return true;
885 }
886 
887 bool X86InstructionSelector::selectCmp(MachineInstr &I,
888                                        MachineRegisterInfo &MRI,
889                                        MachineFunction &MF) const {
890   assert((I.getOpcode() == TargetOpcode::G_ICMP) && "unexpected instruction");
891 
892   X86::CondCode CC;
893   bool SwapArgs;
894   std::tie(CC, SwapArgs) = X86::getX86ConditionCode(
895       (CmpInst::Predicate)I.getOperand(1).getPredicate());
896 
897   Register LHS = I.getOperand(2).getReg();
898   Register RHS = I.getOperand(3).getReg();
899 
900   if (SwapArgs)
901     std::swap(LHS, RHS);
902 
903   unsigned OpCmp;
904   LLT Ty = MRI.getType(LHS);
905 
906   switch (Ty.getSizeInBits()) {
907   default:
908     return false;
909   case 8:
910     OpCmp = X86::CMP8rr;
911     break;
912   case 16:
913     OpCmp = X86::CMP16rr;
914     break;
915   case 32:
916     OpCmp = X86::CMP32rr;
917     break;
918   case 64:
919     OpCmp = X86::CMP64rr;
920     break;
921   }
922 
923   MachineInstr &CmpInst =
924       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
925            .addReg(LHS)
926            .addReg(RHS);
927 
928   MachineInstr &SetInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
929                                    TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
930 
931   constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
932   constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
933 
934   I.eraseFromParent();
935   return true;
936 }
937 
938 bool X86InstructionSelector::selectFCmp(MachineInstr &I,
939                                         MachineRegisterInfo &MRI,
940                                         MachineFunction &MF) const {
941   assert((I.getOpcode() == TargetOpcode::G_FCMP) && "unexpected instruction");
942 
943   Register LhsReg = I.getOperand(2).getReg();
944   Register RhsReg = I.getOperand(3).getReg();
945   CmpInst::Predicate Predicate =
946       (CmpInst::Predicate)I.getOperand(1).getPredicate();
947 
948   // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
949   static const uint16_t SETFOpcTable[2][3] = {
950       {X86::COND_E, X86::COND_NP, X86::AND8rr},
951       {X86::COND_NE, X86::COND_P, X86::OR8rr}};
952   const uint16_t *SETFOpc = nullptr;
953   switch (Predicate) {
954   default:
955     break;
956   case CmpInst::FCMP_OEQ:
957     SETFOpc = &SETFOpcTable[0][0];
958     break;
959   case CmpInst::FCMP_UNE:
960     SETFOpc = &SETFOpcTable[1][0];
961     break;
962   }
963 
964   // Compute the opcode for the CMP instruction.
965   unsigned OpCmp;
966   LLT Ty = MRI.getType(LhsReg);
967   switch (Ty.getSizeInBits()) {
968   default:
969     return false;
970   case 32:
971     OpCmp = X86::UCOMISSrr;
972     break;
973   case 64:
974     OpCmp = X86::UCOMISDrr;
975     break;
976   }
977 
978   Register ResultReg = I.getOperand(0).getReg();
979   RBI.constrainGenericRegister(
980       ResultReg,
981       *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
982   if (SETFOpc) {
983     MachineInstr &CmpInst =
984         *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
985              .addReg(LhsReg)
986              .addReg(RhsReg);
987 
988     Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
989     Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
990     MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
991                                   TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]);
992     MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
993                                   TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]);
994     MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
995                                   TII.get(SETFOpc[2]), ResultReg)
996                               .addReg(FlagReg1)
997                               .addReg(FlagReg2);
998     constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
999     constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
1000     constrainSelectedInstRegOperands(Set2, TII, TRI, RBI);
1001     constrainSelectedInstRegOperands(Set3, TII, TRI, RBI);
1002 
1003     I.eraseFromParent();
1004     return true;
1005   }
1006 
1007   X86::CondCode CC;
1008   bool SwapArgs;
1009   std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate);
1010   assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1011 
1012   if (SwapArgs)
1013     std::swap(LhsReg, RhsReg);
1014 
1015   // Emit a compare of LHS/RHS.
1016   MachineInstr &CmpInst =
1017       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1018            .addReg(LhsReg)
1019            .addReg(RhsReg);
1020 
1021   MachineInstr &Set =
1022       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
1023   constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1024   constrainSelectedInstRegOperands(Set, TII, TRI, RBI);
1025   I.eraseFromParent();
1026   return true;
1027 }
1028 
1029 bool X86InstructionSelector::selectUadde(MachineInstr &I,
1030                                          MachineRegisterInfo &MRI,
1031                                          MachineFunction &MF) const {
1032   assert((I.getOpcode() == TargetOpcode::G_UADDE) && "unexpected instruction");
1033 
1034   const Register DstReg = I.getOperand(0).getReg();
1035   const Register CarryOutReg = I.getOperand(1).getReg();
1036   const Register Op0Reg = I.getOperand(2).getReg();
1037   const Register Op1Reg = I.getOperand(3).getReg();
1038   Register CarryInReg = I.getOperand(4).getReg();
1039 
1040   const LLT DstTy = MRI.getType(DstReg);
1041 
1042   if (DstTy != LLT::scalar(32))
1043     return false;
1044 
1045   // find CarryIn def instruction.
1046   MachineInstr *Def = MRI.getVRegDef(CarryInReg);
1047   while (Def->getOpcode() == TargetOpcode::G_TRUNC) {
1048     CarryInReg = Def->getOperand(1).getReg();
1049     Def = MRI.getVRegDef(CarryInReg);
1050   }
1051 
1052   unsigned Opcode;
1053   if (Def->getOpcode() == TargetOpcode::G_UADDE) {
1054     // carry set by prev ADD.
1055 
1056     BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS)
1057         .addReg(CarryInReg);
1058 
1059     if (!RBI.constrainGenericRegister(CarryInReg, X86::GR32RegClass, MRI))
1060       return false;
1061 
1062     Opcode = X86::ADC32rr;
1063   } else if (auto val = getConstantVRegVal(CarryInReg, MRI)) {
1064     // carry is constant, support only 0.
1065     if (*val != 0)
1066       return false;
1067 
1068     Opcode = X86::ADD32rr;
1069   } else
1070     return false;
1071 
1072   MachineInstr &AddInst =
1073       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
1074            .addReg(Op0Reg)
1075            .addReg(Op1Reg);
1076 
1077   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1078       .addReg(X86::EFLAGS);
1079 
1080   if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) ||
1081       !RBI.constrainGenericRegister(CarryOutReg, X86::GR32RegClass, MRI))
1082     return false;
1083 
1084   I.eraseFromParent();
1085   return true;
1086 }
1087 
1088 bool X86InstructionSelector::selectExtract(MachineInstr &I,
1089                                            MachineRegisterInfo &MRI,
1090                                            MachineFunction &MF) const {
1091   assert((I.getOpcode() == TargetOpcode::G_EXTRACT) &&
1092          "unexpected instruction");
1093 
1094   const Register DstReg = I.getOperand(0).getReg();
1095   const Register SrcReg = I.getOperand(1).getReg();
1096   int64_t Index = I.getOperand(2).getImm();
1097 
1098   const LLT DstTy = MRI.getType(DstReg);
1099   const LLT SrcTy = MRI.getType(SrcReg);
1100 
1101   // Meanwile handle vector type only.
1102   if (!DstTy.isVector())
1103     return false;
1104 
1105   if (Index % DstTy.getSizeInBits() != 0)
1106     return false; // Not extract subvector.
1107 
1108   if (Index == 0) {
1109     // Replace by extract subreg copy.
1110     if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
1111       return false;
1112 
1113     I.eraseFromParent();
1114     return true;
1115   }
1116 
1117   bool HasAVX = STI.hasAVX();
1118   bool HasAVX512 = STI.hasAVX512();
1119   bool HasVLX = STI.hasVLX();
1120 
1121   if (SrcTy.getSizeInBits() == 256 && DstTy.getSizeInBits() == 128) {
1122     if (HasVLX)
1123       I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
1124     else if (HasAVX)
1125       I.setDesc(TII.get(X86::VEXTRACTF128rr));
1126     else
1127       return false;
1128   } else if (SrcTy.getSizeInBits() == 512 && HasAVX512) {
1129     if (DstTy.getSizeInBits() == 128)
1130       I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
1131     else if (DstTy.getSizeInBits() == 256)
1132       I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
1133     else
1134       return false;
1135   } else
1136     return false;
1137 
1138   // Convert to X86 VEXTRACT immediate.
1139   Index = Index / DstTy.getSizeInBits();
1140   I.getOperand(2).setImm(Index);
1141 
1142   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1143 }
1144 
1145 bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
1146                                                MachineInstr &I,
1147                                                MachineRegisterInfo &MRI,
1148                                                MachineFunction &MF) const {
1149   const LLT DstTy = MRI.getType(DstReg);
1150   const LLT SrcTy = MRI.getType(SrcReg);
1151   unsigned SubIdx = X86::NoSubRegister;
1152 
1153   if (!DstTy.isVector() || !SrcTy.isVector())
1154     return false;
1155 
1156   assert(SrcTy.getSizeInBits() > DstTy.getSizeInBits() &&
1157          "Incorrect Src/Dst register size");
1158 
1159   if (DstTy.getSizeInBits() == 128)
1160     SubIdx = X86::sub_xmm;
1161   else if (DstTy.getSizeInBits() == 256)
1162     SubIdx = X86::sub_ymm;
1163   else
1164     return false;
1165 
1166   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1167   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1168 
1169   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
1170 
1171   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1172       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1173     LLVM_DEBUG(dbgs() << "Failed to constrain EXTRACT_SUBREG\n");
1174     return false;
1175   }
1176 
1177   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1178       .addReg(SrcReg, 0, SubIdx);
1179 
1180   return true;
1181 }
1182 
1183 bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
1184                                               MachineInstr &I,
1185                                               MachineRegisterInfo &MRI,
1186                                               MachineFunction &MF) const {
1187   const LLT DstTy = MRI.getType(DstReg);
1188   const LLT SrcTy = MRI.getType(SrcReg);
1189   unsigned SubIdx = X86::NoSubRegister;
1190 
1191   // TODO: support scalar types
1192   if (!DstTy.isVector() || !SrcTy.isVector())
1193     return false;
1194 
1195   assert(SrcTy.getSizeInBits() < DstTy.getSizeInBits() &&
1196          "Incorrect Src/Dst register size");
1197 
1198   if (SrcTy.getSizeInBits() == 128)
1199     SubIdx = X86::sub_xmm;
1200   else if (SrcTy.getSizeInBits() == 256)
1201     SubIdx = X86::sub_ymm;
1202   else
1203     return false;
1204 
1205   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1206   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1207 
1208   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1209       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1210     LLVM_DEBUG(dbgs() << "Failed to constrain INSERT_SUBREG\n");
1211     return false;
1212   }
1213 
1214   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
1215       .addReg(DstReg, RegState::DefineNoRead, SubIdx)
1216       .addReg(SrcReg);
1217 
1218   return true;
1219 }
1220 
1221 bool X86InstructionSelector::selectInsert(MachineInstr &I,
1222                                           MachineRegisterInfo &MRI,
1223                                           MachineFunction &MF) const {
1224   assert((I.getOpcode() == TargetOpcode::G_INSERT) && "unexpected instruction");
1225 
1226   const Register DstReg = I.getOperand(0).getReg();
1227   const Register SrcReg = I.getOperand(1).getReg();
1228   const Register InsertReg = I.getOperand(2).getReg();
1229   int64_t Index = I.getOperand(3).getImm();
1230 
1231   const LLT DstTy = MRI.getType(DstReg);
1232   const LLT InsertRegTy = MRI.getType(InsertReg);
1233 
1234   // Meanwile handle vector type only.
1235   if (!DstTy.isVector())
1236     return false;
1237 
1238   if (Index % InsertRegTy.getSizeInBits() != 0)
1239     return false; // Not insert subvector.
1240 
1241   if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
1242     // Replace by subreg copy.
1243     if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF))
1244       return false;
1245 
1246     I.eraseFromParent();
1247     return true;
1248   }
1249 
1250   bool HasAVX = STI.hasAVX();
1251   bool HasAVX512 = STI.hasAVX512();
1252   bool HasVLX = STI.hasVLX();
1253 
1254   if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) {
1255     if (HasVLX)
1256       I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
1257     else if (HasAVX)
1258       I.setDesc(TII.get(X86::VINSERTF128rr));
1259     else
1260       return false;
1261   } else if (DstTy.getSizeInBits() == 512 && HasAVX512) {
1262     if (InsertRegTy.getSizeInBits() == 128)
1263       I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
1264     else if (InsertRegTy.getSizeInBits() == 256)
1265       I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
1266     else
1267       return false;
1268   } else
1269     return false;
1270 
1271   // Convert to X86 VINSERT immediate.
1272   Index = Index / InsertRegTy.getSizeInBits();
1273 
1274   I.getOperand(3).setImm(Index);
1275 
1276   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1277 }
1278 
1279 bool X86InstructionSelector::selectUnmergeValues(
1280     MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1281   assert((I.getOpcode() == TargetOpcode::G_UNMERGE_VALUES) &&
1282          "unexpected instruction");
1283 
1284   // Split to extracts.
1285   unsigned NumDefs = I.getNumOperands() - 1;
1286   Register SrcReg = I.getOperand(NumDefs).getReg();
1287   unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
1288 
1289   for (unsigned Idx = 0; Idx < NumDefs; ++Idx) {
1290     MachineInstr &ExtrInst =
1291         *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1292                  TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg())
1293              .addReg(SrcReg)
1294              .addImm(Idx * DefSize);
1295 
1296     if (!select(ExtrInst))
1297       return false;
1298   }
1299 
1300   I.eraseFromParent();
1301   return true;
1302 }
1303 
1304 bool X86InstructionSelector::selectMergeValues(
1305     MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1306   assert((I.getOpcode() == TargetOpcode::G_MERGE_VALUES ||
1307           I.getOpcode() == TargetOpcode::G_CONCAT_VECTORS) &&
1308          "unexpected instruction");
1309 
1310   // Split to inserts.
1311   Register DstReg = I.getOperand(0).getReg();
1312   Register SrcReg0 = I.getOperand(1).getReg();
1313 
1314   const LLT DstTy = MRI.getType(DstReg);
1315   const LLT SrcTy = MRI.getType(SrcReg0);
1316   unsigned SrcSize = SrcTy.getSizeInBits();
1317 
1318   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1319 
1320   // For the first src use insertSubReg.
1321   Register DefReg = MRI.createGenericVirtualRegister(DstTy);
1322   MRI.setRegBank(DefReg, RegBank);
1323   if (!emitInsertSubreg(DefReg, I.getOperand(1).getReg(), I, MRI, MF))
1324     return false;
1325 
1326   for (unsigned Idx = 2; Idx < I.getNumOperands(); ++Idx) {
1327     Register Tmp = MRI.createGenericVirtualRegister(DstTy);
1328     MRI.setRegBank(Tmp, RegBank);
1329 
1330     MachineInstr &InsertInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1331                                         TII.get(TargetOpcode::G_INSERT), Tmp)
1332                                     .addReg(DefReg)
1333                                     .addReg(I.getOperand(Idx).getReg())
1334                                     .addImm((Idx - 1) * SrcSize);
1335 
1336     DefReg = Tmp;
1337 
1338     if (!select(InsertInst))
1339       return false;
1340   }
1341 
1342   MachineInstr &CopyInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1343                                     TII.get(TargetOpcode::COPY), DstReg)
1344                                 .addReg(DefReg);
1345 
1346   if (!select(CopyInst))
1347     return false;
1348 
1349   I.eraseFromParent();
1350   return true;
1351 }
1352 
1353 bool X86InstructionSelector::selectCondBranch(MachineInstr &I,
1354                                               MachineRegisterInfo &MRI,
1355                                               MachineFunction &MF) const {
1356   assert((I.getOpcode() == TargetOpcode::G_BRCOND) && "unexpected instruction");
1357 
1358   const Register CondReg = I.getOperand(0).getReg();
1359   MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
1360 
1361   MachineInstr &TestInst =
1362       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
1363            .addReg(CondReg)
1364            .addImm(1);
1365   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
1366       .addMBB(DestMBB).addImm(X86::COND_NE);
1367 
1368   constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
1369 
1370   I.eraseFromParent();
1371   return true;
1372 }
1373 
1374 bool X86InstructionSelector::materializeFP(MachineInstr &I,
1375                                            MachineRegisterInfo &MRI,
1376                                            MachineFunction &MF) const {
1377   assert((I.getOpcode() == TargetOpcode::G_FCONSTANT) &&
1378          "unexpected instruction");
1379 
1380   // Can't handle alternate code models yet.
1381   CodeModel::Model CM = TM.getCodeModel();
1382   if (CM != CodeModel::Small && CM != CodeModel::Large)
1383     return false;
1384 
1385   const Register DstReg = I.getOperand(0).getReg();
1386   const LLT DstTy = MRI.getType(DstReg);
1387   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1388   Align Alignment = Align(DstTy.getSizeInBytes());
1389   const DebugLoc &DbgLoc = I.getDebugLoc();
1390 
1391   unsigned Opc =
1392       getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Alignment);
1393 
1394   // Create the load from the constant pool.
1395   const ConstantFP *CFP = I.getOperand(1).getFPImm();
1396   unsigned CPI = MF.getConstantPool()->getConstantPoolIndex(CFP, Alignment);
1397   MachineInstr *LoadInst = nullptr;
1398   unsigned char OpFlag = STI.classifyLocalReference(nullptr);
1399 
1400   if (CM == CodeModel::Large && STI.is64Bit()) {
1401     // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
1402     // they cannot be folded into immediate fields.
1403 
1404     Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
1405     BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1406         .addConstantPoolIndex(CPI, 0, OpFlag);
1407 
1408     MachineMemOperand *MMO = MF.getMachineMemOperand(
1409         MachinePointerInfo::getConstantPool(MF), MachineMemOperand::MOLoad,
1410         MF.getDataLayout().getPointerSize(), Alignment);
1411 
1412     LoadInst =
1413         addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
1414                      AddrReg)
1415             .addMemOperand(MMO);
1416 
1417   } else if (CM == CodeModel::Small || !STI.is64Bit()) {
1418     // Handle the case when globals fit in our immediate field.
1419     // This is true for X86-32 always and X86-64 when in -mcmodel=small mode.
1420 
1421     // x86-32 PIC requires a PIC base register for constant pools.
1422     unsigned PICBase = 0;
1423     if (OpFlag == X86II::MO_PIC_BASE_OFFSET || OpFlag == X86II::MO_GOTOFF) {
1424       // PICBase can be allocated by TII.getGlobalBaseReg(&MF).
1425       // In DAGISEL the code that initialize it generated by the CGBR pass.
1426       return false; // TODO support the mode.
1427     } else if (STI.is64Bit() && TM.getCodeModel() == CodeModel::Small)
1428       PICBase = X86::RIP;
1429 
1430     LoadInst = addConstantPoolReference(
1431         BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
1432         OpFlag);
1433   } else
1434     return false;
1435 
1436   constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI);
1437   I.eraseFromParent();
1438   return true;
1439 }
1440 
1441 bool X86InstructionSelector::selectImplicitDefOrPHI(
1442     MachineInstr &I, MachineRegisterInfo &MRI) const {
1443   assert((I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
1444           I.getOpcode() == TargetOpcode::G_PHI) &&
1445          "unexpected instruction");
1446 
1447   Register DstReg = I.getOperand(0).getReg();
1448 
1449   if (!MRI.getRegClassOrNull(DstReg)) {
1450     const LLT DstTy = MRI.getType(DstReg);
1451     const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI);
1452 
1453     if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1454       LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
1455                         << " operand\n");
1456       return false;
1457     }
1458   }
1459 
1460   if (I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1461     I.setDesc(TII.get(X86::IMPLICIT_DEF));
1462   else
1463     I.setDesc(TII.get(X86::PHI));
1464 
1465   return true;
1466 }
1467 
1468 bool X86InstructionSelector::selectDivRem(MachineInstr &I,
1469                                           MachineRegisterInfo &MRI,
1470                                           MachineFunction &MF) const {
1471   // The implementation of this function is taken from X86FastISel.
1472   assert((I.getOpcode() == TargetOpcode::G_SDIV ||
1473           I.getOpcode() == TargetOpcode::G_SREM ||
1474           I.getOpcode() == TargetOpcode::G_UDIV ||
1475           I.getOpcode() == TargetOpcode::G_UREM) &&
1476          "unexpected instruction");
1477 
1478   const Register DstReg = I.getOperand(0).getReg();
1479   const Register Op1Reg = I.getOperand(1).getReg();
1480   const Register Op2Reg = I.getOperand(2).getReg();
1481 
1482   const LLT RegTy = MRI.getType(DstReg);
1483   assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
1484          "Arguments and return value types must match");
1485 
1486   const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
1487   if (!RegRB || RegRB->getID() != X86::GPRRegBankID)
1488     return false;
1489 
1490   const static unsigned NumTypes = 4; // i8, i16, i32, i64
1491   const static unsigned NumOps = 4;   // SDiv, SRem, UDiv, URem
1492   const static bool S = true;         // IsSigned
1493   const static bool U = false;        // !IsSigned
1494   const static unsigned Copy = TargetOpcode::COPY;
1495   // For the X86 IDIV instruction, in most cases the dividend
1496   // (numerator) must be in a specific register pair highreg:lowreg,
1497   // producing the quotient in lowreg and the remainder in highreg.
1498   // For most data types, to set up the instruction, the dividend is
1499   // copied into lowreg, and lowreg is sign-extended into highreg.  The
1500   // exception is i8, where the dividend is defined as a single register rather
1501   // than a register pair, and we therefore directly sign-extend the dividend
1502   // into lowreg, instead of copying, and ignore the highreg.
1503   const static struct DivRemEntry {
1504     // The following portion depends only on the data type.
1505     unsigned SizeInBits;
1506     unsigned LowInReg;  // low part of the register pair
1507     unsigned HighInReg; // high part of the register pair
1508     // The following portion depends on both the data type and the operation.
1509     struct DivRemResult {
1510       unsigned OpDivRem;        // The specific DIV/IDIV opcode to use.
1511       unsigned OpSignExtend;    // Opcode for sign-extending lowreg into
1512                                 // highreg, or copying a zero into highreg.
1513       unsigned OpCopy;          // Opcode for copying dividend into lowreg, or
1514                                 // zero/sign-extending into lowreg for i8.
1515       unsigned DivRemResultReg; // Register containing the desired result.
1516       bool IsOpSigned;          // Whether to use signed or unsigned form.
1517     } ResultTable[NumOps];
1518   } OpTable[NumTypes] = {
1519       {8,
1520        X86::AX,
1521        0,
1522        {
1523            {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S}, // SDiv
1524            {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S}, // SRem
1525            {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U},  // UDiv
1526            {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U},  // URem
1527        }},                                                // i8
1528       {16,
1529        X86::AX,
1530        X86::DX,
1531        {
1532            {X86::IDIV16r, X86::CWD, Copy, X86::AX, S},    // SDiv
1533            {X86::IDIV16r, X86::CWD, Copy, X86::DX, S},    // SRem
1534            {X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U}, // UDiv
1535            {X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U}, // URem
1536        }},                                                // i16
1537       {32,
1538        X86::EAX,
1539        X86::EDX,
1540        {
1541            {X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S},    // SDiv
1542            {X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S},    // SRem
1543            {X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U}, // UDiv
1544            {X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U}, // URem
1545        }},                                                 // i32
1546       {64,
1547        X86::RAX,
1548        X86::RDX,
1549        {
1550            {X86::IDIV64r, X86::CQO, Copy, X86::RAX, S},    // SDiv
1551            {X86::IDIV64r, X86::CQO, Copy, X86::RDX, S},    // SRem
1552            {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv
1553            {X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U}, // URem
1554        }},                                                 // i64
1555   };
1556 
1557   auto OpEntryIt = std::find_if(std::begin(OpTable), std::end(OpTable),
1558                                 [RegTy](const DivRemEntry &El) {
1559                                   return El.SizeInBits == RegTy.getSizeInBits();
1560                                 });
1561   if (OpEntryIt == std::end(OpTable))
1562     return false;
1563 
1564   unsigned OpIndex;
1565   switch (I.getOpcode()) {
1566   default:
1567     llvm_unreachable("Unexpected div/rem opcode");
1568   case TargetOpcode::G_SDIV:
1569     OpIndex = 0;
1570     break;
1571   case TargetOpcode::G_SREM:
1572     OpIndex = 1;
1573     break;
1574   case TargetOpcode::G_UDIV:
1575     OpIndex = 2;
1576     break;
1577   case TargetOpcode::G_UREM:
1578     OpIndex = 3;
1579     break;
1580   }
1581 
1582   const DivRemEntry &TypeEntry = *OpEntryIt;
1583   const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
1584 
1585   const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
1586   if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
1587       !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
1588       !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {
1589     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
1590                       << " operand\n");
1591     return false;
1592   }
1593 
1594   // Move op1 into low-order input register.
1595   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy),
1596           TypeEntry.LowInReg)
1597       .addReg(Op1Reg);
1598   // Zero-extend or sign-extend into high-order input register.
1599   if (OpEntry.OpSignExtend) {
1600     if (OpEntry.IsOpSigned)
1601       BuildMI(*I.getParent(), I, I.getDebugLoc(),
1602               TII.get(OpEntry.OpSignExtend));
1603     else {
1604       Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
1605       BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
1606               Zero32);
1607 
1608       // Copy the zero into the appropriate sub/super/identical physical
1609       // register. Unfortunately the operations needed are not uniform enough
1610       // to fit neatly into the table above.
1611       if (RegTy.getSizeInBits() == 16) {
1612         BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1613                 TypeEntry.HighInReg)
1614             .addReg(Zero32, 0, X86::sub_16bit);
1615       } else if (RegTy.getSizeInBits() == 32) {
1616         BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1617                 TypeEntry.HighInReg)
1618             .addReg(Zero32);
1619       } else if (RegTy.getSizeInBits() == 64) {
1620         BuildMI(*I.getParent(), I, I.getDebugLoc(),
1621                 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
1622             .addImm(0)
1623             .addReg(Zero32)
1624             .addImm(X86::sub_32bit);
1625       }
1626     }
1627   }
1628   // Generate the DIV/IDIV instruction.
1629   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem))
1630       .addReg(Op2Reg);
1631   // For i8 remainder, we can't reference ah directly, as we'll end
1632   // up with bogus copies like %r9b = COPY %ah. Reference ax
1633   // instead to prevent ah references in a rex instruction.
1634   //
1635   // The current assumption of the fast register allocator is that isel
1636   // won't generate explicit references to the GR8_NOREX registers. If
1637   // the allocator and/or the backend get enhanced to be more robust in
1638   // that regard, this can be, and should be, removed.
1639   if ((I.getOpcode() == Instruction::SRem ||
1640        I.getOpcode() == Instruction::URem) &&
1641       OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) {
1642     Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1643     Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1644     BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg)
1645         .addReg(X86::AX);
1646 
1647     // Shift AX right by 8 bits instead of using AH.
1648     BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri),
1649             ResultSuperReg)
1650         .addReg(SourceSuperReg)
1651         .addImm(8);
1652 
1653     // Now reference the 8-bit subreg of the result.
1654     BuildMI(*I.getParent(), I, I.getDebugLoc(),
1655             TII.get(TargetOpcode::SUBREG_TO_REG))
1656         .addDef(DstReg)
1657         .addImm(0)
1658         .addReg(ResultSuperReg)
1659         .addImm(X86::sub_8bit);
1660   } else {
1661     BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
1662             DstReg)
1663         .addReg(OpEntry.DivRemResultReg);
1664   }
1665   I.eraseFromParent();
1666   return true;
1667 }
1668 
1669 bool X86InstructionSelector::selectIntrinsicWSideEffects(
1670     MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const {
1671 
1672   assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
1673          "unexpected instruction");
1674 
1675   if (I.getOperand(0).getIntrinsicID() != Intrinsic::trap)
1676     return false;
1677 
1678   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP));
1679 
1680   I.eraseFromParent();
1681   return true;
1682 }
1683 
1684 InstructionSelector *
1685 llvm::createX86InstructionSelector(const X86TargetMachine &TM,
1686                                    X86Subtarget &Subtarget,
1687                                    X86RegisterBankInfo &RBI) {
1688   return new X86InstructionSelector(TM, Subtarget, RBI);
1689 }
1690