1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
23
24// CPU flow control instructions
25
26let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41// The long form of "int $3" turns into int3 as a size optimization.
42// FIXME: This doesn't work because InstAlias can't match immediate constants.
43//def : InstAlias<"int\t$3", (INT3)>;
44
45let SchedRW = [WriteSystem] in {
46
47def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
48              [(int_x86_int imm:$trap)], IIC_INT>;
49
50
51def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
52def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
53def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
54               Requires<[In64BitMode]>;
55
56def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
57                 IIC_SYS_ENTER_EXIT>, TB;
58
59def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
62                 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
63} // SchedRW
64
65def : Pat<(debugtrap),
66          (INT3)>, Requires<[NotPS4]>;
67def : Pat<(debugtrap),
68          (INT (i8 0x41))>, Requires<[IsPS4]>;
69
70//===----------------------------------------------------------------------===//
71//  Input/Output Instructions.
72//
73let SchedRW = [WriteSystem] in {
74let Defs = [AL], Uses = [DX] in
75def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
76               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
77let Defs = [AX], Uses = [DX] in
78def IN16rr : I<0xED, RawFrm, (outs), (ins),
79               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
80let Defs = [EAX], Uses = [DX] in
81def IN32rr : I<0xED, RawFrm, (outs), (ins),
82               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
83
84let Defs = [AL] in
85def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
86                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
87let Defs = [AX] in
88def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
89                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
90let Defs = [EAX] in
91def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
92                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
93
94let Uses = [DX, AL] in
95def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
96                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
97let Uses = [DX, AX] in
98def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
99                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
100let Uses = [DX, EAX] in
101def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
102                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
103
104let Uses = [AL] in
105def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
106                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
107let Uses = [AX] in
108def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
109                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
110let Uses = [EAX] in
111def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
112                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
113
114} // SchedRW
115
116//===----------------------------------------------------------------------===//
117// Moves to and from debug registers
118
119let SchedRW = [WriteSystem] in {
120def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
121                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
122                Requires<[Not64BitMode]>;
123def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
124                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
125                Requires<[In64BitMode]>;
126
127def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
128                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
129                Requires<[Not64BitMode]>;
130def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
131                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
132                Requires<[In64BitMode]>;
133} // SchedRW
134
135//===----------------------------------------------------------------------===//
136// Moves to and from control registers
137
138let SchedRW = [WriteSystem] in {
139def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
140                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
141                Requires<[Not64BitMode]>;
142def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
143                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
144                Requires<[In64BitMode]>;
145
146def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
147                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
148                Requires<[Not64BitMode]>;
149def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
150                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
151                Requires<[In64BitMode]>;
152} // SchedRW
153
154//===----------------------------------------------------------------------===//
155// Segment override instruction prefixes
156
157def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
158def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
159def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
160def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
161def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
162def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
163
164
165//===----------------------------------------------------------------------===//
166// Moves to and from segment registers.
167//
168
169let SchedRW = [WriteMove] in {
170def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
171                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
172def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
173                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
174def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
175                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
176let mayStore = 1 in {
177def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
178                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore;
179}
180def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
181                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
182def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
183                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
184def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
185                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
186let mayLoad = 1 in {
187def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
188                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore;
189}
190} // SchedRW
191
192//===----------------------------------------------------------------------===//
193// Segmentation support instructions.
194
195let SchedRW = [WriteSystem] in {
196def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
197
198let mayLoad = 1 in
199def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
200                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
201                OpSize16;
202def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
203                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
204                OpSize16;
205
206// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
207let mayLoad = 1 in
208def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
209                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
210                OpSize32;
211def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
212                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
213                OpSize32;
214// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
215let mayLoad = 1 in
216def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
217                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
218def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
219                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
220
221let mayLoad = 1 in
222def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
223                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
224                OpSize16;
225def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
226                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
227                OpSize16;
228let mayLoad = 1 in
229def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
230                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
231                OpSize32;
232def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
233                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
234                OpSize32;
235let mayLoad = 1 in
236def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
237                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
238def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
239                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
240
241def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
242               [], IIC_INVLPG>, TB;
243
244def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
245               "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
246def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
247               "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
248def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
249                "str{q}\t$dst", [], IIC_STR>, TB;
250let mayStore = 1 in
251def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
252               "str{w}\t$dst", [], IIC_STR>, TB;
253
254def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
255             "ltr{w}\t$src", [], IIC_LTR>, TB;
256let mayLoad = 1 in
257def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
258             "ltr{w}\t$src", [], IIC_LTR>, TB;
259
260def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
261                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
262                 OpSize16, Requires<[Not64BitMode]>;
263def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
264                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
265                 OpSize32, Requires<[Not64BitMode]>;
266def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
267                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
268                 OpSize16, Requires<[Not64BitMode]>;
269def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
270                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
271                 OpSize32, Requires<[Not64BitMode]>;
272def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
273                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
274                 OpSize16, Requires<[Not64BitMode]>;
275def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
276                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
277                 OpSize32, Requires<[Not64BitMode]>;
278def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
279                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
280                 OpSize16, Requires<[Not64BitMode]>;
281def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
282                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
283                 OpSize32, Requires<[Not64BitMode]>;
284def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
285                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
286def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
287                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
288               OpSize32, Requires<[Not64BitMode]>;
289def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
290                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
291def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
292                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
293               OpSize32, Requires<[Not64BitMode]>;
294def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
295                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
296               OpSize32, Requires<[In64BitMode]>;
297def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
298                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
299               OpSize32, Requires<[In64BitMode]>;
300
301// No "pop cs" instruction.
302def POPSS16 : I<0x17, RawFrm, (outs), (ins),
303                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
304              OpSize16, Requires<[Not64BitMode]>;
305def POPSS32 : I<0x17, RawFrm, (outs), (ins),
306                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
307              OpSize32, Requires<[Not64BitMode]>;
308
309def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
310                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
311              OpSize16, Requires<[Not64BitMode]>;
312def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
313                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
314              OpSize32, Requires<[Not64BitMode]>;
315
316def POPES16 : I<0x07, RawFrm, (outs), (ins),
317                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
318              OpSize16, Requires<[Not64BitMode]>;
319def POPES32 : I<0x07, RawFrm, (outs), (ins),
320                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
321              OpSize32, Requires<[Not64BitMode]>;
322
323def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
324                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
325def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
326                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
327              OpSize32, Requires<[Not64BitMode]>;
328def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
329                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
330              OpSize32, Requires<[In64BitMode]>;
331
332def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
333                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
334def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
335                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
336              OpSize32, Requires<[Not64BitMode]>;
337def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
338                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
339              OpSize32, Requires<[In64BitMode]>;
340
341
342def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
343                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
344                Requires<[Not64BitMode]>;
345def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
346                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
347                Requires<[Not64BitMode]>;
348
349def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
350                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
351def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
352                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
353def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
354                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
355
356def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
357                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
358                Requires<[Not64BitMode]>;
359def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
360                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
361                Requires<[Not64BitMode]>;
362
363def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
364                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
365def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
366                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
367def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
368                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
369
370def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
371                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
372def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
373                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
374
375def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
376                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
377
378
379def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
380              "verr\t$seg", [], IIC_VERR>, TB;
381def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
382              "verw\t$seg", [], IIC_VERW_MEM>, TB;
383let mayLoad = 1 in {
384def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
385              "verr\t$seg", [], IIC_VERR>, TB;
386def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
387              "verw\t$seg", [], IIC_VERW_REG>, TB;
388}
389} // SchedRW
390
391//===----------------------------------------------------------------------===//
392// Descriptor-table support instructions
393
394let SchedRW = [WriteSystem] in {
395def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
396              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
397def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
398              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
399def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
400              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
401def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
402              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
403def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
404              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
405def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
406              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
407def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
408                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
409let mayStore = 1 in
410def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
411                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
412def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
413                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
414
415// LLDT is not interpreted specially in 64-bit mode because there is no sign
416//   extension.
417def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
418                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
419let mayStore = 1 in
420def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
421                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
422
423def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
424              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
425def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
426              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
427def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
428              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
429def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
430              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
431def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
432              "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
433def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
434              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
435def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
436                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
437let mayLoad = 1 in
438def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
439                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
440} // SchedRW
441
442//===----------------------------------------------------------------------===//
443// Specialized register support
444let SchedRW = [WriteSystem] in {
445let Uses = [EAX, ECX, EDX] in
446def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
447let Defs = [EAX, EDX], Uses = [ECX] in
448def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
449
450let Defs = [RAX, RDX], Uses = [ECX] in
451  def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
452              TB;
453
454def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
455                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
456def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
457                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
458// no m form encodable; use SMSW16m
459def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
460                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
461
462// For memory operands, there is only a 16-bit form
463def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
464                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
465
466def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
467                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
468let mayLoad = 1 in
469def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
470                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
471
472let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
473  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
474} // SchedRW
475
476//===----------------------------------------------------------------------===//
477// Cache instructions
478let SchedRW = [WriteSystem] in {
479def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
480def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
481} // SchedRW
482
483//===----------------------------------------------------------------------===//
484// CET instructions
485let SchedRW = [WriteSystem], Predicates = [HasSHSTK]  in{
486  let Uses = [SSP] in {
487    let Defs = [SSP] in {
488      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
489                       [(int_x86_incsspd GR32:$src)]>, XS;
490      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
491                       [(int_x86_incsspq GR64:$src)]>, XS,
492                       Requires<[In64BitMode]>;
493    } // Defs SSP
494
495    let Constraints = "$src = $dst" in {
496      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
497                     "rdsspd\t$dst",
498                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
499      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
500                     "rdsspq\t$dst",
501                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS,
502                     Requires<[In64BitMode]>;
503    }
504
505    let Defs = [SSP] in {
506      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
507                       [(int_x86_saveprevssp)]>, XS;
508      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
509                       "rstorssp\t$src",
510                       [(int_x86_rstorssp addr:$src)]>, XS;
511    } // Defs SSP
512  } // Uses SSP
513
514  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
515                "wrssd\t{$src, $dst|$dst, $src}",
516                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8;
517  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
518                 "wrssq\t{$src, $dst|$dst, $src}",
519                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8,
520                 Requires<[In64BitMode]>;
521  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
522                 "wrussd\t{$src, $dst|$dst, $src}",
523                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
524  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
525                  "wrussq\t{$src, $dst|$dst, $src}",
526                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD,
527                  Requires<[In64BitMode]>;
528
529  let Defs = [SSP] in {
530    let Uses = [SSP] in {
531        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
532                         [(int_x86_setssbsy)]>, XS;
533    } // Uses SSP
534
535    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
536                     "clrssbsy\t$src",
537                     [(int_x86_clrssbsy addr:$src)]>, XS;
538  } // Defs SSP
539} // SchedRW && HasSHSTK
540
541//===----------------------------------------------------------------------===//
542// XSAVE instructions
543let SchedRW = [WriteSystem] in {
544let Predicates = [HasXSAVE] in {
545let Defs = [EDX, EAX], Uses = [ECX] in
546  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
547
548let Uses = [EDX, EAX, ECX] in
549  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
550                "xsetbv",
551                [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
552
553} // HasXSAVE
554
555let Uses = [EDX, EAX] in {
556let Predicates = [HasXSAVE] in {
557  def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
558                "xsave\t$dst",
559                [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS;
560  def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
561                   "xsave64\t$dst",
562                   [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
563  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
564                 "xrstor\t$dst",
565                 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS;
566  def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
567                    "xrstor64\t$dst",
568                    [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
569}
570let Predicates = [HasXSAVEOPT] in {
571  def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
572                   "xsaveopt\t$dst",
573                   [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS;
574  def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
575                      "xsaveopt64\t$dst",
576                      [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
577}
578let Predicates = [HasXSAVEC] in {
579  def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
580                 "xsavec\t$dst",
581                 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB;
582  def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
583                   "xsavec64\t$dst",
584                   [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
585}
586let Predicates = [HasXSAVES] in {
587  def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
588                 "xsaves\t$dst",
589                 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB;
590  def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
591                    "xsaves64\t$dst",
592                    [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
593  def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
594                  "xrstors\t$dst",
595                  [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB;
596  def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
597                     "xrstors64\t$dst",
598                     [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
599}
600} // Uses
601} // SchedRW
602
603//===----------------------------------------------------------------------===//
604// VIA PadLock crypto instructions
605let Defs = [RAX, RDI], Uses = [RDX, RDI] in
606  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
607
608def : InstAlias<"xstorerng", (XSTORE)>;
609
610let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
611  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
612  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
613  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
614  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
615  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
616}
617
618let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
619  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
620  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
621}
622let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
623  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
624//==-----------------------------------------------------------------------===//
625// PKU  - enable protection key
626let usesCustomInserter = 1 in {
627  def WRPKRU : PseudoI<(outs), (ins GR32:$src),
628                [(int_x86_wrpkru GR32:$src)]>;
629  def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
630                [(set GR32:$dst, (int_x86_rdpkru))]>;
631}
632
633let Defs = [EAX, EDX], Uses = [ECX] in
634  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB;
635let Uses = [EAX, ECX, EDX] in
636  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB;
637
638//===----------------------------------------------------------------------===//
639// FS/GS Base Instructions
640let Predicates = [HasFSGSBase, In64BitMode] in {
641  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
642                   "rdfsbase{l}\t$dst",
643                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
644  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
645                     "rdfsbase{q}\t$dst",
646                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
647  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
648                   "rdgsbase{l}\t$dst",
649                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
650  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
651                     "rdgsbase{q}\t$dst",
652                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
653  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
654                   "wrfsbase{l}\t$src",
655                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
656  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
657                      "wrfsbase{q}\t$src",
658                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
659  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
660                   "wrgsbase{l}\t$src",
661                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
662  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
663                      "wrgsbase{q}\t$src",
664                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
665}
666
667//===----------------------------------------------------------------------===//
668// INVPCID Instruction
669def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
670                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
671                Requires<[Not64BitMode]>;
672def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
673                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
674                Requires<[In64BitMode]>;
675
676//===----------------------------------------------------------------------===//
677// SMAP Instruction
678let Defs = [EFLAGS] in {
679  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
680  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
681}
682
683//===----------------------------------------------------------------------===//
684// SMX Instruction
685let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
686  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
687}
688
689//===----------------------------------------------------------------------===//
690// RDPID Instruction
691def RDPID32 : I<0xC7, MRM7r, (outs GR32:$src), (ins),
692              "rdpid\t$src", []>, XS,
693              Requires<[Not64BitMode]>;
694def RDPID64 : I<0xC7, MRM7r, (outs GR64:$src), (ins),
695              "rdpid\t$src", []>, XS,
696              Requires<[In64BitMode]>;
697
698//===----------------------------------------------------------------------===//
699// PTWRITE Instruction
700def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
701                "ptwrite{l}\t$dst", []>, XS;
702def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
703                    "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
704
705def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
706                "ptwrite{l}\t$dst", []>, XS;
707def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
708                   "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
709