1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instructions that are generally used in
10// privileged modes.  These are not typically used by the compiler, but are
11// supported for the assembler and disassembler.
12//
13//===----------------------------------------------------------------------===//
14
15let SchedRW = [WriteSystem] in {
16let Defs = [RAX, RDX] in
17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26
27  def UD1Wm   : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
28                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
29  def UD1Lm   : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
30                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
31  def UD1Qm   : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
32                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
33
34  def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
35                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
36  def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
37                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
38  def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
39                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
40}
41
42def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
43def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
44
45// Interrupt and SysCall Instructions.
46let Uses = [EFLAGS] in
47  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
48
49def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
50
51def UBSAN_UD1 : PseudoI<(outs), (ins i32imm:$kind), [(ubsantrap (i32 timm:$kind))]>;
52// The long form of "int $3" turns into int3 as a size optimization.
53// FIXME: This doesn't work because InstAlias can't match immediate constants.
54//def : InstAlias<"int\t$3", (INT3)>;
55
56def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
57              [(int_x86_int timm:$trap)]>;
58
59
60def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
61def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
62def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
63               Requires<[In64BitMode]>;
64
65def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
66
67def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
68def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
69                  Requires<[In64BitMode]>;
70} // SchedRW
71
72def : Pat<(debugtrap),
73          (INT3)>, Requires<[NotPS4]>;
74def : Pat<(debugtrap),
75          (INT (i8 0x41))>, Requires<[IsPS4]>;
76
77//===----------------------------------------------------------------------===//
78//  Input/Output Instructions.
79//
80let SchedRW = [WriteSystem] in {
81let Defs = [AL], Uses = [DX] in
82def IN8rr  : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
83let Defs = [AX], Uses = [DX] in
84def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
85               OpSize16;
86let Defs = [EAX], Uses = [DX] in
87def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
88               OpSize32;
89
90let Defs = [AL] in
91def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
92                 "in{b}\t{$port, %al|al, $port}", []>;
93let Defs = [AX] in
94def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
95                 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
96let Defs = [EAX] in
97def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
98                 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
99
100let Uses = [DX, AL] in
101def OUT8rr  : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
102let Uses = [DX, AX] in
103def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
104                OpSize16;
105let Uses = [DX, EAX] in
106def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
107                OpSize32;
108
109let Uses = [AL] in
110def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
111                   "out{b}\t{%al, $port|$port, al}", []>;
112let Uses = [AX] in
113def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
114                   "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
115let Uses = [EAX] in
116def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
117                  "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
118
119} // SchedRW
120
121//===----------------------------------------------------------------------===//
122// Moves to and from debug registers
123
124let SchedRW = [WriteSystem] in {
125def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
126                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
127                Requires<[Not64BitMode]>;
128def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
129                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
130                Requires<[In64BitMode]>;
131
132def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
133                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
134                Requires<[Not64BitMode]>;
135def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
136                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
137                Requires<[In64BitMode]>;
138} // SchedRW
139
140//===----------------------------------------------------------------------===//
141// Moves to and from control registers
142
143let SchedRW = [WriteSystem] in {
144def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
145                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
146                Requires<[Not64BitMode]>;
147def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
148                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
149                Requires<[In64BitMode]>;
150
151def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
152                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
153                Requires<[Not64BitMode]>;
154def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
155                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
156                Requires<[In64BitMode]>;
157} // SchedRW
158
159//===----------------------------------------------------------------------===//
160// Segment override instruction prefixes
161
162let SchedRW = [WriteNop] in {
163def CS_PREFIX : I<0x2E, PrefixByte, (outs), (ins), "cs", []>;
164def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>;
165def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>;
166def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>;
167def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>;
168def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>;
169} // SchedRW
170
171//===----------------------------------------------------------------------===//
172// Address-size override prefixes.
173//
174
175let SchedRW = [WriteNop] in {
176def ADDR16_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr16", []>,
177                      Requires<[In32BitMode]>;
178def ADDR32_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr32", []>,
179                      Requires<[In64BitMode]>;
180} // SchedRW
181
182//===----------------------------------------------------------------------===//
183// Moves to and from segment registers.
184//
185
186let SchedRW = [WriteMove] in {
187def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
188                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
189def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
190                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
191def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
192                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
193let mayStore = 1 in {
194def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
195                "mov{w}\t{$src, $dst|$dst, $src}", []>;
196}
197def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
198                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
199def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
200                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
201def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
202                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
203let mayLoad = 1 in {
204def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
205                "mov{w}\t{$src, $dst|$dst, $src}", []>;
206}
207} // SchedRW
208
209//===----------------------------------------------------------------------===//
210// Segmentation support instructions.
211
212let SchedRW = [WriteSystem] in {
213def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
214
215let mayLoad = 1 in
216def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
217                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
218                OpSize16, NotMemoryFoldable;
219def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
220                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
221                OpSize16, NotMemoryFoldable;
222
223let mayLoad = 1 in
224def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
225                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
226                OpSize32, NotMemoryFoldable;
227def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
228                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
229                OpSize32, NotMemoryFoldable;
230let mayLoad = 1 in
231def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
232                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
233def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
234                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
235
236let mayLoad = 1 in
237def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
238                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
239                OpSize16, NotMemoryFoldable;
240def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
241                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
242                OpSize16, NotMemoryFoldable;
243let mayLoad = 1 in
244def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
245                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
246                OpSize32, NotMemoryFoldable;
247def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
248                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
249                OpSize32, NotMemoryFoldable;
250let mayLoad = 1 in
251def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
252                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
253def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
254                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
255
256def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
257
258def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
259               "str{w}\t$dst", []>, TB, OpSize16;
260def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
261               "str{l}\t$dst", []>, TB, OpSize32;
262def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
263                "str{q}\t$dst", []>, TB;
264let mayStore = 1 in
265def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
266
267def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
268let mayLoad = 1 in
269def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
270
271def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
272                 OpSize16, Requires<[Not64BitMode]>;
273def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
274                 OpSize32, Requires<[Not64BitMode]>;
275def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
276                 OpSize16, Requires<[Not64BitMode]>;
277def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
278                 OpSize32, Requires<[Not64BitMode]>;
279def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
280                 OpSize16, Requires<[Not64BitMode]>;
281def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
282                 OpSize32, Requires<[Not64BitMode]>;
283def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
284                 OpSize16, Requires<[Not64BitMode]>;
285def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
286                 OpSize32, Requires<[Not64BitMode]>;
287def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
288                 OpSize16, TB;
289def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
290                 OpSize32, Requires<[Not64BitMode]>;
291def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
292                 OpSize16, TB;
293def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
294                 OpSize32, Requires<[Not64BitMode]>;
295def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
296                 OpSize32, Requires<[In64BitMode]>;
297def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
298                 OpSize32, Requires<[In64BitMode]>;
299
300// No "pop cs" instruction.
301def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
302              OpSize16, Requires<[Not64BitMode]>;
303def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
304              OpSize32, Requires<[Not64BitMode]>;
305
306def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
307              OpSize16, Requires<[Not64BitMode]>;
308def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
309              OpSize32, Requires<[Not64BitMode]>;
310
311def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
312              OpSize16, Requires<[Not64BitMode]>;
313def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
314              OpSize32, Requires<[Not64BitMode]>;
315
316def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
317                OpSize16, TB;
318def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
319                OpSize32, Requires<[Not64BitMode]>;
320def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
321                OpSize32, Requires<[In64BitMode]>;
322
323def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
324                OpSize16, TB;
325def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
326                OpSize32, Requires<[Not64BitMode]>;
327def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
328                OpSize32, Requires<[In64BitMode]>;
329
330def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
331                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
332                Requires<[Not64BitMode]>;
333def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
334                "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
335                Requires<[Not64BitMode]>;
336
337def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
338                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
339def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
340                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
341def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
342                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
343
344def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
345                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
346                Requires<[Not64BitMode]>;
347def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
348                "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
349                Requires<[Not64BitMode]>;
350
351def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
352                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
353def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
354                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
355def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
356                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
357
358def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
359                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
360def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
361                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
362
363def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
364                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
365
366def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
367def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
368let mayLoad = 1 in {
369def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
370def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
371}
372} // SchedRW
373
374//===----------------------------------------------------------------------===//
375// Descriptor-table support instructions
376
377let SchedRW = [WriteSystem] in {
378def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
379                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
380def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
381                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
382def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
383                "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
384def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
385                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
386def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
387                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
388def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
389                "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
390def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
391                "sldt{w}\t$dst", []>, TB, OpSize16;
392let mayStore = 1 in
393def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
394                "sldt{w}\t$dst", []>, TB;
395def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
396                "sldt{l}\t$dst", []>, OpSize32, TB;
397
398// LLDT is not interpreted specially in 64-bit mode because there is no sign
399//   extension.
400def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
401                 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
402
403def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
404                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
405def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
406                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
407def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
408                "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
409def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
410                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
411def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
412                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
413def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
414                "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
415def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
416                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
417let mayLoad = 1 in
418def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
419                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
420} // SchedRW
421
422//===----------------------------------------------------------------------===//
423// Specialized register support
424let SchedRW = [WriteSystem] in {
425let Uses = [EAX, ECX, EDX] in
426def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
427let Defs = [EAX, EDX], Uses = [ECX] in
428def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
429
430let Defs = [RAX, RDX], Uses = [ECX] in
431def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
432
433def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
434                "smsw{w}\t$dst", []>, OpSize16, TB;
435def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
436                "smsw{l}\t$dst", []>, OpSize32, TB;
437// no m form encodable; use SMSW16m
438def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
439                 "smsw{q}\t$dst", []>, TB;
440
441// For memory operands, there is only a 16-bit form
442def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
443                "smsw{w}\t$dst", []>, TB;
444
445def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
446                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
447let mayLoad = 1 in
448def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
449                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
450
451let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
452  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
453} // SchedRW
454
455//===----------------------------------------------------------------------===//
456// Cache instructions
457let SchedRW = [WriteSystem] in {
458def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
459def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, PS;
460
461// wbnoinvd is like wbinvd, except without invalidation
462// encoding: like wbinvd + an 0xF3 prefix
463def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
464                 [(int_x86_wbnoinvd)]>, XS,
465                 Requires<[HasWBNOINVD]>;
466} // SchedRW
467
468//===----------------------------------------------------------------------===//
469// CET instructions
470// Use with caution, availability is not predicated on features.
471let SchedRW = [WriteSystem] in {
472  let Uses = [SSP] in {
473    let Defs = [SSP] in {
474      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
475                       [(int_x86_incsspd GR32:$src)]>, XS;
476      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
477                       [(int_x86_incsspq GR64:$src)]>, XS;
478    } // Defs SSP
479
480    let Constraints = "$src = $dst" in {
481      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
482                     "rdsspd\t$dst",
483                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
484      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
485                     "rdsspq\t$dst",
486                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
487    }
488
489    let Defs = [SSP] in {
490      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
491                       [(int_x86_saveprevssp)]>, XS;
492      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
493                       "rstorssp\t$src",
494                       [(int_x86_rstorssp addr:$src)]>, XS;
495    } // Defs SSP
496  } // Uses SSP
497
498  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
499                "wrssd\t{$src, $dst|$dst, $src}",
500                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
501  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
502                 "wrssq\t{$src, $dst|$dst, $src}",
503                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
504  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
505                 "wrussd\t{$src, $dst|$dst, $src}",
506                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
507  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
508                  "wrussq\t{$src, $dst|$dst, $src}",
509                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
510
511  let Defs = [SSP] in {
512    let Uses = [SSP] in {
513        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
514                         [(int_x86_setssbsy)]>, XS;
515    } // Uses SSP
516
517    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
518                     "clrssbsy\t$src",
519                     [(int_x86_clrssbsy addr:$src)]>, XS;
520  } // Defs SSP
521} // SchedRW
522
523let SchedRW = [WriteSystem] in {
524    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
525    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
526} // SchedRW
527
528//===----------------------------------------------------------------------===//
529// XSAVE instructions
530let SchedRW = [WriteSystem] in {
531let Predicates = [HasXSAVE] in {
532let Defs = [EDX, EAX], Uses = [ECX] in
533  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, PS;
534
535let Uses = [EDX, EAX, ECX] in
536  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
537                "xsetbv",
538                [(int_x86_xsetbv ECX, EDX, EAX)]>, PS;
539
540} // HasXSAVE
541
542let Uses = [EDX, EAX] in {
543def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
544              "xsave\t$dst",
545              [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
546def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
547                 "xsave64\t$dst",
548                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
549def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
550               "xrstor\t$dst",
551               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
552def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
553                  "xrstor64\t$dst",
554                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
555def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
556                 "xsaveopt\t$dst",
557                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
558def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
559                    "xsaveopt64\t$dst",
560                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
561def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
562               "xsavec\t$dst",
563               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC]>;
564def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
565                 "xsavec64\t$dst",
566                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC, In64BitMode]>;
567def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
568               "xsaves\t$dst",
569               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
570def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
571                  "xsaves64\t$dst",
572                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
573def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
574                "xrstors\t$dst",
575                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
576def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
577                   "xrstors64\t$dst",
578                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES, In64BitMode]>;
579} // Uses
580} // SchedRW
581
582//===----------------------------------------------------------------------===//
583// VIA PadLock crypto instructions
584let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
585  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB, REP;
586
587def : InstAlias<"xstorerng", (XSTORE)>;
588
589let SchedRW = [WriteSystem] in {
590let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
591  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB, REP;
592  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB, REP;
593  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB, REP;
594  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB, REP;
595  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB, REP;
596}
597
598let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
599  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB, REP;
600  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB, REP;
601}
602let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
603  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB, REP;
604} // SchedRW
605
606//==-----------------------------------------------------------------------===//
607// PKU  - enable protection key
608let SchedRW = [WriteSystem] in {
609let Defs = [EAX, EDX], Uses = [ECX] in
610  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
611                  [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, PS;
612let Uses = [EAX, ECX, EDX] in
613  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
614                  [(X86wrpkru EAX, EDX, ECX)]>, PS;
615} // SchedRW
616
617//===----------------------------------------------------------------------===//
618// FS/GS Base Instructions
619let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
620  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
621                   "rdfsbase{l}\t$dst",
622                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
623  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
624                     "rdfsbase{q}\t$dst",
625                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
626  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
627                   "rdgsbase{l}\t$dst",
628                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
629  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
630                     "rdgsbase{q}\t$dst",
631                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
632  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
633                   "wrfsbase{l}\t$src",
634                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
635  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
636                      "wrfsbase{q}\t$src",
637                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
638  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
639                   "wrgsbase{l}\t$src",
640                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
641  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
642                      "wrgsbase{q}\t$src",
643                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
644}
645
646//===----------------------------------------------------------------------===//
647// INVPCID Instruction
648let SchedRW = [WriteSystem] in {
649def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
650                  "invpcid\t{$src2, $src1|$src1, $src2}",
651                  [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD,
652                  Requires<[Not64BitMode, HasINVPCID]>;
653def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
654                  "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
655                  Requires<[In64BitMode, HasINVPCID]>;
656} // SchedRW
657
658let Predicates = [In64BitMode, HasINVPCID] in {
659  // The instruction can only use a 64 bit register as the register argument
660  // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
661  // corresponding to it.
662  // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
663  // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
664  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
665            (INVPCID64
666              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
667              addr:$src2)>;
668}
669
670
671//===----------------------------------------------------------------------===//
672// SMAP Instruction
673let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
674  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, PS;
675  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, PS;
676}
677
678//===----------------------------------------------------------------------===//
679// SMX Instruction
680let SchedRW = [WriteSystem] in {
681let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
682  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, PS;
683} // Uses, Defs
684} // SchedRW
685
686//===----------------------------------------------------------------------===//
687// TS flag control instruction.
688let SchedRW = [WriteSystem] in {
689def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
690}
691
692//===----------------------------------------------------------------------===//
693// IF (inside EFLAGS) management instructions.
694let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
695def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
696def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
697}
698
699//===----------------------------------------------------------------------===//
700// RDPID Instruction
701let SchedRW = [WriteSystem] in {
702def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
703                "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS,
704                Requires<[Not64BitMode, HasRDPID]>;
705def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
706                Requires<[In64BitMode, HasRDPID]>;
707} // SchedRW
708
709let Predicates = [In64BitMode, HasRDPID] in {
710  // Due to silly instruction definition, we have to compensate for the
711  // instruction outputing a 64-bit register.
712  def : Pat<(int_x86_rdpid),
713            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
714}
715
716
717//===----------------------------------------------------------------------===//
718// PTWRITE Instruction - Write Data to a Processor Trace Packet
719let SchedRW = [WriteSystem] in {
720def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
721                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
722                Requires<[HasPTWRITE]>;
723def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
724                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
725                    Requires<[In64BitMode, HasPTWRITE]>;
726
727def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
728                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
729                    Requires<[HasPTWRITE]>;
730def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
731                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
732                    Requires<[In64BitMode, HasPTWRITE]>;
733} // SchedRW
734
735//===----------------------------------------------------------------------===//
736// Platform Configuration instruction
737
738// From ISA docs:
739//  "This instruction is used to execute functions for configuring platform
740//   features.
741//   EAX: Leaf function to be invoked.
742//   RBX/RCX/RDX: Leaf-specific purpose."
743//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
744//   AF, OF, and SF are cleared. In case of failure, the failure reason is
745//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
746// Thus all these mentioned registers are considered clobbered.
747
748let SchedRW = [WriteSystem] in {
749let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
750    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, PS,
751                  Requires<[HasPCONFIG]>;
752} // SchedRW
753