1//===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let Defs = [RAX, RDX] in
17  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
27}
28
29def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
31
32// Interrupt and SysCall Instructions.
33let Uses = [EFLAGS] in
34  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
35def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
36              [(int_x86_int (i8 3))]>;
37def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
38              [(int_x86_int imm:$trap)]>;
39
40def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
41def SYSRETL  : I<0x07, RawFrm, (outs), (ins), "sysretl", []>, TB;
42def SYSRETQ  :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
43               Requires<[In64BitMode]>;
44
45def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
46
47def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
48                Requires<[In32BitMode]>;
49def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
50                Requires<[In64BitMode]>;
51
52def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
53def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
54def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
55             Requires<[In64BitMode]>;
56
57
58//===----------------------------------------------------------------------===//
59//  Input/Output Instructions.
60//
61let Defs = [AL], Uses = [DX] in
62def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
63               "in{b}\t{%dx, %al|%AL, %DX}", []>;
64let Defs = [AX], Uses = [DX] in
65def IN16rr : I<0xED, RawFrm, (outs), (ins),
66               "in{w}\t{%dx, %ax|%AX, %DX}", []>,  OpSize;
67let Defs = [EAX], Uses = [DX] in
68def IN32rr : I<0xED, RawFrm, (outs), (ins),
69               "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
70
71let Defs = [AL] in
72def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
73                  "in{b}\t{$port, %al|%AL, $port}", []>;
74let Defs = [AX] in
75def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
76                  "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
77let Defs = [EAX] in
78def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
79                  "in{l}\t{$port, %eax|%EAX, $port}", []>;
80
81let Uses = [DX, AL] in
82def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
83                "out{b}\t{%al, %dx|%DX, %AL}", []>;
84let Uses = [DX, AX] in
85def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
86                "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
87let Uses = [DX, EAX] in
88def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
89                "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
90
91let Uses = [AL] in
92def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
93                   "out{b}\t{%al, $port|$port, %AL}", []>;
94let Uses = [AX] in
95def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
96                   "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
97let Uses = [EAX] in
98def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
99                   "out{l}\t{%eax, $port|$port, %EAX}", []>;
100
101def IN8  : I<0x6C, RawFrm, (outs), (ins), "ins{b}", []>;
102def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>,  OpSize;
103def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", []>;
104
105//===----------------------------------------------------------------------===//
106// Moves to and from debug registers
107
108def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
109                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
110def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
111                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
112
113def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
114                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
115def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
116                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
117
118//===----------------------------------------------------------------------===//
119// Moves to and from control registers
120
121def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
122                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
123def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
124                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
125
126def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
127                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
128def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
129                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
130
131//===----------------------------------------------------------------------===//
132// Segment override instruction prefixes
133
134def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
135def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
136def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
137def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
138def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
139def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
140
141
142//===----------------------------------------------------------------------===//
143// Moves to and from segment registers.
144//
145
146def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
147                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
148def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
149                "mov{l}\t{$src, $dst|$dst, $src}", []>;
150def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
151                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
152
153def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
154                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
155def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
156                "mov{l}\t{$src, $dst|$dst, $src}", []>;
157def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
158                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
159
160def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
161                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
162def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
163                "mov{l}\t{$src, $dst|$dst, $src}", []>;
164def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
165                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
166
167def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
168                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
169def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
170                "mov{l}\t{$src, $dst|$dst, $src}", []>;
171def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
172                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
173
174//===----------------------------------------------------------------------===//
175// Segmentation support instructions.
176
177def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
178
179def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
180                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
181def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
182                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
183
184// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
185def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
186                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
187def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
188                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
189// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
190def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
191                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
192def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
193                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
194
195def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
196                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
197def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
198                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
199def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
200                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
201def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
202                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
203def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
204                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
205def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
206                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
207
208def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
209
210def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
211             "str{w}\t{$dst}", []>, TB;
212def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
213             "str{w}\t{$dst}", []>, TB;
214def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
215             "ltr{w}\t{$src}", []>, TB;
216def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
217             "ltr{w}\t{$src}", []>, TB;
218
219def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
220                 "push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
221def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
222                 "push{l}\t%cs", []>, Requires<[In32BitMode]>;
223def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
224                 "push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
225def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
226                 "push{l}\t%ss", []>, Requires<[In32BitMode]>;
227def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
228                 "push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
229def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
230                 "push{l}\t%ds", []>, Requires<[In32BitMode]>;
231def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
232                 "push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
233def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
234                 "push{l}\t%es", []>, Requires<[In32BitMode]>;
235
236def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
237                 "push{w}\t%fs", []>, OpSize, TB;
238def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
239                 "push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
240def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
241                 "push{w}\t%gs", []>, OpSize, TB;
242def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
243                 "push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
244
245def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
246                 "push{q}\t%fs", []>, TB;
247def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
248                 "push{q}\t%gs", []>, TB;
249
250// No "pop cs" instruction.
251def POPSS16 : I<0x17, RawFrm, (outs), (ins),
252                "pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
253def POPSS32 : I<0x17, RawFrm, (outs), (ins),
254                "pop{l}\t%ss", []>        , Requires<[In32BitMode]>;
255
256def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
257                "pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
258def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
259                "pop{l}\t%ds", []>        , Requires<[In32BitMode]>;
260
261def POPES16 : I<0x07, RawFrm, (outs), (ins),
262                "pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
263def POPES32 : I<0x07, RawFrm, (outs), (ins),
264                "pop{l}\t%es", []>        , Requires<[In32BitMode]>;
265
266def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
267                "pop{w}\t%fs", []>, OpSize, TB;
268def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
269                "pop{l}\t%fs", []>, TB    , Requires<[In32BitMode]>;
270def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
271                "pop{q}\t%fs", []>, TB;
272
273def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
274                "pop{w}\t%gs", []>, OpSize, TB;
275def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
276                "pop{l}\t%gs", []>, TB    , Requires<[In32BitMode]>;
277def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
278                "pop{q}\t%gs", []>, TB;
279
280
281def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
282                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
283def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
284                "lds{l}\t{$src, $dst|$dst, $src}", []>;
285
286def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
287                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
288def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
289                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
290def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
291                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
292
293def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
294                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
295def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
296                "les{l}\t{$src, $dst|$dst, $src}", []>;
297
298def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
299                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
300def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
301                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
302def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
303                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
304
305def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
306                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
307def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
308                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
309
310def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
311                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
312
313
314def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
315              "verr\t$seg", []>, TB;
316def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
317              "verr\t$seg", []>, TB;
318def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
319              "verw\t$seg", []>, TB;
320def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
321              "verw\t$seg", []>, TB;
322
323//===----------------------------------------------------------------------===//
324// Descriptor-table support instructions
325
326def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
327              "sgdtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
328def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
329              "sgdt\t$dst", []>, TB;
330def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
331              "sidtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
332def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
333              "sidt\t$dst", []>, TB;
334def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
335                "sldt{w}\t$dst", []>, TB, OpSize;
336def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
337                "sldt{w}\t$dst", []>, TB;
338def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
339                "sldt{l}\t$dst", []>, TB;
340
341// LLDT is not interpreted specially in 64-bit mode because there is no sign
342//   extension.
343def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
344                 "sldt{q}\t$dst", []>, TB;
345def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
346                 "sldt{q}\t$dst", []>, TB;
347
348def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
349              "lgdtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
350def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
351              "lgdt\t$src", []>, TB;
352def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
353              "lidtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
354def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
355              "lidt\t$src", []>, TB;
356def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
357                "lldt{w}\t$src", []>, TB;
358def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
359                "lldt{w}\t$src", []>, TB;
360
361//===----------------------------------------------------------------------===//
362// Specialized register support
363def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
364def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
365def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
366
367def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
368                "smsw{w}\t$dst", []>, OpSize, TB;
369def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
370                "smsw{l}\t$dst", []>, TB;
371// no m form encodable; use SMSW16m
372def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
373                 "smsw{q}\t$dst", []>, TB;
374
375// For memory operands, there is only a 16-bit form
376def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
377                "smsw{w}\t$dst", []>, TB;
378
379def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
380                "lmsw{w}\t$src", []>, TB;
381def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
382                "lmsw{w}\t$src", []>, TB;
383
384def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
385
386//===----------------------------------------------------------------------===//
387// Cache instructions
388def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
389def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
390
391