1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
23
24// CPU flow control instructions
25
26let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41def : Pat<(debugtrap),
42          (INT3)>;
43
44// The long form of "int $3" turns into int3 as a size optimization.
45// FIXME: This doesn't work because InstAlias can't match immediate constants.
46//def : InstAlias<"int\t$3", (INT3)>;
47
48let SchedRW = [WriteSystem] in {
49
50def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
51              [(int_x86_int imm:$trap)], IIC_INT>;
52
53
54def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
55def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
56def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
57               Requires<[In64BitMode]>;
58
59def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61
62def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
63                 IIC_SYS_ENTER_EXIT>, TB;
64def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
65                Requires<[In64BitMode]>;
66
67def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16;
68def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
69             OpSize32;
70def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
71             Requires<[In64BitMode]>;
72} // SchedRW
73
74
75//===----------------------------------------------------------------------===//
76//  Input/Output Instructions.
77//
78let SchedRW = [WriteSystem] in {
79let Defs = [AL], Uses = [DX] in
80def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
81               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
82let Defs = [AX], Uses = [DX] in
83def IN16rr : I<0xED, RawFrm, (outs), (ins),
84               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
85let Defs = [EAX], Uses = [DX] in
86def IN32rr : I<0xED, RawFrm, (outs), (ins),
87               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
88
89let Defs = [AL] in
90def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
91                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
92let Defs = [AX] in
93def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
94                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
95let Defs = [EAX] in
96def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
97                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
98
99let Uses = [DX, AL] in
100def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
101                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
102let Uses = [DX, AX] in
103def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
104                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
105let Uses = [DX, EAX] in
106def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
107                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
108
109let Uses = [AL] in
110def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
111                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
112let Uses = [AX] in
113def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
114                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
115let Uses = [EAX] in
116def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
117                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
118
119def IN8  : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
120             "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
121def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
122             "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>,  OpSize16;
123def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
124             "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
125} // SchedRW
126
127//===----------------------------------------------------------------------===//
128// Moves to and from debug registers
129
130let SchedRW = [WriteSystem] in {
131def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
132                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
133                Requires<[Not64BitMode]>;
134def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
135                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
136                Requires<[In64BitMode]>;
137
138def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
139                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
140                Requires<[Not64BitMode]>;
141def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
142                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
143                Requires<[In64BitMode]>;
144} // SchedRW
145
146//===----------------------------------------------------------------------===//
147// Moves to and from control registers
148
149let SchedRW = [WriteSystem] in {
150def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
151                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
152                Requires<[Not64BitMode]>;
153def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
154                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
155                Requires<[In64BitMode]>;
156
157def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
158                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
159                Requires<[Not64BitMode]>;
160def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
161                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
162                Requires<[In64BitMode]>;
163} // SchedRW
164
165//===----------------------------------------------------------------------===//
166// Segment override instruction prefixes
167
168def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
169def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
170def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
171def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
172def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
173def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
174
175
176//===----------------------------------------------------------------------===//
177// Moves to and from segment registers.
178//
179
180let SchedRW = [WriteMove] in {
181def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
182                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
183def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
184                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
185def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
186                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
187
188def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
189                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
190def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
191                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
192def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
193                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
194
195def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
196                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
197def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
198                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
199def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
200                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
201
202def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
203                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
204def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
205                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
206def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
207                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
208} // SchedRW
209
210//===----------------------------------------------------------------------===//
211// Segmentation support instructions.
212
213let SchedRW = [WriteSystem] in {
214def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
215
216def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
217                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
218                OpSize16;
219def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
220                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
221                OpSize16;
222
223// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
224def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
225                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
226                OpSize32;
227def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
228                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
229                OpSize32;
230// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
231def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
232                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
233def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
234                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
235
236def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
237                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
238                OpSize16;
239def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
240                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
241                OpSize16;
242def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
243                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
244                OpSize32;
245def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
246                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
247                OpSize32;
248def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
249                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
250def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
251                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
252
253def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
254               [], IIC_INVLPG>, TB;
255
256def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
257               "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
258def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
259               "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
260def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
261                "str{q}\t$dst", [], IIC_STR>, TB;
262def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
263               "str{w}\t$dst", [], IIC_STR>, TB;
264
265def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
266             "ltr{w}\t$src", [], IIC_LTR>, TB;
267def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
268             "ltr{w}\t$src", [], IIC_LTR>, TB;
269
270def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
271                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
272                 OpSize16, Requires<[Not64BitMode]>;
273def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
274                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
275                 OpSize32, Requires<[Not64BitMode]>;
276def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
277                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
278                 OpSize16, Requires<[Not64BitMode]>;
279def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
280                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
281                 OpSize32, Requires<[Not64BitMode]>;
282def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
283                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
284                 OpSize16, Requires<[Not64BitMode]>;
285def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
286                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
287                 OpSize32, Requires<[Not64BitMode]>;
288def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
289                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
290                 OpSize16, Requires<[Not64BitMode]>;
291def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
292                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
293                 OpSize32, Requires<[Not64BitMode]>;
294def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
295                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
296def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
297                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
298               OpSize32, Requires<[Not64BitMode]>;
299def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
300                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
301def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
302                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
303               OpSize32, Requires<[Not64BitMode]>;
304def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
305                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
306               OpSize32, Requires<[In64BitMode]>;
307def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
308                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
309               OpSize32, Requires<[In64BitMode]>;
310
311// No "pop cs" instruction.
312def POPSS16 : I<0x17, RawFrm, (outs), (ins),
313                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
314              OpSize16, Requires<[Not64BitMode]>;
315def POPSS32 : I<0x17, RawFrm, (outs), (ins),
316                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
317              OpSize32, Requires<[Not64BitMode]>;
318
319def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
320                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
321              OpSize16, Requires<[Not64BitMode]>;
322def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
323                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
324              OpSize32, Requires<[Not64BitMode]>;
325
326def POPES16 : I<0x07, RawFrm, (outs), (ins),
327                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
328              OpSize16, Requires<[Not64BitMode]>;
329def POPES32 : I<0x07, RawFrm, (outs), (ins),
330                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
331              OpSize32, Requires<[Not64BitMode]>;
332
333def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
334                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
335def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
336                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
337              OpSize32, Requires<[Not64BitMode]>;
338def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
339                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
340              OpSize32, Requires<[In64BitMode]>;
341
342def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
343                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
344def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
345                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
346              OpSize32, Requires<[Not64BitMode]>;
347def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
348                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
349              OpSize32, Requires<[In64BitMode]>;
350
351
352def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
353                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
354def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
355                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
356
357def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
358                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
359def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
360                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
361def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
362                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
363
364def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
365                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
366def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
367                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
368
369def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
370                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
371def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
372                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
373def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
374                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
375
376def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
377                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
378def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
379                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
380
381def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
382                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
383
384
385def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
386              "verr\t$seg", [], IIC_VERR>, TB;
387def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
388              "verr\t$seg", [], IIC_VERR>, TB;
389def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
390              "verw\t$seg", [], IIC_VERW_MEM>, TB;
391def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
392              "verw\t$seg", [], IIC_VERW_REG>, TB;
393} // SchedRW
394
395//===----------------------------------------------------------------------===//
396// Descriptor-table support instructions
397
398let SchedRW = [WriteSystem] in {
399def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
400              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
401def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
402              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
403def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
404              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
405def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
406              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
407def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
408              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
409def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
410              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
411def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
412                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
413def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
414                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
415def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
416                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
417
418// LLDT is not interpreted specially in 64-bit mode because there is no sign
419//   extension.
420def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
421                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
422def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
423                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
424
425def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
426              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
427def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
428              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
429def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
430              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
431def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
432              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
433def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
434              "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
435def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
436              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
437def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
438                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
439def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
440                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
441} // SchedRW
442
443//===----------------------------------------------------------------------===//
444// Specialized register support
445let SchedRW = [WriteSystem] in {
446def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
447def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
448def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
449
450def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
451                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
452def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
453                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
454// no m form encodable; use SMSW16m
455def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
456                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
457
458// For memory operands, there is only a 16-bit form
459def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
460                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
461
462def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
463                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
464def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
465                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
466
467let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
468  def CPUID32 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
469  Requires<[Not64BitMode]>;
470let Defs = [RAX, RBX, RCX, RDX], Uses = [RAX, RCX] in
471  def CPUID64 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
472  Requires<[In64BitMode]>;
473} // SchedRW
474
475//===----------------------------------------------------------------------===//
476// Cache instructions
477let SchedRW = [WriteSystem] in {
478def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
479def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
480} // SchedRW
481
482//===----------------------------------------------------------------------===//
483// XSAVE instructions
484let SchedRW = [WriteSystem] in {
485let Defs = [RDX, RAX], Uses = [RCX] in
486  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
487
488let Uses = [RDX, RAX, RCX] in
489  def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
490
491let Uses = [RDX, RAX] in {
492  def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
493               "xsave\t$dst", []>, TB;
494  def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
495                 "xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
496  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
497               "xrstor\t$dst", []>, TB;
498  def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
499                 "xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
500  def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
501                  "xsaveopt\t$dst", []>, TB;
502  def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
503                    "xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
504}
505} // SchedRW
506
507//===----------------------------------------------------------------------===//
508// VIA PadLock crypto instructions
509let Defs = [RAX, RDI], Uses = [RDX, RDI] in
510  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
511
512def : InstAlias<"xstorerng", (XSTORE)>;
513
514let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
515  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
516  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
517  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
518  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
519  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
520}
521
522let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
523  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
524  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
525}
526let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
527  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
528
529//===----------------------------------------------------------------------===//
530// FS/GS Base Instructions
531let Predicates = [HasFSGSBase, In64BitMode] in {
532  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
533                   "rdfsbase{l}\t$dst",
534                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
535  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
536                     "rdfsbase{q}\t$dst",
537                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
538  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
539                   "rdgsbase{l}\t$dst",
540                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
541  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
542                     "rdgsbase{q}\t$dst",
543                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
544  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
545                   "wrfsbase{l}\t$src",
546                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
547  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
548                      "wrfsbase{q}\t$src",
549                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
550  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
551                   "wrgsbase{l}\t$src",
552                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
553  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
554                      "wrgsbase{q}\t$src",
555                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
556}
557
558//===----------------------------------------------------------------------===//
559// INVPCID Instruction
560def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
561                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
562                Requires<[Not64BitMode]>;
563def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
564                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
565                Requires<[In64BitMode]>;
566
567//===----------------------------------------------------------------------===//
568// SMAP Instruction
569let Defs = [EFLAGS], Uses = [EFLAGS] in {
570  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
571  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
572}
573