1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
23
24// CPU flow control instructions
25
26let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41def : Pat<(debugtrap),
42          (INT3)>;
43
44// The long form of "int $3" turns into int3 as a size optimization.
45// FIXME: This doesn't work because InstAlias can't match immediate constants.
46//def : InstAlias<"int\t$3", (INT3)>;
47
48let SchedRW = [WriteSystem] in {
49
50def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
51              [(int_x86_int imm:$trap)], IIC_INT>;
52
53
54def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
55def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
56def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
57               Requires<[In64BitMode]>;
58
59def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61
62def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
63                 IIC_SYS_ENTER_EXIT>, TB;
64def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
65                Requires<[In64BitMode]>;
66
67def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
68def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
69             OpSize16;
70def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
71             Requires<[In64BitMode]>;
72} // SchedRW
73
74
75//===----------------------------------------------------------------------===//
76//  Input/Output Instructions.
77//
78let SchedRW = [WriteSystem] in {
79let Defs = [AL], Uses = [DX] in
80def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
81               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
82let Defs = [AX], Uses = [DX] in
83def IN16rr : I<0xED, RawFrm, (outs), (ins),
84               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize;
85let Defs = [EAX], Uses = [DX] in
86def IN32rr : I<0xED, RawFrm, (outs), (ins),
87               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize16;
88
89let Defs = [AL] in
90def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
91                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
92let Defs = [AX] in
93def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
94                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
95let Defs = [EAX] in
96def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
97                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize16;
98
99let Uses = [DX, AL] in
100def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
101                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
102let Uses = [DX, AX] in
103def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
104                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
105let Uses = [DX, EAX] in
106def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
107                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize16;
108
109let Uses = [AL] in
110def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
111                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
112let Uses = [AX] in
113def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
114                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
115let Uses = [EAX] in
116def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
117                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
118
119def IN8  : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
120             "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
121def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
122             "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>,  OpSize;
123def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
124             "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
125} // SchedRW
126
127//===----------------------------------------------------------------------===//
128// Moves to and from debug registers
129
130let SchedRW = [WriteSystem] in {
131def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
132                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
133                Requires<[Not64BitMode]>;
134def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
135                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
136                Requires<[In64BitMode]>;
137
138def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
139                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
140                Requires<[Not64BitMode]>;
141def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
142                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
143                Requires<[In64BitMode]>;
144} // SchedRW
145
146//===----------------------------------------------------------------------===//
147// Moves to and from control registers
148
149let SchedRW = [WriteSystem] in {
150def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
151                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
152                Requires<[Not64BitMode]>;
153def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
154                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
155                Requires<[In64BitMode]>;
156
157def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
158                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
159                Requires<[Not64BitMode]>;
160def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
161                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
162                Requires<[In64BitMode]>;
163} // SchedRW
164
165//===----------------------------------------------------------------------===//
166// Segment override instruction prefixes
167
168def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
169def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
170def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
171def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
172def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
173def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
174
175
176//===----------------------------------------------------------------------===//
177// Moves to and from segment registers.
178//
179
180let SchedRW = [WriteMove] in {
181def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
182                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
183def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
184                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
185def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
186                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
187
188def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
189                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
190def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
191                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
192def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
193                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
194
195def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
196                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
197def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
198                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
199def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
200                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
201
202def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
203                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
204def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
205                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
206def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
207                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
208} // SchedRW
209
210//===----------------------------------------------------------------------===//
211// Segmentation support instructions.
212
213let SchedRW = [WriteSystem] in {
214def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
215
216def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
217                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize;
218def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
219                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize;
220
221// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
222def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
223                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
224                OpSize16;
225def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
226                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
227                OpSize16;
228// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
229def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
230                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
231def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
232                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
233
234def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
235                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize;
236def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
237                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
238def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
239                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
240                OpSize16;
241def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
242                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
243                OpSize16;
244def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
245                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
246def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
247                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
248
249def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
250               [], IIC_INVLPG>, TB;
251
252def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
253               "str{w}\t$dst", [], IIC_STR>, TB, OpSize;
254def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
255               "str{l}\t$dst", [], IIC_STR>, TB, OpSize16;
256def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
257                "str{q}\t$dst", [], IIC_STR>, TB;
258def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
259               "str{w}\t$dst", [], IIC_STR>, TB;
260
261def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
262             "ltr{w}\t$src", [], IIC_LTR>, TB;
263def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
264             "ltr{w}\t$src", [], IIC_LTR>, TB;
265
266def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
267                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
268                 OpSize, Requires<[Not64BitMode]>;
269def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
270                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
271                 OpSize16, Requires<[Not64BitMode]>;
272def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
273                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
274                 OpSize, Requires<[Not64BitMode]>;
275def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
276                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
277                 OpSize16, Requires<[Not64BitMode]>;
278def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
279                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
280                 OpSize, Requires<[Not64BitMode]>;
281def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
282                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
283                 OpSize16, Requires<[Not64BitMode]>;
284def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
285                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
286                 OpSize, Requires<[Not64BitMode]>;
287def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
288                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
289                 OpSize16, Requires<[Not64BitMode]>;
290def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
291                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
292def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
293                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
294               OpSize16, Requires<[Not64BitMode]>;
295def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
296                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
297def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
298                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
299               OpSize16, Requires<[Not64BitMode]>;
300def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
301                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
302def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
303                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
304
305// No "pop cs" instruction.
306def POPSS16 : I<0x17, RawFrm, (outs), (ins),
307                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
308              OpSize, Requires<[Not64BitMode]>;
309def POPSS32 : I<0x17, RawFrm, (outs), (ins),
310                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
311              OpSize16, Requires<[Not64BitMode]>;
312
313def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
314                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
315              OpSize, Requires<[Not64BitMode]>;
316def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
317                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
318              OpSize16, Requires<[Not64BitMode]>;
319
320def POPES16 : I<0x07, RawFrm, (outs), (ins),
321                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
322              OpSize, Requires<[Not64BitMode]>;
323def POPES32 : I<0x07, RawFrm, (outs), (ins),
324                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
325              OpSize16, Requires<[Not64BitMode]>;
326
327def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
328                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
329def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
330                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
331              OpSize16, Requires<[Not64BitMode]>;
332def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
333                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
334
335def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
336                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
337def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
338                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
339              OpSize16, Requires<[Not64BitMode]>;
340def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
341                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
342
343
344def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
345                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
346def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
347                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
348
349def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
350                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
351def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
352                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
353def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
354                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
355
356def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
357                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
358def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
359                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
360
361def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
362                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
363def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
364                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
365def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
366                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
367
368def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
369                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
370def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
371                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
372
373def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
374                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
375
376
377def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
378              "verr\t$seg", [], IIC_VERR>, TB;
379def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
380              "verr\t$seg", [], IIC_VERR>, TB;
381def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
382              "verw\t$seg", [], IIC_VERW_MEM>, TB;
383def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
384              "verw\t$seg", [], IIC_VERW_REG>, TB;
385} // SchedRW
386
387//===----------------------------------------------------------------------===//
388// Descriptor-table support instructions
389
390let SchedRW = [WriteSystem] in {
391def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
392              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[Not64BitMode]>;
393def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
394              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize16, TB, Requires <[Not64BitMode]>;
395def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
396              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
397def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
398              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[Not64BitMode]>;
399def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
400              "sidt{l}\t$dst", []>, OpSize16, TB, Requires <[Not64BitMode]>;
401def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
402              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
403def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
404                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
405def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
406                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
407def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
408                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize16, TB;
409
410// LLDT is not interpreted specially in 64-bit mode because there is no sign
411//   extension.
412def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
413                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
414def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
415                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
416
417def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
418              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[Not64BitMode]>;
419def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
420              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize16, TB, Requires<[Not64BitMode]>;
421def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
422              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
423def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
424              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[Not64BitMode]>;
425def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
426              "lidt{l}\t$src", [], IIC_LIDT>, OpSize16, TB, Requires<[Not64BitMode]>;
427def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
428              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
429def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
430                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
431def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
432                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
433} // SchedRW
434
435//===----------------------------------------------------------------------===//
436// Specialized register support
437let SchedRW = [WriteSystem] in {
438def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
439def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
440def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
441
442def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
443                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
444def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
445                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize16, TB;
446// no m form encodable; use SMSW16m
447def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
448                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
449
450// For memory operands, there is only a 16-bit form
451def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
452                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
453
454def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
455                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
456def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
457                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
458
459let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
460  def CPUID32 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
461  Requires<[Not64BitMode]>;
462let Defs = [RAX, RBX, RCX, RDX], Uses = [RAX, RCX] in
463  def CPUID64 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
464  Requires<[In64BitMode]>;
465} // SchedRW
466
467//===----------------------------------------------------------------------===//
468// Cache instructions
469let SchedRW = [WriteSystem] in {
470def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
471def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
472} // SchedRW
473
474//===----------------------------------------------------------------------===//
475// XSAVE instructions
476let SchedRW = [WriteSystem] in {
477let Defs = [RDX, RAX], Uses = [RCX] in
478  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
479
480let Uses = [RDX, RAX, RCX] in
481  def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
482
483let Uses = [RDX, RAX] in {
484  def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
485               "xsave\t$dst", []>, TB;
486  def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
487                 "xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
488  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
489               "xrstor\t$dst", []>, TB;
490  def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
491                 "xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
492  def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
493                  "xsaveopt\t$dst", []>, TB;
494  def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
495                    "xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
496}
497} // SchedRW
498
499//===----------------------------------------------------------------------===//
500// VIA PadLock crypto instructions
501let Defs = [RAX, RDI], Uses = [RDX, RDI] in
502  def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
503
504def : InstAlias<"xstorerng", (XSTORE)>;
505
506let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
507  def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
508  def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
509  def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
510  def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
511  def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
512}
513
514let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
515  def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
516  def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
517}
518let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
519  def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
520
521//===----------------------------------------------------------------------===//
522// FS/GS Base Instructions
523let Predicates = [HasFSGSBase, In64BitMode] in {
524  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
525                   "rdfsbase{l}\t$dst",
526                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
527  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
528                     "rdfsbase{q}\t$dst",
529                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
530  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
531                   "rdgsbase{l}\t$dst",
532                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
533  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
534                     "rdgsbase{q}\t$dst",
535                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
536  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
537                   "wrfsbase{l}\t$src",
538                   [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
539  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
540                      "wrfsbase{q}\t$src",
541                      [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
542  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
543                   "wrgsbase{l}\t$src",
544                   [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
545  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
546                      "wrgsbase{q}\t$src",
547                      [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
548}
549
550//===----------------------------------------------------------------------===//
551// INVPCID Instruction
552def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
553                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
554                Requires<[Not64BitMode]>;
555def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
556                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
557                Requires<[In64BitMode]>;
558
559//===----------------------------------------------------------------------===//
560// SMAP Instruction
561let Defs = [EFLAGS], Uses = [EFLAGS] in {
562  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
563  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
564}
565