1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
23
24// CPU flow control instructions
25
26let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41// The long form of "int $3" turns into int3 as a size optimization.
42// FIXME: This doesn't work because InstAlias can't match immediate constants.
43//def : InstAlias<"int\t$3", (INT3)>;
44
45let SchedRW = [WriteSystem] in {
46
47def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
48              [(int_x86_int imm:$trap)], IIC_INT>;
49
50
51def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
52def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
53def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
54               Requires<[In64BitMode]>;
55
56def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
57                 IIC_SYS_ENTER_EXIT>, TB;
58
59def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
62                 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
63} // SchedRW
64
65def : Pat<(debugtrap),
66          (INT3)>, Requires<[NotPS4]>;
67def : Pat<(debugtrap),
68          (INT (i8 0x41))>, Requires<[IsPS4]>;
69
70//===----------------------------------------------------------------------===//
71//  Input/Output Instructions.
72//
73let SchedRW = [WriteSystem] in {
74let Defs = [AL], Uses = [DX] in
75def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
76               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
77let Defs = [AX], Uses = [DX] in
78def IN16rr : I<0xED, RawFrm, (outs), (ins),
79               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
80let Defs = [EAX], Uses = [DX] in
81def IN32rr : I<0xED, RawFrm, (outs), (ins),
82               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
83
84let Defs = [AL] in
85def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
86                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
87let Defs = [AX] in
88def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
89                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
90let Defs = [EAX] in
91def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
92                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
93
94let Uses = [DX, AL] in
95def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
96                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
97let Uses = [DX, AX] in
98def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
99                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
100let Uses = [DX, EAX] in
101def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
102                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
103
104let Uses = [AL] in
105def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
106                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
107let Uses = [AX] in
108def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
109                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
110let Uses = [EAX] in
111def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
112                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
113
114} // SchedRW
115
116//===----------------------------------------------------------------------===//
117// Moves to and from debug registers
118
119let SchedRW = [WriteSystem] in {
120def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
121                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
122                Requires<[Not64BitMode]>;
123def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
124                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
125                Requires<[In64BitMode]>;
126
127def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
128                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
129                Requires<[Not64BitMode]>;
130def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
131                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
132                Requires<[In64BitMode]>;
133} // SchedRW
134
135//===----------------------------------------------------------------------===//
136// Moves to and from control registers
137
138let SchedRW = [WriteSystem] in {
139def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
140                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
141                Requires<[Not64BitMode]>;
142def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
143                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
144                Requires<[In64BitMode]>;
145
146def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
147                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
148                Requires<[Not64BitMode]>;
149def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
150                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
151                Requires<[In64BitMode]>;
152} // SchedRW
153
154//===----------------------------------------------------------------------===//
155// Segment override instruction prefixes
156
157let SchedRW = [WriteNop] in {
158def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", [], IIC_NOP>;
159def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", [], IIC_NOP>;
160def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", [], IIC_NOP>;
161def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", [], IIC_NOP>;
162def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", [], IIC_NOP>;
163def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", [], IIC_NOP>;
164} // SchedRW
165
166//===----------------------------------------------------------------------===//
167// Moves to and from segment registers.
168//
169
170let SchedRW = [WriteMove] in {
171def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
172                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
173def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
174                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
175def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
176                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
177let mayStore = 1 in {
178def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
179                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore;
180}
181def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
182                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
183def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
184                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
185def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
186                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
187let mayLoad = 1 in {
188def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
189                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore;
190}
191} // SchedRW
192
193//===----------------------------------------------------------------------===//
194// Segmentation support instructions.
195
196let SchedRW = [WriteSystem] in {
197def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
198
199let mayLoad = 1 in
200def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
201                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
202                OpSize16;
203def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
204                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
205                OpSize16;
206
207// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
208let mayLoad = 1 in
209def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
210                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
211                OpSize32;
212def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
213                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
214                OpSize32;
215// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
216let mayLoad = 1 in
217def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
218                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
219def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
220                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
221
222let mayLoad = 1 in
223def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
224                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
225                OpSize16;
226def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
227                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
228                OpSize16;
229let mayLoad = 1 in
230def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
231                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
232                OpSize32;
233def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
234                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
235                OpSize32;
236let mayLoad = 1 in
237def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
238                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
239def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
240                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
241
242def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
243               [], IIC_INVLPG>, TB;
244
245def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
246               "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
247def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
248               "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
249def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
250                "str{q}\t$dst", [], IIC_STR>, TB;
251let mayStore = 1 in
252def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
253               "str{w}\t$dst", [], IIC_STR>, TB;
254
255def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
256             "ltr{w}\t$src", [], IIC_LTR>, TB;
257let mayLoad = 1 in
258def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
259             "ltr{w}\t$src", [], IIC_LTR>, TB;
260
261def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
262                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
263                 OpSize16, Requires<[Not64BitMode]>;
264def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
265                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
266                 OpSize32, Requires<[Not64BitMode]>;
267def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
268                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
269                 OpSize16, Requires<[Not64BitMode]>;
270def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
271                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
272                 OpSize32, Requires<[Not64BitMode]>;
273def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
274                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
275                 OpSize16, Requires<[Not64BitMode]>;
276def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
277                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
278                 OpSize32, Requires<[Not64BitMode]>;
279def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
280                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
281                 OpSize16, Requires<[Not64BitMode]>;
282def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
283                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
284                 OpSize32, Requires<[Not64BitMode]>;
285def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
286                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
287def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
288                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
289               OpSize32, Requires<[Not64BitMode]>;
290def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
291                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
292def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
293                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
294               OpSize32, Requires<[Not64BitMode]>;
295def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
296                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
297               OpSize32, Requires<[In64BitMode]>;
298def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
299                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
300               OpSize32, Requires<[In64BitMode]>;
301
302// No "pop cs" instruction.
303def POPSS16 : I<0x17, RawFrm, (outs), (ins),
304                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
305              OpSize16, Requires<[Not64BitMode]>;
306def POPSS32 : I<0x17, RawFrm, (outs), (ins),
307                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
308              OpSize32, Requires<[Not64BitMode]>;
309
310def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
311                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
312              OpSize16, Requires<[Not64BitMode]>;
313def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
314                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
315              OpSize32, Requires<[Not64BitMode]>;
316
317def POPES16 : I<0x07, RawFrm, (outs), (ins),
318                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
319              OpSize16, Requires<[Not64BitMode]>;
320def POPES32 : I<0x07, RawFrm, (outs), (ins),
321                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
322              OpSize32, Requires<[Not64BitMode]>;
323
324def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
325                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
326def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
327                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
328              OpSize32, Requires<[Not64BitMode]>;
329def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
330                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
331              OpSize32, Requires<[In64BitMode]>;
332
333def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
334                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
335def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
336                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
337              OpSize32, Requires<[Not64BitMode]>;
338def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
339                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
340              OpSize32, Requires<[In64BitMode]>;
341
342
343def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
344                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
345                Requires<[Not64BitMode]>;
346def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
347                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
348                Requires<[Not64BitMode]>;
349
350def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
351                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
352def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
353                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
354def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
355                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
356
357def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
358                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
359                Requires<[Not64BitMode]>;
360def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
361                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
362                Requires<[Not64BitMode]>;
363
364def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
365                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
366def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
367                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
368def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
369                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
370
371def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
372                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
373def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
374                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
375
376def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
377                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
378
379
380def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
381              "verr\t$seg", [], IIC_VERR>, TB;
382def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
383              "verw\t$seg", [], IIC_VERW_MEM>, TB;
384let mayLoad = 1 in {
385def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
386              "verr\t$seg", [], IIC_VERR>, TB;
387def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
388              "verw\t$seg", [], IIC_VERW_REG>, TB;
389}
390} // SchedRW
391
392//===----------------------------------------------------------------------===//
393// Descriptor-table support instructions
394
395let SchedRW = [WriteSystem] in {
396def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
397              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
398def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
399              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
400def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
401              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
402def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
403              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
404def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
405              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
406def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
407              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
408def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
409                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
410let mayStore = 1 in
411def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
412                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
413def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
414                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
415
416// LLDT is not interpreted specially in 64-bit mode because there is no sign
417//   extension.
418def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
419                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
420let mayStore = 1 in
421def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
422                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
423
424def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
425              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
426def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
427              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
428def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
429              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
430def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
431              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
432def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
433              "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
434def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
435              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
436def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
437                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
438let mayLoad = 1 in
439def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
440                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
441} // SchedRW
442
443//===----------------------------------------------------------------------===//
444// Specialized register support
445let SchedRW = [WriteSystem] in {
446let Uses = [EAX, ECX, EDX] in
447def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
448let Defs = [EAX, EDX], Uses = [ECX] in
449def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
450
451let Defs = [RAX, RDX], Uses = [ECX] in
452  def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
453              TB;
454
455def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
456                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
457def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
458                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
459// no m form encodable; use SMSW16m
460def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
461                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
462
463// For memory operands, there is only a 16-bit form
464def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
465                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
466
467def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
468                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
469let mayLoad = 1 in
470def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
471                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
472
473let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
474  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
475} // SchedRW
476
477//===----------------------------------------------------------------------===//
478// Cache instructions
479let SchedRW = [WriteSystem] in {
480def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
481def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
482} // SchedRW
483
484//===----------------------------------------------------------------------===//
485// CET instructions
486let SchedRW = [WriteSystem], Predicates = [HasSHSTK]  in{
487  let Uses = [SSP] in {
488    let Defs = [SSP] in {
489      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
490                       [(int_x86_incsspd GR32:$src)]>, XS;
491      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
492                       [(int_x86_incsspq GR64:$src)]>, XS,
493                       Requires<[In64BitMode]>;
494    } // Defs SSP
495
496    let Constraints = "$src = $dst" in {
497      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
498                     "rdsspd\t$dst",
499                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
500      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
501                     "rdsspq\t$dst",
502                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS,
503                     Requires<[In64BitMode]>;
504    }
505
506    let Defs = [SSP] in {
507      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
508                       [(int_x86_saveprevssp)]>, XS;
509      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
510                       "rstorssp\t$src",
511                       [(int_x86_rstorssp addr:$src)]>, XS;
512    } // Defs SSP
513  } // Uses SSP
514
515  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
516                "wrssd\t{$src, $dst|$dst, $src}",
517                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8;
518  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
519                 "wrssq\t{$src, $dst|$dst, $src}",
520                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8,
521                 Requires<[In64BitMode]>;
522  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
523                 "wrussd\t{$src, $dst|$dst, $src}",
524                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
525  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
526                  "wrussq\t{$src, $dst|$dst, $src}",
527                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD,
528                  Requires<[In64BitMode]>;
529
530  let Defs = [SSP] in {
531    let Uses = [SSP] in {
532        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
533                         [(int_x86_setssbsy)]>, XS;
534    } // Uses SSP
535
536    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
537                     "clrssbsy\t$src",
538                     [(int_x86_clrssbsy addr:$src)]>, XS;
539  } // Defs SSP
540} // SchedRW && HasSHSTK
541
542//===----------------------------------------------------------------------===//
543// XSAVE instructions
544let SchedRW = [WriteSystem] in {
545let Predicates = [HasXSAVE] in {
546let Defs = [EDX, EAX], Uses = [ECX] in
547  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
548
549let Uses = [EDX, EAX, ECX] in
550  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
551                "xsetbv",
552                [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
553
554} // HasXSAVE
555
556let Uses = [EDX, EAX] in {
557let Predicates = [HasXSAVE] in {
558  def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
559                "xsave\t$dst",
560                [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS;
561  def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
562                   "xsave64\t$dst",
563                   [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
564  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
565                 "xrstor\t$dst",
566                 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS;
567  def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
568                    "xrstor64\t$dst",
569                    [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
570}
571let Predicates = [HasXSAVEOPT] in {
572  def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
573                   "xsaveopt\t$dst",
574                   [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS;
575  def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
576                      "xsaveopt64\t$dst",
577                      [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
578}
579let Predicates = [HasXSAVEC] in {
580  def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
581                 "xsavec\t$dst",
582                 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB;
583  def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
584                   "xsavec64\t$dst",
585                   [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
586}
587let Predicates = [HasXSAVES] in {
588  def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
589                 "xsaves\t$dst",
590                 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB;
591  def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
592                    "xsaves64\t$dst",
593                    [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
594  def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
595                  "xrstors\t$dst",
596                  [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB;
597  def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
598                     "xrstors64\t$dst",
599                     [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
600}
601} // Uses
602} // SchedRW
603
604//===----------------------------------------------------------------------===//
605// VIA PadLock crypto instructions
606let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
607  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
608
609def : InstAlias<"xstorerng", (XSTORE)>;
610
611let SchedRW = [WriteSystem] in {
612let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
613  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
614  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
615  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
616  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
617  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
618}
619
620let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
621  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
622  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
623}
624let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
625  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
626} // SchedRW
627
628//==-----------------------------------------------------------------------===//
629// PKU  - enable protection key
630let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
631  def WRPKRU : PseudoI<(outs), (ins GR32:$src),
632                [(int_x86_wrpkru GR32:$src)]>;
633  def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
634                [(set GR32:$dst, (int_x86_rdpkru))]>;
635}
636
637let SchedRW = [WriteSystem] in {
638let Defs = [EAX, EDX], Uses = [ECX] in
639  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", [], IIC_PKU>, TB;
640let Uses = [EAX, ECX, EDX] in
641  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", [], IIC_PKU>, TB;
642} // SchedRW
643
644//===----------------------------------------------------------------------===//
645// FS/GS Base Instructions
646let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
647  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
648                   "rdfsbase{l}\t$dst",
649                   [(set GR32:$dst, (int_x86_rdfsbase_32))],
650                   IIC_SEGMENT_BASE_R>, XS;
651  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
652                     "rdfsbase{q}\t$dst",
653                     [(set GR64:$dst, (int_x86_rdfsbase_64))],
654                     IIC_SEGMENT_BASE_R>, XS;
655  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
656                   "rdgsbase{l}\t$dst",
657                   [(set GR32:$dst, (int_x86_rdgsbase_32))],
658                   IIC_SEGMENT_BASE_R>, XS;
659  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
660                     "rdgsbase{q}\t$dst",
661                     [(set GR64:$dst, (int_x86_rdgsbase_64))],
662                     IIC_SEGMENT_BASE_R>, XS;
663  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
664                   "wrfsbase{l}\t$src",
665                   [(int_x86_wrfsbase_32 GR32:$src)],
666                   IIC_SEGMENT_BASE_W>, XS;
667  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
668                      "wrfsbase{q}\t$src",
669                      [(int_x86_wrfsbase_64 GR64:$src)],
670                      IIC_SEGMENT_BASE_W>, XS;
671  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
672                   "wrgsbase{l}\t$src",
673                   [(int_x86_wrgsbase_32 GR32:$src)], IIC_SEGMENT_BASE_W>, XS;
674  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
675                      "wrgsbase{q}\t$src",
676                      [(int_x86_wrgsbase_64 GR64:$src)],
677                      IIC_SEGMENT_BASE_W>, XS;
678}
679
680//===----------------------------------------------------------------------===//
681// INVPCID Instruction
682let SchedRW = [WriteSystem] in {
683def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
684                "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
685                Requires<[Not64BitMode]>;
686def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
687                "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
688                Requires<[In64BitMode]>;
689} // SchedRW
690
691//===----------------------------------------------------------------------===//
692// SMAP Instruction
693let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
694  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", [], IIC_SMAP>, TB;
695  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", [], IIC_SMAP>, TB;
696}
697
698//===----------------------------------------------------------------------===//
699// SMX Instruction
700let SchedRW = [WriteSystem] in {
701let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
702  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", [], IIC_SMX>, TB;
703} // Uses, Defs
704} // SchedRW
705
706//===----------------------------------------------------------------------===//
707// RDPID Instruction
708let SchedRW = [WriteSystem] in {
709def RDPID32 : I<0xC7, MRM7r, (outs GR32:$src), (ins),
710              "rdpid\t$src", [], IIC_RDPID>, XS,
711              Requires<[Not64BitMode]>;
712def RDPID64 : I<0xC7, MRM7r, (outs GR64:$src), (ins),
713              "rdpid\t$src", [], IIC_RDPID>, XS,
714              Requires<[In64BitMode]>;
715} // SchedRW
716
717//===----------------------------------------------------------------------===//
718// PTWRITE Instruction
719let SchedRW = [WriteSystem] in {
720
721def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
722                "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
723def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
724                    "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
725                    Requires<[In64BitMode]>;
726
727def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
728                 "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
729def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
730                    "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
731                    Requires<[In64BitMode]>;
732} // SchedRW
733