1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instructions that are generally used in
10// privileged modes.  These are not typically used by the compiler, but are
11// supported for the assembler and disassembler.
12//
13//===----------------------------------------------------------------------===//
14
15let SchedRW = [WriteSystem] in {
16let Defs = [RAX, RDX] in
17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26
27  def UD1Wm   : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
28                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
29  def UD1Lm   : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
30                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
31  def UD1Qm   : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
32                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
33
34  def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
35                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
36  def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
37                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
38  def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
39                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
40}
41
42def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
43def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
44
45// Interrupt and SysCall Instructions.
46let Uses = [EFLAGS] in
47  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
48
49def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
50} // SchedRW
51
52// The long form of "int $3" turns into int3 as a size optimization.
53// FIXME: This doesn't work because InstAlias can't match immediate constants.
54//def : InstAlias<"int\t$3", (INT3)>;
55
56let SchedRW = [WriteSystem] in {
57
58def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
59              [(int_x86_int timm:$trap)]>;
60
61
62def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
63def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
64def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
65               Requires<[In64BitMode]>;
66
67def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
68
69def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
70def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
71                  Requires<[In64BitMode]>;
72} // SchedRW
73
74def : Pat<(debugtrap),
75          (INT3)>, Requires<[NotPS4]>;
76def : Pat<(debugtrap),
77          (INT (i8 0x41))>, Requires<[IsPS4]>;
78
79//===----------------------------------------------------------------------===//
80//  Input/Output Instructions.
81//
82let SchedRW = [WriteSystem] in {
83let Defs = [AL], Uses = [DX] in
84def IN8rr  : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
85let Defs = [AX], Uses = [DX] in
86def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
87               OpSize16;
88let Defs = [EAX], Uses = [DX] in
89def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
90               OpSize32;
91
92let Defs = [AL] in
93def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
94                 "in{b}\t{$port, %al|al, $port}", []>;
95let Defs = [AX] in
96def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
97                 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
98let Defs = [EAX] in
99def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
100                 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
101
102let Uses = [DX, AL] in
103def OUT8rr  : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
104let Uses = [DX, AX] in
105def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
106                OpSize16;
107let Uses = [DX, EAX] in
108def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
109                OpSize32;
110
111let Uses = [AL] in
112def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
113                   "out{b}\t{%al, $port|$port, al}", []>;
114let Uses = [AX] in
115def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
116                   "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
117let Uses = [EAX] in
118def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
119                  "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
120
121} // SchedRW
122
123//===----------------------------------------------------------------------===//
124// Moves to and from debug registers
125
126let SchedRW = [WriteSystem] in {
127def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
128                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
129                Requires<[Not64BitMode]>;
130def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
131                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
132                Requires<[In64BitMode]>;
133
134def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
135                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
136                Requires<[Not64BitMode]>;
137def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
138                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
139                Requires<[In64BitMode]>;
140} // SchedRW
141
142//===----------------------------------------------------------------------===//
143// Moves to and from control registers
144
145let SchedRW = [WriteSystem] in {
146def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
147                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
148                Requires<[Not64BitMode]>;
149def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
150                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
151                Requires<[In64BitMode]>;
152
153def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
154                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
155                Requires<[Not64BitMode]>;
156def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
157                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
158                Requires<[In64BitMode]>;
159} // SchedRW
160
161//===----------------------------------------------------------------------===//
162// Segment override instruction prefixes
163
164let SchedRW = [WriteNop] in {
165def CS_PREFIX : I<0x2E, PrefixByte, (outs), (ins), "cs", []>;
166def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>;
167def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>;
168def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>;
169def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>;
170def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>;
171} // SchedRW
172
173//===----------------------------------------------------------------------===//
174// Moves to and from segment registers.
175//
176
177let SchedRW = [WriteMove] in {
178def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
179                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
180def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
181                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
182def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
183                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
184let mayStore = 1 in {
185def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
186                "mov{w}\t{$src, $dst|$dst, $src}", []>;
187}
188def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
189                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
190def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
191                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
192def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
193                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
194let mayLoad = 1 in {
195def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
196                "mov{w}\t{$src, $dst|$dst, $src}", []>;
197}
198} // SchedRW
199
200//===----------------------------------------------------------------------===//
201// Segmentation support instructions.
202
203let SchedRW = [WriteSystem] in {
204def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
205
206let mayLoad = 1 in
207def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
208                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
209                OpSize16, NotMemoryFoldable;
210def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
211                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
212                OpSize16, NotMemoryFoldable;
213
214// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
215let mayLoad = 1 in
216def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
217                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
218                OpSize32, NotMemoryFoldable;
219def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
220                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
221                OpSize32, NotMemoryFoldable;
222// i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo.
223let mayLoad = 1 in
224def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
225                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
226def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
227                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
228
229// i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo.
230let mayLoad = 1 in
231def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
232                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
233                OpSize16, NotMemoryFoldable;
234def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
235                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
236                OpSize16, NotMemoryFoldable;
237// i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo.
238let mayLoad = 1 in
239def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
240                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
241                OpSize32, NotMemoryFoldable;
242def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
243                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
244                OpSize32, NotMemoryFoldable;
245let mayLoad = 1 in
246def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
247                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
248def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
249                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
250
251def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
252
253def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
254               "str{w}\t$dst", []>, TB, OpSize16;
255def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
256               "str{l}\t$dst", []>, TB, OpSize32;
257def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
258                "str{q}\t$dst", []>, TB;
259let mayStore = 1 in
260def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
261
262def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
263let mayLoad = 1 in
264def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
265
266def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
267                 OpSize16, Requires<[Not64BitMode]>;
268def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
269                 OpSize32, Requires<[Not64BitMode]>;
270def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
271                 OpSize16, Requires<[Not64BitMode]>;
272def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
273                 OpSize32, Requires<[Not64BitMode]>;
274def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
275                 OpSize16, Requires<[Not64BitMode]>;
276def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
277                 OpSize32, Requires<[Not64BitMode]>;
278def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
279                 OpSize16, Requires<[Not64BitMode]>;
280def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
281                 OpSize32, Requires<[Not64BitMode]>;
282def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
283                 OpSize16, TB;
284def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
285                 OpSize32, Requires<[Not64BitMode]>;
286def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
287                 OpSize16, TB;
288def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
289                 OpSize32, Requires<[Not64BitMode]>;
290def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
291                 OpSize32, Requires<[In64BitMode]>;
292def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
293                 OpSize32, Requires<[In64BitMode]>;
294
295// No "pop cs" instruction.
296def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
297              OpSize16, Requires<[Not64BitMode]>;
298def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
299              OpSize32, Requires<[Not64BitMode]>;
300
301def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
302              OpSize16, Requires<[Not64BitMode]>;
303def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
304              OpSize32, Requires<[Not64BitMode]>;
305
306def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
307              OpSize16, Requires<[Not64BitMode]>;
308def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
309              OpSize32, Requires<[Not64BitMode]>;
310
311def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
312                OpSize16, TB;
313def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
314                OpSize32, Requires<[Not64BitMode]>;
315def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
316                OpSize32, Requires<[In64BitMode]>;
317
318def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
319                OpSize16, TB;
320def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
321                OpSize32, Requires<[Not64BitMode]>;
322def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
323                OpSize32, Requires<[In64BitMode]>;
324
325def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
326                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
327                Requires<[Not64BitMode]>;
328def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
329                "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
330                Requires<[Not64BitMode]>;
331
332def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
333                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
334def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
335                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
336def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
337                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
338
339def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
340                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
341                Requires<[Not64BitMode]>;
342def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
343                "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
344                Requires<[Not64BitMode]>;
345
346def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
347                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
348def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
349                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
350def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
351                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
352
353def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
354                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
355def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
356                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
357
358def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
359                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
360
361def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
362def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
363let mayLoad = 1 in {
364def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
365def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
366}
367} // SchedRW
368
369//===----------------------------------------------------------------------===//
370// Descriptor-table support instructions
371
372let SchedRW = [WriteSystem] in {
373def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
374                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
375def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
376                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
377def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
378                "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
379def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
380                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
381def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
382                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
383def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
384                "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
385def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
386                "sldt{w}\t$dst", []>, TB, OpSize16;
387let mayStore = 1 in
388def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
389                "sldt{w}\t$dst", []>, TB;
390def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
391                "sldt{l}\t$dst", []>, OpSize32, TB;
392
393// LLDT is not interpreted specially in 64-bit mode because there is no sign
394//   extension.
395def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
396                 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
397
398def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
399                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
400def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
401                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
402def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
403                "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
404def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
405                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
406def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
407                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
408def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
409                "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
410def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
411                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
412let mayLoad = 1 in
413def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
414                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
415} // SchedRW
416
417//===----------------------------------------------------------------------===//
418// Specialized register support
419let SchedRW = [WriteSystem] in {
420let Uses = [EAX, ECX, EDX] in
421def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
422let Defs = [EAX, EDX], Uses = [ECX] in
423def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
424
425let Defs = [RAX, RDX], Uses = [ECX] in
426def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
427
428def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
429                "smsw{w}\t$dst", []>, OpSize16, TB;
430def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
431                "smsw{l}\t$dst", []>, OpSize32, TB;
432// no m form encodable; use SMSW16m
433def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
434                 "smsw{q}\t$dst", []>, TB;
435
436// For memory operands, there is only a 16-bit form
437def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
438                "smsw{w}\t$dst", []>, TB;
439
440def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
441                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
442let mayLoad = 1 in
443def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
444                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
445
446let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
447  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
448} // SchedRW
449
450//===----------------------------------------------------------------------===//
451// Cache instructions
452let SchedRW = [WriteSystem] in {
453def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
454def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB;
455
456// wbnoinvd is like wbinvd, except without invalidation
457// encoding: like wbinvd + an 0xF3 prefix
458def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
459                 [(int_x86_wbnoinvd)]>, XS,
460                 Requires<[HasWBNOINVD]>;
461} // SchedRW
462
463//===----------------------------------------------------------------------===//
464// CET instructions
465// Use with caution, availability is not predicated on features.
466let SchedRW = [WriteSystem] in {
467  let Uses = [SSP] in {
468    let Defs = [SSP] in {
469      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
470                       [(int_x86_incsspd GR32:$src)]>, XS;
471      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
472                       [(int_x86_incsspq GR64:$src)]>, XS;
473    } // Defs SSP
474
475    let Constraints = "$src = $dst" in {
476      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
477                     "rdsspd\t$dst",
478                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
479      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
480                     "rdsspq\t$dst",
481                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
482    }
483
484    let Defs = [SSP] in {
485      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
486                       [(int_x86_saveprevssp)]>, XS;
487      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
488                       "rstorssp\t$src",
489                       [(int_x86_rstorssp addr:$src)]>, XS;
490    } // Defs SSP
491  } // Uses SSP
492
493  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
494                "wrssd\t{$src, $dst|$dst, $src}",
495                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
496  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
497                 "wrssq\t{$src, $dst|$dst, $src}",
498                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
499  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
500                 "wrussd\t{$src, $dst|$dst, $src}",
501                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
502  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
503                  "wrussq\t{$src, $dst|$dst, $src}",
504                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
505
506  let Defs = [SSP] in {
507    let Uses = [SSP] in {
508        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
509                         [(int_x86_setssbsy)]>, XS;
510    } // Uses SSP
511
512    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
513                     "clrssbsy\t$src",
514                     [(int_x86_clrssbsy addr:$src)]>, XS;
515  } // Defs SSP
516} // SchedRW
517
518let SchedRW = [WriteSystem] in {
519    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
520    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
521} // SchedRW
522
523//===----------------------------------------------------------------------===//
524// XSAVE instructions
525let SchedRW = [WriteSystem] in {
526let Predicates = [HasXSAVE] in {
527let Defs = [EDX, EAX], Uses = [ECX] in
528  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, PS;
529
530let Uses = [EDX, EAX, ECX] in
531  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
532                "xsetbv",
533                [(int_x86_xsetbv ECX, EDX, EAX)]>, PS;
534
535} // HasXSAVE
536
537let Uses = [EDX, EAX] in {
538def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
539              "xsave\t$dst",
540              [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
541def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
542                 "xsave64\t$dst",
543                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
544def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
545               "xrstor\t$dst",
546               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
547def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
548                  "xrstor64\t$dst",
549                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
550def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
551                 "xsaveopt\t$dst",
552                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
553def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
554                    "xsaveopt64\t$dst",
555                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
556def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
557               "xsavec\t$dst",
558               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC]>;
559def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
560                 "xsavec64\t$dst",
561                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC, In64BitMode]>;
562def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
563               "xsaves\t$dst",
564               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
565def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
566                  "xsaves64\t$dst",
567                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
568def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
569                "xrstors\t$dst",
570                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
571def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
572                   "xrstors64\t$dst",
573                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES, In64BitMode]>;
574} // Uses
575} // SchedRW
576
577//===----------------------------------------------------------------------===//
578// VIA PadLock crypto instructions
579let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
580  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB, REP;
581
582def : InstAlias<"xstorerng", (XSTORE)>;
583
584let SchedRW = [WriteSystem] in {
585let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
586  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB, REP;
587  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB, REP;
588  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB, REP;
589  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB, REP;
590  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB, REP;
591}
592
593let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
594  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB, REP;
595  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB, REP;
596}
597let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
598  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB, REP;
599} // SchedRW
600
601//==-----------------------------------------------------------------------===//
602// PKU  - enable protection key
603let SchedRW = [WriteSystem] in {
604let Defs = [EAX, EDX], Uses = [ECX] in
605  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
606                  [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, PS;
607let Uses = [EAX, ECX, EDX] in
608  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
609                  [(X86wrpkru EAX, EDX, ECX)]>, PS;
610} // SchedRW
611
612//===----------------------------------------------------------------------===//
613// FS/GS Base Instructions
614let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
615  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
616                   "rdfsbase{l}\t$dst",
617                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
618  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
619                     "rdfsbase{q}\t$dst",
620                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
621  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
622                   "rdgsbase{l}\t$dst",
623                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
624  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
625                     "rdgsbase{q}\t$dst",
626                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
627  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
628                   "wrfsbase{l}\t$src",
629                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
630  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
631                      "wrfsbase{q}\t$src",
632                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
633  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
634                   "wrgsbase{l}\t$src",
635                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
636  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
637                      "wrgsbase{q}\t$src",
638                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
639}
640
641//===----------------------------------------------------------------------===//
642// INVPCID Instruction
643let SchedRW = [WriteSystem] in {
644def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
645                  "invpcid\t{$src2, $src1|$src1, $src2}",
646                  [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD,
647                  Requires<[Not64BitMode, HasINVPCID]>;
648def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
649                  "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
650                  Requires<[In64BitMode, HasINVPCID]>;
651} // SchedRW
652
653let Predicates = [In64BitMode, HasINVPCID] in {
654  // The instruction can only use a 64 bit register as the register argument
655  // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
656  // corresponding to it.
657  // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
658  // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
659  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
660            (INVPCID64
661              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
662              addr:$src2)>;
663}
664
665
666//===----------------------------------------------------------------------===//
667// SMAP Instruction
668let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
669  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, PS;
670  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, PS;
671}
672
673//===----------------------------------------------------------------------===//
674// SMX Instruction
675let SchedRW = [WriteSystem] in {
676let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
677  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, PS;
678} // Uses, Defs
679} // SchedRW
680
681//===----------------------------------------------------------------------===//
682// TS flag control instruction.
683let SchedRW = [WriteSystem] in {
684def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
685}
686
687//===----------------------------------------------------------------------===//
688// IF (inside EFLAGS) management instructions.
689let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
690def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
691def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
692}
693
694//===----------------------------------------------------------------------===//
695// RDPID Instruction
696let SchedRW = [WriteSystem] in {
697def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
698                "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS,
699                Requires<[Not64BitMode, HasRDPID]>;
700def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
701                Requires<[In64BitMode, HasRDPID]>;
702} // SchedRW
703
704let Predicates = [In64BitMode, HasRDPID] in {
705  // Due to silly instruction definition, we have to compensate for the
706  // instruction outputing a 64-bit register.
707  def : Pat<(int_x86_rdpid),
708            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
709}
710
711
712//===----------------------------------------------------------------------===//
713// PTWRITE Instruction - Write Data to a Processor Trace Packet
714let SchedRW = [WriteSystem] in {
715def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
716                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
717                Requires<[HasPTWRITE]>;
718def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
719                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
720                    Requires<[In64BitMode, HasPTWRITE]>;
721
722def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
723                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
724                    Requires<[HasPTWRITE]>;
725def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
726                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
727                    Requires<[In64BitMode, HasPTWRITE]>;
728} // SchedRW
729
730//===----------------------------------------------------------------------===//
731// Platform Configuration instruction
732
733// From ISA docs:
734//  "This instruction is used to execute functions for configuring platform
735//   features.
736//   EAX: Leaf function to be invoked.
737//   RBX/RCX/RDX: Leaf-specific purpose."
738//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
739//   AF, OF, and SF are cleared. In case of failure, the failure reason is
740//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
741// Thus all these mentioned registers are considered clobbered.
742
743let SchedRW = [WriteSystem] in {
744let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
745    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, PS,
746                  Requires<[HasPCONFIG]>;
747} // SchedRW
748