1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
23
24// CPU flow control instructions
25
26let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41def : Pat<(debugtrap),
42          (INT3)>;
43
44// The long form of "int $3" turns into int3 as a size optimization.
45// FIXME: This doesn't work because InstAlias can't match immediate constants.
46//def : InstAlias<"int\t$3", (INT3)>;
47
48let SchedRW = [WriteSystem] in {
49
50def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
51              [(int_x86_int imm:$trap)], IIC_INT>;
52
53
54def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
55def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
56def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
57               Requires<[In64BitMode]>;
58
59def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61
62def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
63                 IIC_SYS_ENTER_EXIT>, TB;
64def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
65                Requires<[In64BitMode]>;
66
67def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
68def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
69             OpSize16;
70def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
71             Requires<[In64BitMode]>;
72} // SchedRW
73
74
75//===----------------------------------------------------------------------===//
76//  Input/Output Instructions.
77//
78let SchedRW = [WriteSystem] in {
79let Defs = [AL], Uses = [DX] in
80def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
81               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
82let Defs = [AX], Uses = [DX] in
83def IN16rr : I<0xED, RawFrm, (outs), (ins),
84               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize;
85let Defs = [EAX], Uses = [DX] in
86def IN32rr : I<0xED, RawFrm, (outs), (ins),
87               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize16;
88
89let Defs = [AL] in
90def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
91                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
92let Defs = [AX] in
93def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
94                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
95let Defs = [EAX] in
96def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
97                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize16;
98
99let Uses = [DX, AL] in
100def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
101                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
102let Uses = [DX, AX] in
103def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
104                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
105let Uses = [DX, EAX] in
106def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
107                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize16;
108
109let Uses = [AL] in
110def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
111                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
112let Uses = [AX] in
113def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
114                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
115let Uses = [EAX] in
116def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
117                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
118
119def IN8  : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
120def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>,  OpSize;
121def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>, OpSize16;
122} // SchedRW
123
124//===----------------------------------------------------------------------===//
125// Moves to and from debug registers
126
127let SchedRW = [WriteSystem] in {
128def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
129                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
130                Requires<[Not64BitMode]>;
131def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
132                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
133                Requires<[In64BitMode]>;
134
135def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
136                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
137                Requires<[Not64BitMode]>;
138def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
139                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
140                Requires<[In64BitMode]>;
141} // SchedRW
142
143//===----------------------------------------------------------------------===//
144// Moves to and from control registers
145
146let SchedRW = [WriteSystem] in {
147def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
148                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
149                Requires<[Not64BitMode]>;
150def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
151                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
152                Requires<[In64BitMode]>;
153
154def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
155                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
156                Requires<[Not64BitMode]>;
157def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
158                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
159                Requires<[In64BitMode]>;
160} // SchedRW
161
162//===----------------------------------------------------------------------===//
163// Segment override instruction prefixes
164
165def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
166def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
167def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
168def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
169def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
170def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
171
172
173//===----------------------------------------------------------------------===//
174// Moves to and from segment registers.
175//
176
177let SchedRW = [WriteMove] in {
178def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
179                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
180def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
181                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
182def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
183                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
184
185def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
186                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
187def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
188                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
189def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
190                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
191
192def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
193                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
194def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
195                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
196def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
197                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
198
199def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
200                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
201def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
202                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
203def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
204                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
205} // SchedRW
206
207//===----------------------------------------------------------------------===//
208// Segmentation support instructions.
209
210let SchedRW = [WriteSystem] in {
211def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
212
213def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
214                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize;
215def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
216                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize;
217
218// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
219def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
220                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
221                OpSize16;
222def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
223                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
224                OpSize16;
225// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
226def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
227                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
228def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
229                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
230
231def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
232                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize;
233def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
234                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
235def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
236                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
237                OpSize16;
238def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
239                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
240                OpSize16;
241def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
242                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
243def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
244                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
245
246def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
247               [], IIC_INVLPG>, TB;
248
249def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
250               "str{w}\t$dst", [], IIC_STR>, TB, OpSize;
251def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
252               "str{l}\t$dst", [], IIC_STR>, TB, OpSize16;
253def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
254                "str{q}\t$dst", [], IIC_STR>, TB;
255def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
256               "str{w}\t$dst", [], IIC_STR>, TB;
257
258def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
259             "ltr{w}\t$src", [], IIC_LTR>, TB;
260def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
261             "ltr{w}\t$src", [], IIC_LTR>, TB;
262
263def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
264                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
265                 OpSize, Requires<[Not64BitMode]>;
266def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
267                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
268                 OpSize16, Requires<[Not64BitMode]>;
269def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
270                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
271                 OpSize, Requires<[Not64BitMode]>;
272def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
273                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
274                 OpSize16, Requires<[Not64BitMode]>;
275def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
276                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
277                 OpSize, Requires<[Not64BitMode]>;
278def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
279                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
280                 OpSize16, Requires<[Not64BitMode]>;
281def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
282                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
283                 OpSize, Requires<[Not64BitMode]>;
284def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
285                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
286                 OpSize16, Requires<[Not64BitMode]>;
287def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
288                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
289def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
290                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
291               OpSize16, Requires<[Not64BitMode]>;
292def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
293                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
294def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
295                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
296               OpSize16, Requires<[Not64BitMode]>;
297def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
298                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
299def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
300                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
301
302// No "pop cs" instruction.
303def POPSS16 : I<0x17, RawFrm, (outs), (ins),
304                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
305              OpSize, Requires<[Not64BitMode]>;
306def POPSS32 : I<0x17, RawFrm, (outs), (ins),
307                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
308              OpSize16, Requires<[Not64BitMode]>;
309
310def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
311                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
312              OpSize, Requires<[Not64BitMode]>;
313def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
314                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
315              OpSize16, Requires<[Not64BitMode]>;
316
317def POPES16 : I<0x07, RawFrm, (outs), (ins),
318                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
319              OpSize, Requires<[Not64BitMode]>;
320def POPES32 : I<0x07, RawFrm, (outs), (ins),
321                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
322              OpSize16, Requires<[Not64BitMode]>;
323
324def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
325                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
326def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
327                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
328              OpSize16, Requires<[Not64BitMode]>;
329def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
330                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
331
332def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
333                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
334def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
335                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
336              OpSize16, Requires<[Not64BitMode]>;
337def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
338                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
339
340
341def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
342                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
343def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
344                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
345
346def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
347                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
348def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
349                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
350def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
351                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
352
353def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
354                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
355def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
356                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
357
358def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
359                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
360def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
361                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
362def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
363                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
364
365def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
366                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
367def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
368                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
369
370def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
371                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
372
373
374def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
375              "verr\t$seg", [], IIC_VERR>, TB;
376def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
377              "verr\t$seg", [], IIC_VERR>, TB;
378def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
379              "verw\t$seg", [], IIC_VERW_MEM>, TB;
380def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
381              "verw\t$seg", [], IIC_VERW_REG>, TB;
382} // SchedRW
383
384//===----------------------------------------------------------------------===//
385// Descriptor-table support instructions
386
387let SchedRW = [WriteSystem] in {
388def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
389              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[Not64BitMode]>;
390def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
391              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize16, TB, Requires <[Not64BitMode]>;
392def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
393              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
394def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
395              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[Not64BitMode]>;
396def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
397              "sidt{l}\t$dst", []>, OpSize16, TB, Requires <[Not64BitMode]>;
398def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
399              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
400def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
401                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
402def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
403                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
404def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
405                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize16, TB;
406
407// LLDT is not interpreted specially in 64-bit mode because there is no sign
408//   extension.
409def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
410                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
411def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
412                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
413
414def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
415              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[Not64BitMode]>;
416def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
417              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize16, TB, Requires<[Not64BitMode]>;
418def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
419              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
420def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
421              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[Not64BitMode]>;
422def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
423              "lidt{l}\t$src", [], IIC_LIDT>, OpSize16, TB, Requires<[Not64BitMode]>;
424def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
425              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
426def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
427                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
428def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
429                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
430} // SchedRW
431
432//===----------------------------------------------------------------------===//
433// Specialized register support
434let SchedRW = [WriteSystem] in {
435def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
436def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
437def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
438
439def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
440                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
441def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
442                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize16, TB;
443// no m form encodable; use SMSW16m
444def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
445                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
446
447// For memory operands, there is only a 16-bit form
448def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
449                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
450
451def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
452                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
453def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
454                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
455
456def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
457} // SchedRW
458
459//===----------------------------------------------------------------------===//
460// Cache instructions
461let SchedRW = [WriteSystem] in {
462def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
463def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
464} // SchedRW
465
466//===----------------------------------------------------------------------===//
467// XSAVE instructions
468let SchedRW = [WriteSystem] in {
469let Defs = [RDX, RAX], Uses = [RCX] in
470  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
471
472let Uses = [RDX, RAX, RCX] in
473  def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
474
475let Uses = [RDX, RAX] in {
476  def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
477               "xsave\t$dst", []>, TB;
478  def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
479                 "xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
480  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
481               "xrstor\t$dst", []>, TB;
482  def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
483                 "xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
484  def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
485                  "xsaveopt\t$dst", []>, TB;
486  def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
487                    "xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
488}
489} // SchedRW
490
491//===----------------------------------------------------------------------===//
492// VIA PadLock crypto instructions
493let Defs = [RAX, RDI], Uses = [RDX, RDI] in
494  def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
495
496def : InstAlias<"xstorerng", (XSTORE)>;
497
498let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
499  def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
500  def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
501  def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
502  def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
503  def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
504}
505
506let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
507  def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
508  def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
509}
510let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
511  def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
512
513//===----------------------------------------------------------------------===//
514// FS/GS Base Instructions
515let Predicates = [HasFSGSBase, In64BitMode] in {
516  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
517                   "rdfsbase{l}\t$dst",
518                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
519  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
520                     "rdfsbase{q}\t$dst",
521                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
522  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
523                   "rdgsbase{l}\t$dst",
524                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
525  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
526                     "rdgsbase{q}\t$dst",
527                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
528  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
529                   "wrfsbase{l}\t$src",
530                   [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
531  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
532                      "wrfsbase{q}\t$src",
533                      [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
534  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
535                   "wrgsbase{l}\t$src",
536                   [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
537  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
538                      "wrgsbase{q}\t$src",
539                      [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
540}
541
542//===----------------------------------------------------------------------===//
543// INVPCID Instruction
544def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
545                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
546                Requires<[Not64BitMode]>;
547def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
548                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
549                Requires<[In64BitMode]>;
550
551//===----------------------------------------------------------------------===//
552// SMAP Instruction
553let Defs = [EFLAGS], Uses = [EFLAGS] in {
554  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
555  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
556}
557