1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)],
23                 IIC_RDTSCP>, TB;
24
25// CPU flow control instructions
26
27let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in {
28  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
29  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
30}
31
32def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
33def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
34
35// Interrupt and SysCall Instructions.
36let Uses = [EFLAGS] in
37  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
38def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
39              [(int_x86_int (i8 3))], IIC_INT3>;
40} // SchedRW
41
42// The long form of "int $3" turns into int3 as a size optimization.
43// FIXME: This doesn't work because InstAlias can't match immediate constants.
44//def : InstAlias<"int\t$3", (INT3)>;
45
46let SchedRW = [WriteSystem] in {
47
48def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
49              [(int_x86_int imm:$trap)], IIC_INT>;
50
51
52def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
53def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
54def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
55               Requires<[In64BitMode]>;
56
57def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
58                 IIC_SYS_ENTER_EXIT>, TB;
59
60def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
61                 IIC_SYS_ENTER_EXIT>, TB;
62def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
63                 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
64} // SchedRW
65
66def : Pat<(debugtrap),
67          (INT3)>, Requires<[NotPS4]>;
68def : Pat<(debugtrap),
69          (INT (i8 0x41))>, Requires<[IsPS4]>;
70
71//===----------------------------------------------------------------------===//
72//  Input/Output Instructions.
73//
74let SchedRW = [WriteSystem] in {
75let Defs = [AL], Uses = [DX] in
76def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
77               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
78let Defs = [AX], Uses = [DX] in
79def IN16rr : I<0xED, RawFrm, (outs), (ins),
80               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
81let Defs = [EAX], Uses = [DX] in
82def IN32rr : I<0xED, RawFrm, (outs), (ins),
83               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
84
85let Defs = [AL] in
86def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
87                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
88let Defs = [AX] in
89def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
90                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
91let Defs = [EAX] in
92def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
93                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
94
95let Uses = [DX, AL] in
96def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
97                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
98let Uses = [DX, AX] in
99def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
100                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
101let Uses = [DX, EAX] in
102def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
103                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
104
105let Uses = [AL] in
106def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
107                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
108let Uses = [AX] in
109def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
110                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
111let Uses = [EAX] in
112def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
113                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
114
115} // SchedRW
116
117//===----------------------------------------------------------------------===//
118// Moves to and from debug registers
119
120let SchedRW = [WriteSystem] in {
121def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
122                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
123                Requires<[Not64BitMode]>;
124def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
125                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
126                Requires<[In64BitMode]>;
127
128def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
129                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
130                Requires<[Not64BitMode]>;
131def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
132                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
133                Requires<[In64BitMode]>;
134} // SchedRW
135
136//===----------------------------------------------------------------------===//
137// Moves to and from control registers
138
139let SchedRW = [WriteSystem] in {
140def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
141                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
142                Requires<[Not64BitMode]>;
143def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
144                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
145                Requires<[In64BitMode]>;
146
147def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
148                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
149                Requires<[Not64BitMode]>;
150def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
151                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
152                Requires<[In64BitMode]>;
153} // SchedRW
154
155//===----------------------------------------------------------------------===//
156// Segment override instruction prefixes
157
158let SchedRW = [WriteNop] in {
159def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", [], IIC_NOP>;
160def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", [], IIC_NOP>;
161def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", [], IIC_NOP>;
162def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", [], IIC_NOP>;
163def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", [], IIC_NOP>;
164def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", [], IIC_NOP>;
165} // SchedRW
166
167//===----------------------------------------------------------------------===//
168// Moves to and from segment registers.
169//
170
171let SchedRW = [WriteMove] in {
172def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
173                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
174def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
175                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
176def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
177                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
178let mayStore = 1 in {
179def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
180                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore;
181}
182def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
183                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
184def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
185                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
186def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
187                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
188let mayLoad = 1 in {
189def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
190                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore;
191}
192} // SchedRW
193
194//===----------------------------------------------------------------------===//
195// Segmentation support instructions.
196
197let SchedRW = [WriteSystem] in {
198def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
199
200let mayLoad = 1 in
201def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
202                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
203                OpSize16;
204def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
205                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
206                OpSize16;
207
208// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
209let mayLoad = 1 in
210def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
211                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
212                OpSize32;
213def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
214                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
215                OpSize32;
216// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
217let mayLoad = 1 in
218def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
219                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
220def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
221                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
222
223let mayLoad = 1 in
224def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
225                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
226                OpSize16;
227def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
228                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
229                OpSize16;
230let mayLoad = 1 in
231def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
232                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
233                OpSize32;
234def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
235                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
236                OpSize32;
237let mayLoad = 1 in
238def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
239                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
240def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
241                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
242
243def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
244               [], IIC_INVLPG>, TB;
245
246def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
247               "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
248def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
249               "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
250def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
251                "str{q}\t$dst", [], IIC_STR>, TB;
252let mayStore = 1 in
253def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
254               "str{w}\t$dst", [], IIC_STR>, TB;
255
256def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
257             "ltr{w}\t$src", [], IIC_LTR>, TB;
258let mayLoad = 1 in
259def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
260             "ltr{w}\t$src", [], IIC_LTR>, TB;
261
262def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
263                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
264                 OpSize16, Requires<[Not64BitMode]>;
265def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
266                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
267                 OpSize32, Requires<[Not64BitMode]>;
268def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
269                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
270                 OpSize16, Requires<[Not64BitMode]>;
271def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
272                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
273                 OpSize32, Requires<[Not64BitMode]>;
274def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
275                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
276                 OpSize16, Requires<[Not64BitMode]>;
277def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
278                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
279                 OpSize32, Requires<[Not64BitMode]>;
280def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
281                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
282                 OpSize16, Requires<[Not64BitMode]>;
283def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
284                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
285                 OpSize32, Requires<[Not64BitMode]>;
286def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
287                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
288def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
289                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
290               OpSize32, Requires<[Not64BitMode]>;
291def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
292                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
293def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
294                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
295               OpSize32, Requires<[Not64BitMode]>;
296def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
297                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
298               OpSize32, Requires<[In64BitMode]>;
299def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
300                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
301               OpSize32, Requires<[In64BitMode]>;
302
303// No "pop cs" instruction.
304def POPSS16 : I<0x17, RawFrm, (outs), (ins),
305                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
306              OpSize16, Requires<[Not64BitMode]>;
307def POPSS32 : I<0x17, RawFrm, (outs), (ins),
308                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
309              OpSize32, Requires<[Not64BitMode]>;
310
311def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
312                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
313              OpSize16, Requires<[Not64BitMode]>;
314def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
315                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
316              OpSize32, Requires<[Not64BitMode]>;
317
318def POPES16 : I<0x07, RawFrm, (outs), (ins),
319                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
320              OpSize16, Requires<[Not64BitMode]>;
321def POPES32 : I<0x07, RawFrm, (outs), (ins),
322                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
323              OpSize32, Requires<[Not64BitMode]>;
324
325def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
326                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
327def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
328                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
329              OpSize32, Requires<[Not64BitMode]>;
330def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
331                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
332              OpSize32, Requires<[In64BitMode]>;
333
334def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
335                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
336def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
337                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
338              OpSize32, Requires<[Not64BitMode]>;
339def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
340                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
341              OpSize32, Requires<[In64BitMode]>;
342
343
344def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
345                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
346                Requires<[Not64BitMode]>;
347def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
348                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
349                Requires<[Not64BitMode]>;
350
351def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
352                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
353def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
354                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
355def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
356                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
357
358def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
359                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
360                Requires<[Not64BitMode]>;
361def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
362                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
363                Requires<[Not64BitMode]>;
364
365def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
366                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
367def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
368                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
369def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
370                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
371
372def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
373                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
374def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
375                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
376
377def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
378                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
379
380
381def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
382              "verr\t$seg", [], IIC_VERR>, TB;
383def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
384              "verw\t$seg", [], IIC_VERW_MEM>, TB;
385let mayLoad = 1 in {
386def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
387              "verr\t$seg", [], IIC_VERR>, TB;
388def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
389              "verw\t$seg", [], IIC_VERW_REG>, TB;
390}
391} // SchedRW
392
393//===----------------------------------------------------------------------===//
394// Descriptor-table support instructions
395
396let SchedRW = [WriteSystem] in {
397def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
398              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
399def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
400              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
401def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
402              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
403def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
404              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
405def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
406              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
407def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
408              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
409def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
410                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
411let mayStore = 1 in
412def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
413                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
414def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
415                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
416
417// LLDT is not interpreted specially in 64-bit mode because there is no sign
418//   extension.
419def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
420                 "sldt{q}\t$dst", [], IIC_SLDT>, TB, Requires<[In64BitMode]>;
421let mayStore = 1 in
422def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
423                 "sldt{q}\t$dst", [], IIC_SLDT>, TB, Requires<[In64BitMode]>;
424
425def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
426              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
427def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
428              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
429def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
430              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
431def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
432              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
433def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
434              "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
435def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
436              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
437def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
438                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
439let mayLoad = 1 in
440def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
441                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
442} // SchedRW
443
444//===----------------------------------------------------------------------===//
445// Specialized register support
446let SchedRW = [WriteSystem] in {
447let Uses = [EAX, ECX, EDX] in
448def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
449let Defs = [EAX, EDX], Uses = [ECX] in
450def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
451
452let Defs = [RAX, RDX], Uses = [ECX] in
453  def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
454              TB;
455
456def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
457                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
458def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
459                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
460// no m form encodable; use SMSW16m
461def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
462                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
463
464// For memory operands, there is only a 16-bit form
465def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
466                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
467
468def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
469                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
470let mayLoad = 1 in
471def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
472                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
473
474let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
475  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
476} // SchedRW
477
478//===----------------------------------------------------------------------===//
479// Cache instructions
480let SchedRW = [WriteSystem] in {
481def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
482def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
483} // SchedRW
484
485//===----------------------------------------------------------------------===//
486// CET instructions
487let SchedRW = [WriteSystem], Predicates = [HasSHSTK]  in{
488  let Uses = [SSP] in {
489    let Defs = [SSP] in {
490      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
491                       [(int_x86_incsspd GR32:$src)]>, XS;
492      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
493                       [(int_x86_incsspq GR64:$src)]>, XS;
494    } // Defs SSP
495
496    let Constraints = "$src = $dst" in {
497      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
498                     "rdsspd\t$dst",
499                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
500      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
501                     "rdsspq\t$dst",
502                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
503    }
504
505    let Defs = [SSP] in {
506      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
507                       [(int_x86_saveprevssp)]>, XS;
508      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
509                       "rstorssp\t$src",
510                       [(int_x86_rstorssp addr:$src)]>, XS;
511    } // Defs SSP
512  } // Uses SSP
513
514  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
515                "wrssd\t{$src, $dst|$dst, $src}",
516                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
517  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
518                 "wrssq\t{$src, $dst|$dst, $src}",
519                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
520  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
521                 "wrussd\t{$src, $dst|$dst, $src}",
522                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
523  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
524                  "wrussq\t{$src, $dst|$dst, $src}",
525                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
526
527  let Defs = [SSP] in {
528    let Uses = [SSP] in {
529        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
530                         [(int_x86_setssbsy)]>, XS;
531    } // Uses SSP
532
533    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
534                     "clrssbsy\t$src",
535                     [(int_x86_clrssbsy addr:$src)]>, XS;
536  } // Defs SSP
537} // SchedRW && HasSHSTK
538
539let Predicates = [HasIBT]  in {
540    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
541    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
542} // HasIBT
543
544//===----------------------------------------------------------------------===//
545// XSAVE instructions
546let SchedRW = [WriteSystem] in {
547let Predicates = [HasXSAVE] in {
548let Defs = [EDX, EAX], Uses = [ECX] in
549  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
550
551let Uses = [EDX, EAX, ECX] in
552  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
553                "xsetbv",
554                [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
555
556} // HasXSAVE
557
558let Uses = [EDX, EAX] in {
559def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
560              "xsave\t$dst",
561              [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
562def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
563                 "xsave64\t$dst",
564                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
565def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
566               "xrstor\t$dst",
567               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
568def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
569                  "xrstor64\t$dst",
570                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
571def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
572                 "xsaveopt\t$dst",
573                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
574def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
575                    "xsaveopt64\t$dst",
576                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
577def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
578               "xsavec\t$dst",
579               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
580def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
581                 "xsavec64\t$dst",
582                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
583def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
584               "xsaves\t$dst",
585               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
586def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
587                  "xsaves64\t$dst",
588                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
589def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
590                "xrstors\t$dst",
591                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
592def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
593                   "xrstors64\t$dst",
594                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
595} // Uses
596} // SchedRW
597
598//===----------------------------------------------------------------------===//
599// VIA PadLock crypto instructions
600let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
601  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
602
603def : InstAlias<"xstorerng", (XSTORE)>;
604
605let SchedRW = [WriteSystem] in {
606let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
607  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
608  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
609  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
610  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
611  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
612}
613
614let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
615  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
616  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
617}
618let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
619  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
620} // SchedRW
621
622//==-----------------------------------------------------------------------===//
623// PKU  - enable protection key
624let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
625  def WRPKRU : PseudoI<(outs), (ins GR32:$src),
626                [(int_x86_wrpkru GR32:$src)]>;
627  def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
628                [(set GR32:$dst, (int_x86_rdpkru))]>;
629}
630
631let SchedRW = [WriteSystem] in {
632let Defs = [EAX, EDX], Uses = [ECX] in
633  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", [], IIC_PKU>, TB;
634let Uses = [EAX, ECX, EDX] in
635  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", [], IIC_PKU>, TB;
636} // SchedRW
637
638//===----------------------------------------------------------------------===//
639// FS/GS Base Instructions
640let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
641  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
642                   "rdfsbase{l}\t$dst",
643                   [(set GR32:$dst, (int_x86_rdfsbase_32))],
644                   IIC_SEGMENT_BASE_R>, XS;
645  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
646                     "rdfsbase{q}\t$dst",
647                     [(set GR64:$dst, (int_x86_rdfsbase_64))],
648                     IIC_SEGMENT_BASE_R>, XS;
649  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
650                   "rdgsbase{l}\t$dst",
651                   [(set GR32:$dst, (int_x86_rdgsbase_32))],
652                   IIC_SEGMENT_BASE_R>, XS;
653  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
654                     "rdgsbase{q}\t$dst",
655                     [(set GR64:$dst, (int_x86_rdgsbase_64))],
656                     IIC_SEGMENT_BASE_R>, XS;
657  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
658                   "wrfsbase{l}\t$src",
659                   [(int_x86_wrfsbase_32 GR32:$src)],
660                   IIC_SEGMENT_BASE_W>, XS;
661  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
662                      "wrfsbase{q}\t$src",
663                      [(int_x86_wrfsbase_64 GR64:$src)],
664                      IIC_SEGMENT_BASE_W>, XS;
665  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
666                   "wrgsbase{l}\t$src",
667                   [(int_x86_wrgsbase_32 GR32:$src)], IIC_SEGMENT_BASE_W>, XS;
668  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
669                      "wrgsbase{q}\t$src",
670                      [(int_x86_wrgsbase_64 GR64:$src)],
671                      IIC_SEGMENT_BASE_W>, XS;
672}
673
674//===----------------------------------------------------------------------===//
675// INVPCID Instruction
676let SchedRW = [WriteSystem] in {
677def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
678                "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
679                Requires<[Not64BitMode]>;
680def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
681                "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
682                Requires<[In64BitMode]>;
683} // SchedRW
684
685//===----------------------------------------------------------------------===//
686// SMAP Instruction
687let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
688  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", [], IIC_SMAP>, TB;
689  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", [], IIC_SMAP>, TB;
690}
691
692//===----------------------------------------------------------------------===//
693// SMX Instruction
694let SchedRW = [WriteSystem] in {
695let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
696  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", [], IIC_SMX>, TB;
697} // Uses, Defs
698} // SchedRW
699
700//===----------------------------------------------------------------------===//
701// RDPID Instruction
702let SchedRW = [WriteSystem] in {
703def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
704              "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))], IIC_RDPID>, XS,
705              Requires<[Not64BitMode, HasRDPID]>;
706def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins),
707              "rdpid\t$dst", [], IIC_RDPID>, XS,
708              Requires<[In64BitMode, HasRDPID]>;
709} // SchedRW
710
711let Predicates = [In64BitMode, HasRDPID] in {
712  // Due to silly instruction definition, we have to compensate for the
713  // instruction outputing a 64-bit register.
714  def : Pat<(int_x86_rdpid),
715            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
716}
717
718
719//===----------------------------------------------------------------------===//
720// PTWRITE Instruction
721let SchedRW = [WriteSystem] in {
722
723def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
724                "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
725def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
726                    "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
727                    Requires<[In64BitMode]>;
728
729def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
730                 "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
731def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
732                    "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
733                    Requires<[In64BitMode]>;
734} // SchedRW
735