1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
23
24// CPU flow control instructions
25
26let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41// The long form of "int $3" turns into int3 as a size optimization.
42// FIXME: This doesn't work because InstAlias can't match immediate constants.
43//def : InstAlias<"int\t$3", (INT3)>;
44
45let SchedRW = [WriteSystem] in {
46
47def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
48              [(int_x86_int imm:$trap)], IIC_INT>;
49
50
51def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
52def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
53def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
54               Requires<[In64BitMode]>;
55
56def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
57                 IIC_SYS_ENTER_EXIT>, TB;
58
59def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
62                 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
63} // SchedRW
64
65def : Pat<(debugtrap),
66          (INT3)>, Requires<[NotPS4]>;
67def : Pat<(debugtrap),
68          (INT (i8 0x41))>, Requires<[IsPS4]>;
69
70//===----------------------------------------------------------------------===//
71//  Input/Output Instructions.
72//
73let SchedRW = [WriteSystem] in {
74let Defs = [AL], Uses = [DX] in
75def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
76               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
77let Defs = [AX], Uses = [DX] in
78def IN16rr : I<0xED, RawFrm, (outs), (ins),
79               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
80let Defs = [EAX], Uses = [DX] in
81def IN32rr : I<0xED, RawFrm, (outs), (ins),
82               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
83
84let Defs = [AL] in
85def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
86                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
87let Defs = [AX] in
88def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
89                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
90let Defs = [EAX] in
91def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
92                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
93
94let Uses = [DX, AL] in
95def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
96                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
97let Uses = [DX, AX] in
98def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
99                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
100let Uses = [DX, EAX] in
101def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
102                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
103
104let Uses = [AL] in
105def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
106                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
107let Uses = [AX] in
108def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
109                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
110let Uses = [EAX] in
111def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
112                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
113
114} // SchedRW
115
116//===----------------------------------------------------------------------===//
117// Moves to and from debug registers
118
119let SchedRW = [WriteSystem] in {
120def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
121                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
122                Requires<[Not64BitMode]>;
123def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
124                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
125                Requires<[In64BitMode]>;
126
127def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
128                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
129                Requires<[Not64BitMode]>;
130def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
131                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
132                Requires<[In64BitMode]>;
133} // SchedRW
134
135//===----------------------------------------------------------------------===//
136// Moves to and from control registers
137
138let SchedRW = [WriteSystem] in {
139def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
140                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
141                Requires<[Not64BitMode]>;
142def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
143                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
144                Requires<[In64BitMode]>;
145
146def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
147                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
148                Requires<[Not64BitMode]>;
149def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
150                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
151                Requires<[In64BitMode]>;
152} // SchedRW
153
154//===----------------------------------------------------------------------===//
155// Segment override instruction prefixes
156
157def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
158def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
159def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
160def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
161def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
162def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
163
164
165//===----------------------------------------------------------------------===//
166// Moves to and from segment registers.
167//
168
169let SchedRW = [WriteMove] in {
170def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
171                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
172def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
173                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
174def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
175                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
176let mayStore = 1 in {
177def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
178                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
179def MOV32ms : I<0x8C, MRMDestMem, (outs), (ins i32mem:$dst, SEGMENT_REG:$src),
180                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
181def MOV64ms : RI<0x8C, MRMDestMem, (outs), (ins i64mem:$dst, SEGMENT_REG:$src),
182                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
183}
184def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
185                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
186def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
187                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
188def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
189                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
190let mayLoad = 1 in {
191def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
192                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
193def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
194                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
195def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
196                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
197}
198} // SchedRW
199
200//===----------------------------------------------------------------------===//
201// Segmentation support instructions.
202
203let SchedRW = [WriteSystem] in {
204def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
205
206let mayLoad = 1 in
207def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
208                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
209                OpSize16;
210def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
211                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
212                OpSize16;
213
214// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
215let mayLoad = 1 in
216def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
217                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
218                OpSize32;
219def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
220                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
221                OpSize32;
222// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
223let mayLoad = 1 in
224def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
225                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
226def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
227                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
228
229let mayLoad = 1 in
230def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
231                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
232                OpSize16;
233def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
234                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
235                OpSize16;
236let mayLoad = 1 in
237def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
238                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
239                OpSize32;
240def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
241                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
242                OpSize32;
243let mayLoad = 1 in
244def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
245                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
246def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
247                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
248
249def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
250               [], IIC_INVLPG>, TB;
251
252def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
253               "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
254def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
255               "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
256def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
257                "str{q}\t$dst", [], IIC_STR>, TB;
258let mayStore = 1 in
259def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
260               "str{w}\t$dst", [], IIC_STR>, TB;
261
262def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
263             "ltr{w}\t$src", [], IIC_LTR>, TB;
264let mayLoad = 1 in
265def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
266             "ltr{w}\t$src", [], IIC_LTR>, TB;
267
268def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
269                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
270                 OpSize16, Requires<[Not64BitMode]>;
271def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
272                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
273                 OpSize32, Requires<[Not64BitMode]>;
274def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
275                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
276                 OpSize16, Requires<[Not64BitMode]>;
277def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
278                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
279                 OpSize32, Requires<[Not64BitMode]>;
280def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
281                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
282                 OpSize16, Requires<[Not64BitMode]>;
283def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
284                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
285                 OpSize32, Requires<[Not64BitMode]>;
286def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
287                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
288                 OpSize16, Requires<[Not64BitMode]>;
289def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
290                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
291                 OpSize32, Requires<[Not64BitMode]>;
292def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
293                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
294def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
295                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
296               OpSize32, Requires<[Not64BitMode]>;
297def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
298                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
299def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
300                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
301               OpSize32, Requires<[Not64BitMode]>;
302def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
303                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
304               OpSize32, Requires<[In64BitMode]>;
305def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
306                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
307               OpSize32, Requires<[In64BitMode]>;
308
309// No "pop cs" instruction.
310def POPSS16 : I<0x17, RawFrm, (outs), (ins),
311                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
312              OpSize16, Requires<[Not64BitMode]>;
313def POPSS32 : I<0x17, RawFrm, (outs), (ins),
314                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
315              OpSize32, Requires<[Not64BitMode]>;
316
317def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
318                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
319              OpSize16, Requires<[Not64BitMode]>;
320def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
321                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
322              OpSize32, Requires<[Not64BitMode]>;
323
324def POPES16 : I<0x07, RawFrm, (outs), (ins),
325                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
326              OpSize16, Requires<[Not64BitMode]>;
327def POPES32 : I<0x07, RawFrm, (outs), (ins),
328                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
329              OpSize32, Requires<[Not64BitMode]>;
330
331def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
332                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
333def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
334                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
335              OpSize32, Requires<[Not64BitMode]>;
336def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
337                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
338              OpSize32, Requires<[In64BitMode]>;
339
340def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
341                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
342def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
343                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
344              OpSize32, Requires<[Not64BitMode]>;
345def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
346                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
347              OpSize32, Requires<[In64BitMode]>;
348
349
350def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
351                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
352                Requires<[Not64BitMode]>;
353def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
354                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
355                Requires<[Not64BitMode]>;
356
357def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
358                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
359def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
360                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
361def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
362                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
363
364def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
365                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
366                Requires<[Not64BitMode]>;
367def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
368                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
369                Requires<[Not64BitMode]>;
370
371def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
372                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
373def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
374                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
375def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
376                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
377
378def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
379                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
380def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
381                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
382
383def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
384                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
385
386
387def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
388              "verr\t$seg", [], IIC_VERR>, TB;
389def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
390              "verw\t$seg", [], IIC_VERW_MEM>, TB;
391let mayLoad = 1 in {
392def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
393              "verr\t$seg", [], IIC_VERR>, TB;
394def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
395              "verw\t$seg", [], IIC_VERW_REG>, TB;
396}
397} // SchedRW
398
399//===----------------------------------------------------------------------===//
400// Descriptor-table support instructions
401
402let SchedRW = [WriteSystem] in {
403def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
404              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
405def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
406              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
407def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
408              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
409def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
410              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
411def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
412              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
413def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
414              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
415def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
416                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
417let mayStore = 1 in
418def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
419                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
420def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
421                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
422
423// LLDT is not interpreted specially in 64-bit mode because there is no sign
424//   extension.
425def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
426                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
427let mayStore = 1 in
428def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
429                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
430
431def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
432              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
433def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
434              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
435def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
436              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
437def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
438              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
439def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
440              "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
441def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
442              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
443def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
444                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
445let mayLoad = 1 in
446def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
447                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
448} // SchedRW
449
450//===----------------------------------------------------------------------===//
451// Specialized register support
452let SchedRW = [WriteSystem] in {
453let Uses = [EAX, ECX, EDX] in
454def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
455let Defs = [EAX, EDX], Uses = [ECX] in
456def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
457
458let Defs = [RAX, RDX], Uses = [ECX] in
459  def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
460              TB;
461
462def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
463                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
464def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
465                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
466// no m form encodable; use SMSW16m
467def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
468                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
469
470// For memory operands, there is only a 16-bit form
471def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
472                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
473
474def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
475                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
476let mayLoad = 1 in
477def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
478                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
479
480let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
481  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
482} // SchedRW
483
484//===----------------------------------------------------------------------===//
485// Cache instructions
486let SchedRW = [WriteSystem] in {
487def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
488def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
489} // SchedRW
490
491//===----------------------------------------------------------------------===//
492// XSAVE instructions
493let SchedRW = [WriteSystem] in {
494let Predicates = [HasXSAVE] in {
495let Defs = [EDX, EAX], Uses = [ECX] in
496  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
497
498let Uses = [EDX, EAX, ECX] in
499  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
500                "xsetbv",
501                [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
502
503} // HasXSAVE
504
505let Uses = [EDX, EAX] in {
506let Predicates = [HasXSAVE] in {
507  def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
508                "xsave\t$dst",
509                [(int_x86_xsave addr:$dst, EDX, EAX)]>, TB;
510  def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
511                   "xsave64\t$dst",
512                   [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
513  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
514                 "xrstor\t$dst",
515                 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, TB;
516  def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
517                    "xrstor64\t$dst",
518                    [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
519}
520let Predicates = [HasXSAVEOPT] in {
521  def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
522                   "xsaveopt\t$dst",
523                   [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS;
524  def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
525                      "xsaveopt64\t$dst",
526                      [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[In64BitMode]>;
527}
528let Predicates = [HasXSAVEC] in {
529  def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
530                 "xsavec\t$dst",
531                 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB;
532  def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
533                   "xsavec64\t$dst",
534                   [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
535}
536let Predicates = [HasXSAVES] in {
537  def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
538                 "xsaves\t$dst",
539                 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB;
540  def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
541                    "xsaves64\t$dst",
542                    [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
543  def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
544                  "xrstors\t$dst",
545                  [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB;
546  def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
547                     "xrstors64\t$dst",
548                     [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
549}
550} // Uses
551} // SchedRW
552
553//===----------------------------------------------------------------------===//
554// VIA PadLock crypto instructions
555let Defs = [RAX, RDI], Uses = [RDX, RDI] in
556  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
557
558def : InstAlias<"xstorerng", (XSTORE)>;
559
560let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
561  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
562  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
563  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
564  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
565  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
566}
567
568let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
569  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
570  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
571}
572let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
573  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
574//==-----------------------------------------------------------------------===//
575// PKU  - enable protection key
576let usesCustomInserter = 1 in {
577  def WRPKRU : PseudoI<(outs), (ins GR32:$src),
578                [(int_x86_wrpkru GR32:$src)]>;
579  def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
580                [(set GR32:$dst, (int_x86_rdpkru))]>;
581}
582
583let Defs = [EAX, EDX], Uses = [ECX] in
584  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB;
585let Uses = [EAX, ECX, EDX] in
586  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB;
587
588//===----------------------------------------------------------------------===//
589// FS/GS Base Instructions
590let Predicates = [HasFSGSBase, In64BitMode] in {
591  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
592                   "rdfsbase{l}\t$dst",
593                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
594  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
595                     "rdfsbase{q}\t$dst",
596                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
597  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
598                   "rdgsbase{l}\t$dst",
599                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
600  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
601                     "rdgsbase{q}\t$dst",
602                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
603  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
604                   "wrfsbase{l}\t$src",
605                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
606  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
607                      "wrfsbase{q}\t$src",
608                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
609  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
610                   "wrgsbase{l}\t$src",
611                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
612  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
613                      "wrgsbase{q}\t$src",
614                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
615}
616
617//===----------------------------------------------------------------------===//
618// INVPCID Instruction
619def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
620                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
621                Requires<[Not64BitMode]>;
622def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
623                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
624                Requires<[In64BitMode]>;
625
626//===----------------------------------------------------------------------===//
627// SMAP Instruction
628let Defs = [EFLAGS] in {
629  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
630  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
631}
632
633//===----------------------------------------------------------------------===//
634// SMX Instruction
635let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
636  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
637}
638