1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)],
23                 IIC_RDTSCP>, TB;
24
25// CPU flow control instructions
26
27let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in {
28  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
29  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
30}
31
32def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
33def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
34
35// Interrupt and SysCall Instructions.
36let Uses = [EFLAGS] in
37  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
38def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
39              [(int_x86_int (i8 3))], IIC_INT3>;
40} // SchedRW
41
42// The long form of "int $3" turns into int3 as a size optimization.
43// FIXME: This doesn't work because InstAlias can't match immediate constants.
44//def : InstAlias<"int\t$3", (INT3)>;
45
46let SchedRW = [WriteSystem] in {
47
48def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
49              [(int_x86_int imm:$trap)], IIC_INT>;
50
51
52def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
53def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
54def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
55               Requires<[In64BitMode]>;
56
57def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
58                 IIC_SYS_ENTER_EXIT>, TB;
59
60def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
61                 IIC_SYS_ENTER_EXIT>, TB;
62def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
63                 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
64} // SchedRW
65
66def : Pat<(debugtrap),
67          (INT3)>, Requires<[NotPS4]>;
68def : Pat<(debugtrap),
69          (INT (i8 0x41))>, Requires<[IsPS4]>;
70
71//===----------------------------------------------------------------------===//
72//  Input/Output Instructions.
73//
74let SchedRW = [WriteSystem] in {
75let Defs = [AL], Uses = [DX] in
76def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
77               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
78let Defs = [AX], Uses = [DX] in
79def IN16rr : I<0xED, RawFrm, (outs), (ins),
80               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
81let Defs = [EAX], Uses = [DX] in
82def IN32rr : I<0xED, RawFrm, (outs), (ins),
83               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
84
85let Defs = [AL] in
86def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
87                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
88let Defs = [AX] in
89def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
90                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
91let Defs = [EAX] in
92def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
93                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
94
95let Uses = [DX, AL] in
96def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
97                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
98let Uses = [DX, AX] in
99def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
100                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
101let Uses = [DX, EAX] in
102def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
103                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
104
105let Uses = [AL] in
106def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
107                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
108let Uses = [AX] in
109def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
110                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
111let Uses = [EAX] in
112def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
113                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
114
115} // SchedRW
116
117//===----------------------------------------------------------------------===//
118// Moves to and from debug registers
119
120let SchedRW = [WriteSystem] in {
121def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
122                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
123                Requires<[Not64BitMode]>;
124def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
125                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
126                Requires<[In64BitMode]>;
127
128def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
129                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
130                Requires<[Not64BitMode]>;
131def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
132                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
133                Requires<[In64BitMode]>;
134} // SchedRW
135
136//===----------------------------------------------------------------------===//
137// Moves to and from control registers
138
139let SchedRW = [WriteSystem] in {
140def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
141                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
142                Requires<[Not64BitMode]>;
143def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
144                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
145                Requires<[In64BitMode]>;
146
147def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
148                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
149                Requires<[Not64BitMode]>;
150def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
151                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
152                Requires<[In64BitMode]>;
153} // SchedRW
154
155//===----------------------------------------------------------------------===//
156// Segment override instruction prefixes
157
158let SchedRW = [WriteNop] in {
159def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", [], IIC_NOP>;
160def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", [], IIC_NOP>;
161def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", [], IIC_NOP>;
162def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", [], IIC_NOP>;
163def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", [], IIC_NOP>;
164def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", [], IIC_NOP>;
165} // SchedRW
166
167//===----------------------------------------------------------------------===//
168// Moves to and from segment registers.
169//
170
171let SchedRW = [WriteMove] in {
172def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
173                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
174def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
175                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
176def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
177                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
178let mayStore = 1 in {
179def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
180                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSizeIgnore;
181}
182def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
183                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
184def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
185                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
186def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
187                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
188let mayLoad = 1 in {
189def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
190                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSizeIgnore;
191}
192} // SchedRW
193
194//===----------------------------------------------------------------------===//
195// Segmentation support instructions.
196
197let SchedRW = [WriteSystem] in {
198def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
199
200let mayLoad = 1 in
201def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
202                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
203                OpSize16;
204def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
205                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
206                OpSize16;
207
208// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
209let mayLoad = 1 in
210def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
211                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
212                OpSize32;
213def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
214                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
215                OpSize32;
216// i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo.
217let mayLoad = 1 in
218def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
219                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
220def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
221                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
222
223// i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo.
224let mayLoad = 1 in
225def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
226                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
227                OpSize16;
228def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
229                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
230                OpSize16;
231// i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo.
232let mayLoad = 1 in
233def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
234                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
235                OpSize32;
236def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
237                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
238                OpSize32;
239let mayLoad = 1 in
240def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
241                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
242def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
243                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
244
245def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
246               [], IIC_INVLPG>, TB;
247
248def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
249               "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
250def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
251               "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
252def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
253                "str{q}\t$dst", [], IIC_STR>, TB;
254let mayStore = 1 in
255def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
256               "str{w}\t$dst", [], IIC_STR>, TB;
257
258def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
259             "ltr{w}\t$src", [], IIC_LTR>, TB;
260let mayLoad = 1 in
261def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
262             "ltr{w}\t$src", [], IIC_LTR>, TB;
263
264def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
265                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
266                 OpSize16, Requires<[Not64BitMode]>;
267def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
268                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
269                 OpSize32, Requires<[Not64BitMode]>;
270def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
271                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
272                 OpSize16, Requires<[Not64BitMode]>;
273def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
274                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
275                 OpSize32, Requires<[Not64BitMode]>;
276def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
277                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
278                 OpSize16, Requires<[Not64BitMode]>;
279def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
280                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
281                 OpSize32, Requires<[Not64BitMode]>;
282def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
283                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
284                 OpSize16, Requires<[Not64BitMode]>;
285def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
286                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
287                 OpSize32, Requires<[Not64BitMode]>;
288def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
289                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
290def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
291                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
292               OpSize32, Requires<[Not64BitMode]>;
293def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
294                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
295def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
296                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
297               OpSize32, Requires<[Not64BitMode]>;
298def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
299                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
300               OpSize32, Requires<[In64BitMode]>;
301def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
302                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
303               OpSize32, Requires<[In64BitMode]>;
304
305// No "pop cs" instruction.
306def POPSS16 : I<0x17, RawFrm, (outs), (ins),
307                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
308              OpSize16, Requires<[Not64BitMode]>;
309def POPSS32 : I<0x17, RawFrm, (outs), (ins),
310                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
311              OpSize32, Requires<[Not64BitMode]>;
312
313def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
314                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
315              OpSize16, Requires<[Not64BitMode]>;
316def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
317                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
318              OpSize32, Requires<[Not64BitMode]>;
319
320def POPES16 : I<0x07, RawFrm, (outs), (ins),
321                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
322              OpSize16, Requires<[Not64BitMode]>;
323def POPES32 : I<0x07, RawFrm, (outs), (ins),
324                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
325              OpSize32, Requires<[Not64BitMode]>;
326
327def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
328                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
329def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
330                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
331              OpSize32, Requires<[Not64BitMode]>;
332def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
333                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
334              OpSize32, Requires<[In64BitMode]>;
335
336def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
337                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
338def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
339                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
340              OpSize32, Requires<[Not64BitMode]>;
341def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
342                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
343              OpSize32, Requires<[In64BitMode]>;
344
345
346def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
347                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
348                Requires<[Not64BitMode]>;
349def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
350                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
351                Requires<[Not64BitMode]>;
352
353def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
354                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
355def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
356                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
357def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
358                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
359
360def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
361                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
362                Requires<[Not64BitMode]>;
363def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
364                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
365                Requires<[Not64BitMode]>;
366
367def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
368                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
369def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
370                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
371def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
372                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
373
374def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
375                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
376def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
377                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
378
379def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
380                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
381
382
383def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
384              "verr\t$seg", [], IIC_VERR>, TB;
385def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
386              "verw\t$seg", [], IIC_VERW_MEM>, TB;
387let mayLoad = 1 in {
388def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
389              "verr\t$seg", [], IIC_VERR>, TB;
390def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
391              "verw\t$seg", [], IIC_VERW_REG>, TB;
392}
393} // SchedRW
394
395//===----------------------------------------------------------------------===//
396// Descriptor-table support instructions
397
398let SchedRW = [WriteSystem] in {
399def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
400              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
401def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
402              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
403def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
404              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
405def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
406              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
407def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
408              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
409def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
410              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
411def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
412                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
413let mayStore = 1 in
414def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
415                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
416def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
417                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
418
419// LLDT is not interpreted specially in 64-bit mode because there is no sign
420//   extension.
421def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
422                 "sldt{q}\t$dst", [], IIC_SLDT>, TB, Requires<[In64BitMode]>;
423let mayStore = 1 in
424def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
425                 "sldt{q}\t$dst", [], IIC_SLDT>, TB, Requires<[In64BitMode]>;
426
427def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
428              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
429def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
430              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
431def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
432              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
433def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
434              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
435def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
436              "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
437def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
438              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
439def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
440                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
441let mayLoad = 1 in
442def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
443                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
444} // SchedRW
445
446//===----------------------------------------------------------------------===//
447// Specialized register support
448let SchedRW = [WriteSystem] in {
449let Uses = [EAX, ECX, EDX] in
450def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
451let Defs = [EAX, EDX], Uses = [ECX] in
452def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
453
454let Defs = [RAX, RDX], Uses = [ECX] in
455  def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
456              TB;
457
458def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
459                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
460def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
461                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
462// no m form encodable; use SMSW16m
463def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
464                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
465
466// For memory operands, there is only a 16-bit form
467def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
468                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
469
470def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
471                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
472let mayLoad = 1 in
473def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
474                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
475
476let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
477  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
478} // SchedRW
479
480//===----------------------------------------------------------------------===//
481// Cache instructions
482let SchedRW = [WriteSystem] in {
483def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
484def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
485} // SchedRW
486
487//===----------------------------------------------------------------------===//
488// CET instructions
489let SchedRW = [WriteSystem], Predicates = [HasSHSTK]  in{
490  let Uses = [SSP] in {
491    let Defs = [SSP] in {
492      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
493                       [(int_x86_incsspd GR32:$src)]>, XS;
494      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
495                       [(int_x86_incsspq GR64:$src)]>, XS;
496    } // Defs SSP
497
498    let Constraints = "$src = $dst" in {
499      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
500                     "rdsspd\t$dst",
501                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
502      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
503                     "rdsspq\t$dst",
504                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
505    }
506
507    let Defs = [SSP] in {
508      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
509                       [(int_x86_saveprevssp)]>, XS;
510      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
511                       "rstorssp\t$src",
512                       [(int_x86_rstorssp addr:$src)]>, XS;
513    } // Defs SSP
514  } // Uses SSP
515
516  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
517                "wrssd\t{$src, $dst|$dst, $src}",
518                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
519  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
520                 "wrssq\t{$src, $dst|$dst, $src}",
521                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
522  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
523                 "wrussd\t{$src, $dst|$dst, $src}",
524                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
525  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
526                  "wrussq\t{$src, $dst|$dst, $src}",
527                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
528
529  let Defs = [SSP] in {
530    let Uses = [SSP] in {
531        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
532                         [(int_x86_setssbsy)]>, XS;
533    } // Uses SSP
534
535    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
536                     "clrssbsy\t$src",
537                     [(int_x86_clrssbsy addr:$src)]>, XS;
538  } // Defs SSP
539} // SchedRW && HasSHSTK
540
541let SchedRW = [WriteSystem], Predicates = [HasIBT]  in {
542    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
543    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
544} // SchedRW && HasIBT
545
546//===----------------------------------------------------------------------===//
547// XSAVE instructions
548let SchedRW = [WriteSystem] in {
549let Predicates = [HasXSAVE] in {
550let Defs = [EDX, EAX], Uses = [ECX] in
551  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
552
553let Uses = [EDX, EAX, ECX] in
554  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
555                "xsetbv",
556                [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
557
558} // HasXSAVE
559
560let Uses = [EDX, EAX] in {
561def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
562              "xsave\t$dst",
563              [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
564def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
565                 "xsave64\t$dst",
566                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
567def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
568               "xrstor\t$dst",
569               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
570def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
571                  "xrstor64\t$dst",
572                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
573def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
574                 "xsaveopt\t$dst",
575                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
576def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
577                    "xsaveopt64\t$dst",
578                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
579def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
580               "xsavec\t$dst",
581               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
582def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
583                 "xsavec64\t$dst",
584                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
585def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
586               "xsaves\t$dst",
587               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
588def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
589                  "xsaves64\t$dst",
590                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
591def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
592                "xrstors\t$dst",
593                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
594def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
595                   "xrstors64\t$dst",
596                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
597} // Uses
598} // SchedRW
599
600//===----------------------------------------------------------------------===//
601// VIA PadLock crypto instructions
602let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
603  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
604
605def : InstAlias<"xstorerng", (XSTORE)>;
606
607let SchedRW = [WriteSystem] in {
608let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
609  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
610  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
611  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
612  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
613  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
614}
615
616let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
617  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
618  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
619}
620let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
621  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
622} // SchedRW
623
624//==-----------------------------------------------------------------------===//
625// PKU  - enable protection key
626let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
627  def WRPKRU : PseudoI<(outs), (ins GR32:$src),
628                [(int_x86_wrpkru GR32:$src)]>;
629  def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
630                [(set GR32:$dst, (int_x86_rdpkru))]>;
631}
632
633let SchedRW = [WriteSystem] in {
634let Defs = [EAX, EDX], Uses = [ECX] in
635  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", [], IIC_PKU>, TB;
636let Uses = [EAX, ECX, EDX] in
637  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", [], IIC_PKU>, TB;
638} // SchedRW
639
640//===----------------------------------------------------------------------===//
641// FS/GS Base Instructions
642let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
643  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
644                   "rdfsbase{l}\t$dst",
645                   [(set GR32:$dst, (int_x86_rdfsbase_32))],
646                   IIC_SEGMENT_BASE_R>, XS;
647  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
648                     "rdfsbase{q}\t$dst",
649                     [(set GR64:$dst, (int_x86_rdfsbase_64))],
650                     IIC_SEGMENT_BASE_R>, XS;
651  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
652                   "rdgsbase{l}\t$dst",
653                   [(set GR32:$dst, (int_x86_rdgsbase_32))],
654                   IIC_SEGMENT_BASE_R>, XS;
655  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
656                     "rdgsbase{q}\t$dst",
657                     [(set GR64:$dst, (int_x86_rdgsbase_64))],
658                     IIC_SEGMENT_BASE_R>, XS;
659  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
660                   "wrfsbase{l}\t$src",
661                   [(int_x86_wrfsbase_32 GR32:$src)],
662                   IIC_SEGMENT_BASE_W>, XS;
663  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
664                      "wrfsbase{q}\t$src",
665                      [(int_x86_wrfsbase_64 GR64:$src)],
666                      IIC_SEGMENT_BASE_W>, XS;
667  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
668                   "wrgsbase{l}\t$src",
669                   [(int_x86_wrgsbase_32 GR32:$src)], IIC_SEGMENT_BASE_W>, XS;
670  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
671                      "wrgsbase{q}\t$src",
672                      [(int_x86_wrgsbase_64 GR64:$src)],
673                      IIC_SEGMENT_BASE_W>, XS;
674}
675
676//===----------------------------------------------------------------------===//
677// INVPCID Instruction
678let SchedRW = [WriteSystem] in {
679def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
680                "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
681                Requires<[Not64BitMode]>;
682def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
683                "invpcid\t{$src2, $src1|$src1, $src2}", [], IIC_INVPCID>, T8PD,
684                Requires<[In64BitMode]>;
685} // SchedRW
686
687//===----------------------------------------------------------------------===//
688// SMAP Instruction
689let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
690  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", [], IIC_SMAP>, TB;
691  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", [], IIC_SMAP>, TB;
692}
693
694//===----------------------------------------------------------------------===//
695// SMX Instruction
696let SchedRW = [WriteSystem] in {
697let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
698  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", [], IIC_SMX>, TB;
699} // Uses, Defs
700} // SchedRW
701
702//===----------------------------------------------------------------------===//
703// RDPID Instruction
704let SchedRW = [WriteSystem] in {
705def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
706              "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))], IIC_RDPID>, XS,
707              Requires<[Not64BitMode, HasRDPID]>;
708def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins),
709              "rdpid\t$dst", [], IIC_RDPID>, XS,
710              Requires<[In64BitMode, HasRDPID]>;
711} // SchedRW
712
713let Predicates = [In64BitMode, HasRDPID] in {
714  // Due to silly instruction definition, we have to compensate for the
715  // instruction outputing a 64-bit register.
716  def : Pat<(int_x86_rdpid),
717            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
718}
719
720
721//===----------------------------------------------------------------------===//
722// PTWRITE Instruction
723let SchedRW = [WriteSystem] in {
724
725def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
726                "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
727def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
728                    "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
729                    Requires<[In64BitMode]>;
730
731def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
732                 "ptwrite{l}\t$dst", [], IIC_PTWRITE>, XS;
733def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
734                    "ptwrite{q}\t$dst", [], IIC_PTWRITE>, XS,
735                    Requires<[In64BitMode]>;
736} // SchedRW
737