1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/IR/DebugInfoMetadata.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetOptions.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "x86-instr-info"
47 
48 #define GET_INSTRINFO_CTOR_DTOR
49 #include "X86GenInstrInfo.inc"
50 
51 static cl::opt<bool>
52     NoFusing("disable-spill-fusing",
53              cl::desc("Disable fusing of spill code into instructions"),
54              cl::Hidden);
55 static cl::opt<bool>
56 PrintFailedFusing("print-failed-fuse-candidates",
57                   cl::desc("Print instructions that the allocator wants to"
58                            " fuse, but the X86 backend currently can't"),
59                   cl::Hidden);
60 static cl::opt<bool>
61 ReMatPICStubLoad("remat-pic-stub-load",
62                  cl::desc("Re-materialize load from stub in PIC mode"),
63                  cl::init(false), cl::Hidden);
64 static cl::opt<unsigned>
65 PartialRegUpdateClearance("partial-reg-update-clearance",
66                           cl::desc("Clearance between two register writes "
67                                    "for inserting XOR to avoid partial "
68                                    "register update"),
69                           cl::init(64), cl::Hidden);
70 static cl::opt<unsigned>
71 UndefRegClearance("undef-reg-clearance",
72                   cl::desc("How many idle instructions we would like before "
73                            "certain undef register reads"),
74                   cl::init(128), cl::Hidden);
75 
76 
77 // Pin the vtable to this file.
78 void X86InstrInfo::anchor() {}
79 
80 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
81     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
82                                                : X86::ADJCALLSTACKDOWN32),
83                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
84                                                : X86::ADJCALLSTACKUP32),
85                       X86::CATCHRET,
86                       (STI.is64Bit() ? X86::RET64 : X86::RET32)),
87       Subtarget(STI), RI(STI.getTargetTriple()) {
88 }
89 
90 bool
91 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
92                                     Register &SrcReg, Register &DstReg,
93                                     unsigned &SubIdx) const {
94   switch (MI.getOpcode()) {
95   default: break;
96   case X86::MOVSX16rr8:
97   case X86::MOVZX16rr8:
98   case X86::MOVSX32rr8:
99   case X86::MOVZX32rr8:
100   case X86::MOVSX64rr8:
101     if (!Subtarget.is64Bit())
102       // It's not always legal to reference the low 8-bit of the larger
103       // register in 32-bit mode.
104       return false;
105     LLVM_FALLTHROUGH;
106   case X86::MOVSX32rr16:
107   case X86::MOVZX32rr16:
108   case X86::MOVSX64rr16:
109   case X86::MOVSX64rr32: {
110     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
111       // Be conservative.
112       return false;
113     SrcReg = MI.getOperand(1).getReg();
114     DstReg = MI.getOperand(0).getReg();
115     switch (MI.getOpcode()) {
116     default: llvm_unreachable("Unreachable!");
117     case X86::MOVSX16rr8:
118     case X86::MOVZX16rr8:
119     case X86::MOVSX32rr8:
120     case X86::MOVZX32rr8:
121     case X86::MOVSX64rr8:
122       SubIdx = X86::sub_8bit;
123       break;
124     case X86::MOVSX32rr16:
125     case X86::MOVZX32rr16:
126     case X86::MOVSX64rr16:
127       SubIdx = X86::sub_16bit;
128       break;
129     case X86::MOVSX64rr32:
130       SubIdx = X86::sub_32bit;
131       break;
132     }
133     return true;
134   }
135   }
136   return false;
137 }
138 
139 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
140   switch (MI.getOpcode()) {
141   default:
142     // By default, assume that the instruction is not data invariant.
143     return false;
144 
145     // Some target-independent operations that trivially lower to data-invariant
146     // instructions.
147   case TargetOpcode::COPY:
148   case TargetOpcode::INSERT_SUBREG:
149   case TargetOpcode::SUBREG_TO_REG:
150     return true;
151 
152   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
153   // However, they set flags and are perhaps the most surprisingly constant
154   // time operations so we call them out here separately.
155   case X86::IMUL16rr:
156   case X86::IMUL16rri8:
157   case X86::IMUL16rri:
158   case X86::IMUL32rr:
159   case X86::IMUL32rri8:
160   case X86::IMUL32rri:
161   case X86::IMUL64rr:
162   case X86::IMUL64rri32:
163   case X86::IMUL64rri8:
164 
165   // Bit scanning and counting instructions that are somewhat surprisingly
166   // constant time as they scan across bits and do other fairly complex
167   // operations like popcnt, but are believed to be constant time on x86.
168   // However, these set flags.
169   case X86::BSF16rr:
170   case X86::BSF32rr:
171   case X86::BSF64rr:
172   case X86::BSR16rr:
173   case X86::BSR32rr:
174   case X86::BSR64rr:
175   case X86::LZCNT16rr:
176   case X86::LZCNT32rr:
177   case X86::LZCNT64rr:
178   case X86::POPCNT16rr:
179   case X86::POPCNT32rr:
180   case X86::POPCNT64rr:
181   case X86::TZCNT16rr:
182   case X86::TZCNT32rr:
183   case X86::TZCNT64rr:
184 
185   // Bit manipulation instructions are effectively combinations of basic
186   // arithmetic ops, and should still execute in constant time. These also
187   // set flags.
188   case X86::BLCFILL32rr:
189   case X86::BLCFILL64rr:
190   case X86::BLCI32rr:
191   case X86::BLCI64rr:
192   case X86::BLCIC32rr:
193   case X86::BLCIC64rr:
194   case X86::BLCMSK32rr:
195   case X86::BLCMSK64rr:
196   case X86::BLCS32rr:
197   case X86::BLCS64rr:
198   case X86::BLSFILL32rr:
199   case X86::BLSFILL64rr:
200   case X86::BLSI32rr:
201   case X86::BLSI64rr:
202   case X86::BLSIC32rr:
203   case X86::BLSIC64rr:
204   case X86::BLSMSK32rr:
205   case X86::BLSMSK64rr:
206   case X86::BLSR32rr:
207   case X86::BLSR64rr:
208   case X86::TZMSK32rr:
209   case X86::TZMSK64rr:
210 
211   // Bit extracting and clearing instructions should execute in constant time,
212   // and set flags.
213   case X86::BEXTR32rr:
214   case X86::BEXTR64rr:
215   case X86::BEXTRI32ri:
216   case X86::BEXTRI64ri:
217   case X86::BZHI32rr:
218   case X86::BZHI64rr:
219 
220   // Shift and rotate.
221   case X86::ROL8r1:
222   case X86::ROL16r1:
223   case X86::ROL32r1:
224   case X86::ROL64r1:
225   case X86::ROL8rCL:
226   case X86::ROL16rCL:
227   case X86::ROL32rCL:
228   case X86::ROL64rCL:
229   case X86::ROL8ri:
230   case X86::ROL16ri:
231   case X86::ROL32ri:
232   case X86::ROL64ri:
233   case X86::ROR8r1:
234   case X86::ROR16r1:
235   case X86::ROR32r1:
236   case X86::ROR64r1:
237   case X86::ROR8rCL:
238   case X86::ROR16rCL:
239   case X86::ROR32rCL:
240   case X86::ROR64rCL:
241   case X86::ROR8ri:
242   case X86::ROR16ri:
243   case X86::ROR32ri:
244   case X86::ROR64ri:
245   case X86::SAR8r1:
246   case X86::SAR16r1:
247   case X86::SAR32r1:
248   case X86::SAR64r1:
249   case X86::SAR8rCL:
250   case X86::SAR16rCL:
251   case X86::SAR32rCL:
252   case X86::SAR64rCL:
253   case X86::SAR8ri:
254   case X86::SAR16ri:
255   case X86::SAR32ri:
256   case X86::SAR64ri:
257   case X86::SHL8r1:
258   case X86::SHL16r1:
259   case X86::SHL32r1:
260   case X86::SHL64r1:
261   case X86::SHL8rCL:
262   case X86::SHL16rCL:
263   case X86::SHL32rCL:
264   case X86::SHL64rCL:
265   case X86::SHL8ri:
266   case X86::SHL16ri:
267   case X86::SHL32ri:
268   case X86::SHL64ri:
269   case X86::SHR8r1:
270   case X86::SHR16r1:
271   case X86::SHR32r1:
272   case X86::SHR64r1:
273   case X86::SHR8rCL:
274   case X86::SHR16rCL:
275   case X86::SHR32rCL:
276   case X86::SHR64rCL:
277   case X86::SHR8ri:
278   case X86::SHR16ri:
279   case X86::SHR32ri:
280   case X86::SHR64ri:
281   case X86::SHLD16rrCL:
282   case X86::SHLD32rrCL:
283   case X86::SHLD64rrCL:
284   case X86::SHLD16rri8:
285   case X86::SHLD32rri8:
286   case X86::SHLD64rri8:
287   case X86::SHRD16rrCL:
288   case X86::SHRD32rrCL:
289   case X86::SHRD64rrCL:
290   case X86::SHRD16rri8:
291   case X86::SHRD32rri8:
292   case X86::SHRD64rri8:
293 
294   // Basic arithmetic is constant time on the input but does set flags.
295   case X86::ADC8rr:
296   case X86::ADC8ri:
297   case X86::ADC16rr:
298   case X86::ADC16ri:
299   case X86::ADC16ri8:
300   case X86::ADC32rr:
301   case X86::ADC32ri:
302   case X86::ADC32ri8:
303   case X86::ADC64rr:
304   case X86::ADC64ri8:
305   case X86::ADC64ri32:
306   case X86::ADD8rr:
307   case X86::ADD8ri:
308   case X86::ADD16rr:
309   case X86::ADD16ri:
310   case X86::ADD16ri8:
311   case X86::ADD32rr:
312   case X86::ADD32ri:
313   case X86::ADD32ri8:
314   case X86::ADD64rr:
315   case X86::ADD64ri8:
316   case X86::ADD64ri32:
317   case X86::AND8rr:
318   case X86::AND8ri:
319   case X86::AND16rr:
320   case X86::AND16ri:
321   case X86::AND16ri8:
322   case X86::AND32rr:
323   case X86::AND32ri:
324   case X86::AND32ri8:
325   case X86::AND64rr:
326   case X86::AND64ri8:
327   case X86::AND64ri32:
328   case X86::OR8rr:
329   case X86::OR8ri:
330   case X86::OR16rr:
331   case X86::OR16ri:
332   case X86::OR16ri8:
333   case X86::OR32rr:
334   case X86::OR32ri:
335   case X86::OR32ri8:
336   case X86::OR64rr:
337   case X86::OR64ri8:
338   case X86::OR64ri32:
339   case X86::SBB8rr:
340   case X86::SBB8ri:
341   case X86::SBB16rr:
342   case X86::SBB16ri:
343   case X86::SBB16ri8:
344   case X86::SBB32rr:
345   case X86::SBB32ri:
346   case X86::SBB32ri8:
347   case X86::SBB64rr:
348   case X86::SBB64ri8:
349   case X86::SBB64ri32:
350   case X86::SUB8rr:
351   case X86::SUB8ri:
352   case X86::SUB16rr:
353   case X86::SUB16ri:
354   case X86::SUB16ri8:
355   case X86::SUB32rr:
356   case X86::SUB32ri:
357   case X86::SUB32ri8:
358   case X86::SUB64rr:
359   case X86::SUB64ri8:
360   case X86::SUB64ri32:
361   case X86::XOR8rr:
362   case X86::XOR8ri:
363   case X86::XOR16rr:
364   case X86::XOR16ri:
365   case X86::XOR16ri8:
366   case X86::XOR32rr:
367   case X86::XOR32ri:
368   case X86::XOR32ri8:
369   case X86::XOR64rr:
370   case X86::XOR64ri8:
371   case X86::XOR64ri32:
372   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
373   case X86::ADCX32rr:
374   case X86::ADCX64rr:
375   case X86::ADOX32rr:
376   case X86::ADOX64rr:
377   case X86::ANDN32rr:
378   case X86::ANDN64rr:
379   // Unary arithmetic operations.
380   case X86::DEC8r:
381   case X86::DEC16r:
382   case X86::DEC32r:
383   case X86::DEC64r:
384   case X86::INC8r:
385   case X86::INC16r:
386   case X86::INC32r:
387   case X86::INC64r:
388   case X86::NEG8r:
389   case X86::NEG16r:
390   case X86::NEG32r:
391   case X86::NEG64r:
392 
393   // Unlike other arithmetic, NOT doesn't set EFLAGS.
394   case X86::NOT8r:
395   case X86::NOT16r:
396   case X86::NOT32r:
397   case X86::NOT64r:
398 
399   // Various move instructions used to zero or sign extend things. Note that we
400   // intentionally don't support the _NOREX variants as we can't handle that
401   // register constraint anyways.
402   case X86::MOVSX16rr8:
403   case X86::MOVSX32rr8:
404   case X86::MOVSX32rr16:
405   case X86::MOVSX64rr8:
406   case X86::MOVSX64rr16:
407   case X86::MOVSX64rr32:
408   case X86::MOVZX16rr8:
409   case X86::MOVZX32rr8:
410   case X86::MOVZX32rr16:
411   case X86::MOVZX64rr8:
412   case X86::MOVZX64rr16:
413   case X86::MOV32rr:
414 
415   // Arithmetic instructions that are both constant time and don't set flags.
416   case X86::RORX32ri:
417   case X86::RORX64ri:
418   case X86::SARX32rr:
419   case X86::SARX64rr:
420   case X86::SHLX32rr:
421   case X86::SHLX64rr:
422   case X86::SHRX32rr:
423   case X86::SHRX64rr:
424 
425   // LEA doesn't actually access memory, and its arithmetic is constant time.
426   case X86::LEA16r:
427   case X86::LEA32r:
428   case X86::LEA64_32r:
429   case X86::LEA64r:
430     return true;
431   }
432 }
433 
434 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
435   switch (MI.getOpcode()) {
436   default:
437     // By default, assume that the load will immediately leak.
438     return false;
439 
440   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
441   // However, they set flags and are perhaps the most surprisingly constant
442   // time operations so we call them out here separately.
443   case X86::IMUL16rm:
444   case X86::IMUL16rmi8:
445   case X86::IMUL16rmi:
446   case X86::IMUL32rm:
447   case X86::IMUL32rmi8:
448   case X86::IMUL32rmi:
449   case X86::IMUL64rm:
450   case X86::IMUL64rmi32:
451   case X86::IMUL64rmi8:
452 
453   // Bit scanning and counting instructions that are somewhat surprisingly
454   // constant time as they scan across bits and do other fairly complex
455   // operations like popcnt, but are believed to be constant time on x86.
456   // However, these set flags.
457   case X86::BSF16rm:
458   case X86::BSF32rm:
459   case X86::BSF64rm:
460   case X86::BSR16rm:
461   case X86::BSR32rm:
462   case X86::BSR64rm:
463   case X86::LZCNT16rm:
464   case X86::LZCNT32rm:
465   case X86::LZCNT64rm:
466   case X86::POPCNT16rm:
467   case X86::POPCNT32rm:
468   case X86::POPCNT64rm:
469   case X86::TZCNT16rm:
470   case X86::TZCNT32rm:
471   case X86::TZCNT64rm:
472 
473   // Bit manipulation instructions are effectively combinations of basic
474   // arithmetic ops, and should still execute in constant time. These also
475   // set flags.
476   case X86::BLCFILL32rm:
477   case X86::BLCFILL64rm:
478   case X86::BLCI32rm:
479   case X86::BLCI64rm:
480   case X86::BLCIC32rm:
481   case X86::BLCIC64rm:
482   case X86::BLCMSK32rm:
483   case X86::BLCMSK64rm:
484   case X86::BLCS32rm:
485   case X86::BLCS64rm:
486   case X86::BLSFILL32rm:
487   case X86::BLSFILL64rm:
488   case X86::BLSI32rm:
489   case X86::BLSI64rm:
490   case X86::BLSIC32rm:
491   case X86::BLSIC64rm:
492   case X86::BLSMSK32rm:
493   case X86::BLSMSK64rm:
494   case X86::BLSR32rm:
495   case X86::BLSR64rm:
496   case X86::TZMSK32rm:
497   case X86::TZMSK64rm:
498 
499   // Bit extracting and clearing instructions should execute in constant time,
500   // and set flags.
501   case X86::BEXTR32rm:
502   case X86::BEXTR64rm:
503   case X86::BEXTRI32mi:
504   case X86::BEXTRI64mi:
505   case X86::BZHI32rm:
506   case X86::BZHI64rm:
507 
508   // Basic arithmetic is constant time on the input but does set flags.
509   case X86::ADC8rm:
510   case X86::ADC16rm:
511   case X86::ADC32rm:
512   case X86::ADC64rm:
513   case X86::ADCX32rm:
514   case X86::ADCX64rm:
515   case X86::ADD8rm:
516   case X86::ADD16rm:
517   case X86::ADD32rm:
518   case X86::ADD64rm:
519   case X86::ADOX32rm:
520   case X86::ADOX64rm:
521   case X86::AND8rm:
522   case X86::AND16rm:
523   case X86::AND32rm:
524   case X86::AND64rm:
525   case X86::ANDN32rm:
526   case X86::ANDN64rm:
527   case X86::OR8rm:
528   case X86::OR16rm:
529   case X86::OR32rm:
530   case X86::OR64rm:
531   case X86::SBB8rm:
532   case X86::SBB16rm:
533   case X86::SBB32rm:
534   case X86::SBB64rm:
535   case X86::SUB8rm:
536   case X86::SUB16rm:
537   case X86::SUB32rm:
538   case X86::SUB64rm:
539   case X86::XOR8rm:
540   case X86::XOR16rm:
541   case X86::XOR32rm:
542   case X86::XOR64rm:
543 
544   // Integer multiply w/o affecting flags is still believed to be constant
545   // time on x86. Called out separately as this is among the most surprising
546   // instructions to exhibit that behavior.
547   case X86::MULX32rm:
548   case X86::MULX64rm:
549 
550   // Arithmetic instructions that are both constant time and don't set flags.
551   case X86::RORX32mi:
552   case X86::RORX64mi:
553   case X86::SARX32rm:
554   case X86::SARX64rm:
555   case X86::SHLX32rm:
556   case X86::SHLX64rm:
557   case X86::SHRX32rm:
558   case X86::SHRX64rm:
559 
560   // Conversions are believed to be constant time and don't set flags.
561   case X86::CVTTSD2SI64rm:
562   case X86::VCVTTSD2SI64rm:
563   case X86::VCVTTSD2SI64Zrm:
564   case X86::CVTTSD2SIrm:
565   case X86::VCVTTSD2SIrm:
566   case X86::VCVTTSD2SIZrm:
567   case X86::CVTTSS2SI64rm:
568   case X86::VCVTTSS2SI64rm:
569   case X86::VCVTTSS2SI64Zrm:
570   case X86::CVTTSS2SIrm:
571   case X86::VCVTTSS2SIrm:
572   case X86::VCVTTSS2SIZrm:
573   case X86::CVTSI2SDrm:
574   case X86::VCVTSI2SDrm:
575   case X86::VCVTSI2SDZrm:
576   case X86::CVTSI2SSrm:
577   case X86::VCVTSI2SSrm:
578   case X86::VCVTSI2SSZrm:
579   case X86::CVTSI642SDrm:
580   case X86::VCVTSI642SDrm:
581   case X86::VCVTSI642SDZrm:
582   case X86::CVTSI642SSrm:
583   case X86::VCVTSI642SSrm:
584   case X86::VCVTSI642SSZrm:
585   case X86::CVTSS2SDrm:
586   case X86::VCVTSS2SDrm:
587   case X86::VCVTSS2SDZrm:
588   case X86::CVTSD2SSrm:
589   case X86::VCVTSD2SSrm:
590   case X86::VCVTSD2SSZrm:
591   // AVX512 added unsigned integer conversions.
592   case X86::VCVTTSD2USI64Zrm:
593   case X86::VCVTTSD2USIZrm:
594   case X86::VCVTTSS2USI64Zrm:
595   case X86::VCVTTSS2USIZrm:
596   case X86::VCVTUSI2SDZrm:
597   case X86::VCVTUSI642SDZrm:
598   case X86::VCVTUSI2SSZrm:
599   case X86::VCVTUSI642SSZrm:
600 
601   // Loads to register don't set flags.
602   case X86::MOV8rm:
603   case X86::MOV8rm_NOREX:
604   case X86::MOV16rm:
605   case X86::MOV32rm:
606   case X86::MOV64rm:
607   case X86::MOVSX16rm8:
608   case X86::MOVSX32rm16:
609   case X86::MOVSX32rm8:
610   case X86::MOVSX32rm8_NOREX:
611   case X86::MOVSX64rm16:
612   case X86::MOVSX64rm32:
613   case X86::MOVSX64rm8:
614   case X86::MOVZX16rm8:
615   case X86::MOVZX32rm16:
616   case X86::MOVZX32rm8:
617   case X86::MOVZX32rm8_NOREX:
618   case X86::MOVZX64rm16:
619   case X86::MOVZX64rm8:
620     return true;
621   }
622 }
623 
624 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
625   const MachineFunction *MF = MI.getParent()->getParent();
626   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
627 
628   if (isFrameInstr(MI)) {
629     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
630     SPAdj -= getFrameAdjustment(MI);
631     if (!isFrameSetup(MI))
632       SPAdj = -SPAdj;
633     return SPAdj;
634   }
635 
636   // To know whether a call adjusts the stack, we need information
637   // that is bound to the following ADJCALLSTACKUP pseudo.
638   // Look for the next ADJCALLSTACKUP that follows the call.
639   if (MI.isCall()) {
640     const MachineBasicBlock *MBB = MI.getParent();
641     auto I = ++MachineBasicBlock::const_iterator(MI);
642     for (auto E = MBB->end(); I != E; ++I) {
643       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
644           I->isCall())
645         break;
646     }
647 
648     // If we could not find a frame destroy opcode, then it has already
649     // been simplified, so we don't care.
650     if (I->getOpcode() != getCallFrameDestroyOpcode())
651       return 0;
652 
653     return -(I->getOperand(1).getImm());
654   }
655 
656   // Currently handle only PUSHes we can reasonably expect to see
657   // in call sequences
658   switch (MI.getOpcode()) {
659   default:
660     return 0;
661   case X86::PUSH32i8:
662   case X86::PUSH32r:
663   case X86::PUSH32rmm:
664   case X86::PUSH32rmr:
665   case X86::PUSHi32:
666     return 4;
667   case X86::PUSH64i8:
668   case X86::PUSH64r:
669   case X86::PUSH64rmm:
670   case X86::PUSH64rmr:
671   case X86::PUSH64i32:
672     return 8;
673   }
674 }
675 
676 /// Return true and the FrameIndex if the specified
677 /// operand and follow operands form a reference to the stack frame.
678 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
679                                   int &FrameIndex) const {
680   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
681       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
682       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
683       MI.getOperand(Op + X86::AddrDisp).isImm() &&
684       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
685       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
686       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
687     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
688     return true;
689   }
690   return false;
691 }
692 
693 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
694   switch (Opcode) {
695   default:
696     return false;
697   case X86::MOV8rm:
698   case X86::KMOVBkm:
699     MemBytes = 1;
700     return true;
701   case X86::MOV16rm:
702   case X86::KMOVWkm:
703   case X86::VMOVSHZrm:
704   case X86::VMOVSHZrm_alt:
705     MemBytes = 2;
706     return true;
707   case X86::MOV32rm:
708   case X86::MOVSSrm:
709   case X86::MOVSSrm_alt:
710   case X86::VMOVSSrm:
711   case X86::VMOVSSrm_alt:
712   case X86::VMOVSSZrm:
713   case X86::VMOVSSZrm_alt:
714   case X86::KMOVDkm:
715     MemBytes = 4;
716     return true;
717   case X86::MOV64rm:
718   case X86::LD_Fp64m:
719   case X86::MOVSDrm:
720   case X86::MOVSDrm_alt:
721   case X86::VMOVSDrm:
722   case X86::VMOVSDrm_alt:
723   case X86::VMOVSDZrm:
724   case X86::VMOVSDZrm_alt:
725   case X86::MMX_MOVD64rm:
726   case X86::MMX_MOVQ64rm:
727   case X86::KMOVQkm:
728     MemBytes = 8;
729     return true;
730   case X86::MOVAPSrm:
731   case X86::MOVUPSrm:
732   case X86::MOVAPDrm:
733   case X86::MOVUPDrm:
734   case X86::MOVDQArm:
735   case X86::MOVDQUrm:
736   case X86::VMOVAPSrm:
737   case X86::VMOVUPSrm:
738   case X86::VMOVAPDrm:
739   case X86::VMOVUPDrm:
740   case X86::VMOVDQArm:
741   case X86::VMOVDQUrm:
742   case X86::VMOVAPSZ128rm:
743   case X86::VMOVUPSZ128rm:
744   case X86::VMOVAPSZ128rm_NOVLX:
745   case X86::VMOVUPSZ128rm_NOVLX:
746   case X86::VMOVAPDZ128rm:
747   case X86::VMOVUPDZ128rm:
748   case X86::VMOVDQU8Z128rm:
749   case X86::VMOVDQU16Z128rm:
750   case X86::VMOVDQA32Z128rm:
751   case X86::VMOVDQU32Z128rm:
752   case X86::VMOVDQA64Z128rm:
753   case X86::VMOVDQU64Z128rm:
754     MemBytes = 16;
755     return true;
756   case X86::VMOVAPSYrm:
757   case X86::VMOVUPSYrm:
758   case X86::VMOVAPDYrm:
759   case X86::VMOVUPDYrm:
760   case X86::VMOVDQAYrm:
761   case X86::VMOVDQUYrm:
762   case X86::VMOVAPSZ256rm:
763   case X86::VMOVUPSZ256rm:
764   case X86::VMOVAPSZ256rm_NOVLX:
765   case X86::VMOVUPSZ256rm_NOVLX:
766   case X86::VMOVAPDZ256rm:
767   case X86::VMOVUPDZ256rm:
768   case X86::VMOVDQU8Z256rm:
769   case X86::VMOVDQU16Z256rm:
770   case X86::VMOVDQA32Z256rm:
771   case X86::VMOVDQU32Z256rm:
772   case X86::VMOVDQA64Z256rm:
773   case X86::VMOVDQU64Z256rm:
774     MemBytes = 32;
775     return true;
776   case X86::VMOVAPSZrm:
777   case X86::VMOVUPSZrm:
778   case X86::VMOVAPDZrm:
779   case X86::VMOVUPDZrm:
780   case X86::VMOVDQU8Zrm:
781   case X86::VMOVDQU16Zrm:
782   case X86::VMOVDQA32Zrm:
783   case X86::VMOVDQU32Zrm:
784   case X86::VMOVDQA64Zrm:
785   case X86::VMOVDQU64Zrm:
786     MemBytes = 64;
787     return true;
788   }
789 }
790 
791 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
792   switch (Opcode) {
793   default:
794     return false;
795   case X86::MOV8mr:
796   case X86::KMOVBmk:
797     MemBytes = 1;
798     return true;
799   case X86::MOV16mr:
800   case X86::KMOVWmk:
801   case X86::VMOVSHZmr:
802     MemBytes = 2;
803     return true;
804   case X86::MOV32mr:
805   case X86::MOVSSmr:
806   case X86::VMOVSSmr:
807   case X86::VMOVSSZmr:
808   case X86::KMOVDmk:
809     MemBytes = 4;
810     return true;
811   case X86::MOV64mr:
812   case X86::ST_FpP64m:
813   case X86::MOVSDmr:
814   case X86::VMOVSDmr:
815   case X86::VMOVSDZmr:
816   case X86::MMX_MOVD64mr:
817   case X86::MMX_MOVQ64mr:
818   case X86::MMX_MOVNTQmr:
819   case X86::KMOVQmk:
820     MemBytes = 8;
821     return true;
822   case X86::MOVAPSmr:
823   case X86::MOVUPSmr:
824   case X86::MOVAPDmr:
825   case X86::MOVUPDmr:
826   case X86::MOVDQAmr:
827   case X86::MOVDQUmr:
828   case X86::VMOVAPSmr:
829   case X86::VMOVUPSmr:
830   case X86::VMOVAPDmr:
831   case X86::VMOVUPDmr:
832   case X86::VMOVDQAmr:
833   case X86::VMOVDQUmr:
834   case X86::VMOVUPSZ128mr:
835   case X86::VMOVAPSZ128mr:
836   case X86::VMOVUPSZ128mr_NOVLX:
837   case X86::VMOVAPSZ128mr_NOVLX:
838   case X86::VMOVUPDZ128mr:
839   case X86::VMOVAPDZ128mr:
840   case X86::VMOVDQA32Z128mr:
841   case X86::VMOVDQU32Z128mr:
842   case X86::VMOVDQA64Z128mr:
843   case X86::VMOVDQU64Z128mr:
844   case X86::VMOVDQU8Z128mr:
845   case X86::VMOVDQU16Z128mr:
846     MemBytes = 16;
847     return true;
848   case X86::VMOVUPSYmr:
849   case X86::VMOVAPSYmr:
850   case X86::VMOVUPDYmr:
851   case X86::VMOVAPDYmr:
852   case X86::VMOVDQUYmr:
853   case X86::VMOVDQAYmr:
854   case X86::VMOVUPSZ256mr:
855   case X86::VMOVAPSZ256mr:
856   case X86::VMOVUPSZ256mr_NOVLX:
857   case X86::VMOVAPSZ256mr_NOVLX:
858   case X86::VMOVUPDZ256mr:
859   case X86::VMOVAPDZ256mr:
860   case X86::VMOVDQU8Z256mr:
861   case X86::VMOVDQU16Z256mr:
862   case X86::VMOVDQA32Z256mr:
863   case X86::VMOVDQU32Z256mr:
864   case X86::VMOVDQA64Z256mr:
865   case X86::VMOVDQU64Z256mr:
866     MemBytes = 32;
867     return true;
868   case X86::VMOVUPSZmr:
869   case X86::VMOVAPSZmr:
870   case X86::VMOVUPDZmr:
871   case X86::VMOVAPDZmr:
872   case X86::VMOVDQU8Zmr:
873   case X86::VMOVDQU16Zmr:
874   case X86::VMOVDQA32Zmr:
875   case X86::VMOVDQU32Zmr:
876   case X86::VMOVDQA64Zmr:
877   case X86::VMOVDQU64Zmr:
878     MemBytes = 64;
879     return true;
880   }
881   return false;
882 }
883 
884 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
885                                            int &FrameIndex) const {
886   unsigned Dummy;
887   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
888 }
889 
890 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
891                                            int &FrameIndex,
892                                            unsigned &MemBytes) const {
893   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
894     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
895       return MI.getOperand(0).getReg();
896   return 0;
897 }
898 
899 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
900                                                  int &FrameIndex) const {
901   unsigned Dummy;
902   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
903     unsigned Reg;
904     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
905       return Reg;
906     // Check for post-frame index elimination operations
907     SmallVector<const MachineMemOperand *, 1> Accesses;
908     if (hasLoadFromStackSlot(MI, Accesses)) {
909       FrameIndex =
910           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
911               ->getFrameIndex();
912       return MI.getOperand(0).getReg();
913     }
914   }
915   return 0;
916 }
917 
918 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
919                                           int &FrameIndex) const {
920   unsigned Dummy;
921   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
922 }
923 
924 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
925                                           int &FrameIndex,
926                                           unsigned &MemBytes) const {
927   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
928     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
929         isFrameOperand(MI, 0, FrameIndex))
930       return MI.getOperand(X86::AddrNumOperands).getReg();
931   return 0;
932 }
933 
934 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
935                                                 int &FrameIndex) const {
936   unsigned Dummy;
937   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
938     unsigned Reg;
939     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
940       return Reg;
941     // Check for post-frame index elimination operations
942     SmallVector<const MachineMemOperand *, 1> Accesses;
943     if (hasStoreToStackSlot(MI, Accesses)) {
944       FrameIndex =
945           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
946               ->getFrameIndex();
947       return MI.getOperand(X86::AddrNumOperands).getReg();
948     }
949   }
950   return 0;
951 }
952 
953 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
954 static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
955   // Don't waste compile time scanning use-def chains of physregs.
956   if (!BaseReg.isVirtual())
957     return false;
958   bool isPICBase = false;
959   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
960          E = MRI.def_instr_end(); I != E; ++I) {
961     MachineInstr *DefMI = &*I;
962     if (DefMI->getOpcode() != X86::MOVPC32r)
963       return false;
964     assert(!isPICBase && "More than one PIC base?");
965     isPICBase = true;
966   }
967   return isPICBase;
968 }
969 
970 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
971                                                      AAResults *AA) const {
972   switch (MI.getOpcode()) {
973   default:
974     // This function should only be called for opcodes with the ReMaterializable
975     // flag set.
976     llvm_unreachable("Unknown rematerializable operation!");
977     break;
978 
979   case X86::LOAD_STACK_GUARD:
980   case X86::AVX1_SETALLONES:
981   case X86::AVX2_SETALLONES:
982   case X86::AVX512_128_SET0:
983   case X86::AVX512_256_SET0:
984   case X86::AVX512_512_SET0:
985   case X86::AVX512_512_SETALLONES:
986   case X86::AVX512_FsFLD0SD:
987   case X86::AVX512_FsFLD0SH:
988   case X86::AVX512_FsFLD0SS:
989   case X86::AVX512_FsFLD0F128:
990   case X86::AVX_SET0:
991   case X86::FsFLD0SD:
992   case X86::FsFLD0SS:
993   case X86::FsFLD0F128:
994   case X86::KSET0D:
995   case X86::KSET0Q:
996   case X86::KSET0W:
997   case X86::KSET1D:
998   case X86::KSET1Q:
999   case X86::KSET1W:
1000   case X86::MMX_SET0:
1001   case X86::MOV32ImmSExti8:
1002   case X86::MOV32r0:
1003   case X86::MOV32r1:
1004   case X86::MOV32r_1:
1005   case X86::MOV32ri64:
1006   case X86::MOV64ImmSExti8:
1007   case X86::V_SET0:
1008   case X86::V_SETALLONES:
1009   case X86::MOV16ri:
1010   case X86::MOV32ri:
1011   case X86::MOV64ri:
1012   case X86::MOV64ri32:
1013   case X86::MOV8ri:
1014   case X86::PTILEZEROV:
1015     return true;
1016 
1017   case X86::MOV8rm:
1018   case X86::MOV8rm_NOREX:
1019   case X86::MOV16rm:
1020   case X86::MOV32rm:
1021   case X86::MOV64rm:
1022   case X86::MOVSSrm:
1023   case X86::MOVSSrm_alt:
1024   case X86::MOVSDrm:
1025   case X86::MOVSDrm_alt:
1026   case X86::MOVAPSrm:
1027   case X86::MOVUPSrm:
1028   case X86::MOVAPDrm:
1029   case X86::MOVUPDrm:
1030   case X86::MOVDQArm:
1031   case X86::MOVDQUrm:
1032   case X86::VMOVSSrm:
1033   case X86::VMOVSSrm_alt:
1034   case X86::VMOVSDrm:
1035   case X86::VMOVSDrm_alt:
1036   case X86::VMOVAPSrm:
1037   case X86::VMOVUPSrm:
1038   case X86::VMOVAPDrm:
1039   case X86::VMOVUPDrm:
1040   case X86::VMOVDQArm:
1041   case X86::VMOVDQUrm:
1042   case X86::VMOVAPSYrm:
1043   case X86::VMOVUPSYrm:
1044   case X86::VMOVAPDYrm:
1045   case X86::VMOVUPDYrm:
1046   case X86::VMOVDQAYrm:
1047   case X86::VMOVDQUYrm:
1048   case X86::MMX_MOVD64rm:
1049   case X86::MMX_MOVQ64rm:
1050   // AVX-512
1051   case X86::VMOVSSZrm:
1052   case X86::VMOVSSZrm_alt:
1053   case X86::VMOVSDZrm:
1054   case X86::VMOVSDZrm_alt:
1055   case X86::VMOVSHZrm:
1056   case X86::VMOVSHZrm_alt:
1057   case X86::VMOVAPDZ128rm:
1058   case X86::VMOVAPDZ256rm:
1059   case X86::VMOVAPDZrm:
1060   case X86::VMOVAPSZ128rm:
1061   case X86::VMOVAPSZ256rm:
1062   case X86::VMOVAPSZ128rm_NOVLX:
1063   case X86::VMOVAPSZ256rm_NOVLX:
1064   case X86::VMOVAPSZrm:
1065   case X86::VMOVDQA32Z128rm:
1066   case X86::VMOVDQA32Z256rm:
1067   case X86::VMOVDQA32Zrm:
1068   case X86::VMOVDQA64Z128rm:
1069   case X86::VMOVDQA64Z256rm:
1070   case X86::VMOVDQA64Zrm:
1071   case X86::VMOVDQU16Z128rm:
1072   case X86::VMOVDQU16Z256rm:
1073   case X86::VMOVDQU16Zrm:
1074   case X86::VMOVDQU32Z128rm:
1075   case X86::VMOVDQU32Z256rm:
1076   case X86::VMOVDQU32Zrm:
1077   case X86::VMOVDQU64Z128rm:
1078   case X86::VMOVDQU64Z256rm:
1079   case X86::VMOVDQU64Zrm:
1080   case X86::VMOVDQU8Z128rm:
1081   case X86::VMOVDQU8Z256rm:
1082   case X86::VMOVDQU8Zrm:
1083   case X86::VMOVUPDZ128rm:
1084   case X86::VMOVUPDZ256rm:
1085   case X86::VMOVUPDZrm:
1086   case X86::VMOVUPSZ128rm:
1087   case X86::VMOVUPSZ256rm:
1088   case X86::VMOVUPSZ128rm_NOVLX:
1089   case X86::VMOVUPSZ256rm_NOVLX:
1090   case X86::VMOVUPSZrm: {
1091     // Loads from constant pools are trivially rematerializable.
1092     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1093         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1094         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1095         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1096         MI.isDereferenceableInvariantLoad(AA)) {
1097       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1098       if (BaseReg == 0 || BaseReg == X86::RIP)
1099         return true;
1100       // Allow re-materialization of PIC load.
1101       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1102         return false;
1103       const MachineFunction &MF = *MI.getParent()->getParent();
1104       const MachineRegisterInfo &MRI = MF.getRegInfo();
1105       return regIsPICBase(BaseReg, MRI);
1106     }
1107     return false;
1108   }
1109 
1110   case X86::LEA32r:
1111   case X86::LEA64r: {
1112     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1113         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1114         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1115         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1116       // lea fi#, lea GV, etc. are all rematerializable.
1117       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1118         return true;
1119       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1120       if (BaseReg == 0)
1121         return true;
1122       // Allow re-materialization of lea PICBase + x.
1123       const MachineFunction &MF = *MI.getParent()->getParent();
1124       const MachineRegisterInfo &MRI = MF.getRegInfo();
1125       return regIsPICBase(BaseReg, MRI);
1126     }
1127     return false;
1128   }
1129   }
1130 }
1131 
1132 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1133                                  MachineBasicBlock::iterator I,
1134                                  Register DestReg, unsigned SubIdx,
1135                                  const MachineInstr &Orig,
1136                                  const TargetRegisterInfo &TRI) const {
1137   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1138   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
1139                             MachineBasicBlock::LQR_Dead) {
1140     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1141     // effects.
1142     int Value;
1143     switch (Orig.getOpcode()) {
1144     case X86::MOV32r0:  Value = 0; break;
1145     case X86::MOV32r1:  Value = 1; break;
1146     case X86::MOV32r_1: Value = -1; break;
1147     default:
1148       llvm_unreachable("Unexpected instruction!");
1149     }
1150 
1151     const DebugLoc &DL = Orig.getDebugLoc();
1152     BuildMI(MBB, I, DL, get(X86::MOV32ri))
1153         .add(Orig.getOperand(0))
1154         .addImm(Value);
1155   } else {
1156     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1157     MBB.insert(I, MI);
1158   }
1159 
1160   MachineInstr &NewMI = *std::prev(I);
1161   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1162 }
1163 
1164 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1165 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1166   for (const MachineOperand &MO : MI.operands()) {
1167     if (MO.isReg() && MO.isDef() &&
1168         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1169       return true;
1170     }
1171   }
1172   return false;
1173 }
1174 
1175 /// Check whether the shift count for a machine operand is non-zero.
1176 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1177                                               unsigned ShiftAmtOperandIdx) {
1178   // The shift count is six bits with the REX.W prefix and five bits without.
1179   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1180   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1181   return Imm & ShiftCountMask;
1182 }
1183 
1184 /// Check whether the given shift count is appropriate
1185 /// can be represented by a LEA instruction.
1186 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1187   // Left shift instructions can be transformed into load-effective-address
1188   // instructions if we can encode them appropriately.
1189   // A LEA instruction utilizes a SIB byte to encode its scale factor.
1190   // The SIB.scale field is two bits wide which means that we can encode any
1191   // shift amount less than 4.
1192   return ShAmt < 4 && ShAmt > 0;
1193 }
1194 
1195 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1196                                   unsigned Opc, bool AllowSP, Register &NewSrc,
1197                                   bool &isKill, MachineOperand &ImplicitOp,
1198                                   LiveVariables *LV, LiveIntervals *LIS) const {
1199   MachineFunction &MF = *MI.getParent()->getParent();
1200   const TargetRegisterClass *RC;
1201   if (AllowSP) {
1202     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1203   } else {
1204     RC = Opc != X86::LEA32r ?
1205       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1206   }
1207   Register SrcReg = Src.getReg();
1208   isKill = MI.killsRegister(SrcReg);
1209 
1210   // For both LEA64 and LEA32 the register already has essentially the right
1211   // type (32-bit or 64-bit) we may just need to forbid SP.
1212   if (Opc != X86::LEA64_32r) {
1213     NewSrc = SrcReg;
1214     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1215 
1216     if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1217       return false;
1218 
1219     return true;
1220   }
1221 
1222   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1223   // another we need to add 64-bit registers to the final MI.
1224   if (SrcReg.isPhysical()) {
1225     ImplicitOp = Src;
1226     ImplicitOp.setImplicit();
1227 
1228     NewSrc = getX86SubSuperRegister(SrcReg, 64);
1229     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1230   } else {
1231     // Virtual register of the wrong class, we have to create a temporary 64-bit
1232     // vreg to feed into the LEA.
1233     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1234     MachineInstr *Copy =
1235         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1236             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1237             .addReg(SrcReg, getKillRegState(isKill));
1238 
1239     // Which is obviously going to be dead after we're done with it.
1240     isKill = true;
1241 
1242     if (LV)
1243       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1244 
1245     if (LIS) {
1246       SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(*Copy);
1247       SlotIndex Idx = LIS->getInstructionIndex(MI);
1248       LiveInterval &LI = LIS->getInterval(SrcReg);
1249       LiveRange::Segment *S = LI.getSegmentContaining(Idx);
1250       if (S->end.getBaseIndex() == Idx)
1251         S->end = CopyIdx.getRegSlot();
1252     }
1253   }
1254 
1255   // We've set all the parameters without issue.
1256   return true;
1257 }
1258 
1259 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1260                                                          MachineInstr &MI,
1261                                                          LiveVariables *LV,
1262                                                          LiveIntervals *LIS,
1263                                                          bool Is8BitOp) const {
1264   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1265   MachineBasicBlock &MBB = *MI.getParent();
1266   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1267   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1268               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1269          "Unexpected type for LEA transform");
1270 
1271   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1272   // something like this:
1273   //   Opcode = X86::LEA32r;
1274   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1275   //   OutRegLEA =
1276   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1277   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1278   if (!Subtarget.is64Bit())
1279     return nullptr;
1280 
1281   unsigned Opcode = X86::LEA64_32r;
1282   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1283   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1284   Register InRegLEA2;
1285 
1286   // Build and insert into an implicit UNDEF value. This is OK because
1287   // we will be shifting and then extracting the lower 8/16-bits.
1288   // This has the potential to cause partial register stall. e.g.
1289   //   movw    (%rbp,%rcx,2), %dx
1290   //   leal    -65(%rdx), %esi
1291   // But testing has shown this *does* help performance in 64-bit mode (at
1292   // least on modern x86 machines).
1293   MachineBasicBlock::iterator MBBI = MI.getIterator();
1294   Register Dest = MI.getOperand(0).getReg();
1295   Register Src = MI.getOperand(1).getReg();
1296   Register Src2;
1297   bool IsDead = MI.getOperand(0).isDead();
1298   bool IsKill = MI.getOperand(1).isKill();
1299   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1300   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1301   MachineInstr *ImpDef =
1302       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1303   MachineInstr *InsMI =
1304       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1305           .addReg(InRegLEA, RegState::Define, SubReg)
1306           .addReg(Src, getKillRegState(IsKill));
1307   MachineInstr *ImpDef2 = nullptr;
1308   MachineInstr *InsMI2 = nullptr;
1309 
1310   MachineInstrBuilder MIB =
1311       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1312   switch (MIOpc) {
1313   default: llvm_unreachable("Unreachable!");
1314   case X86::SHL8ri:
1315   case X86::SHL16ri: {
1316     unsigned ShAmt = MI.getOperand(2).getImm();
1317     MIB.addReg(0).addImm(1ULL << ShAmt)
1318        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1319     break;
1320   }
1321   case X86::INC8r:
1322   case X86::INC16r:
1323     addRegOffset(MIB, InRegLEA, true, 1);
1324     break;
1325   case X86::DEC8r:
1326   case X86::DEC16r:
1327     addRegOffset(MIB, InRegLEA, true, -1);
1328     break;
1329   case X86::ADD8ri:
1330   case X86::ADD8ri_DB:
1331   case X86::ADD16ri:
1332   case X86::ADD16ri8:
1333   case X86::ADD16ri_DB:
1334   case X86::ADD16ri8_DB:
1335     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1336     break;
1337   case X86::ADD8rr:
1338   case X86::ADD8rr_DB:
1339   case X86::ADD16rr:
1340   case X86::ADD16rr_DB: {
1341     Src2 = MI.getOperand(2).getReg();
1342     bool IsKill2 = MI.getOperand(2).isKill();
1343     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1344     if (Src == Src2) {
1345       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1346       // just a single insert_subreg.
1347       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1348     } else {
1349       if (Subtarget.is64Bit())
1350         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1351       else
1352         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1353       // Build and insert into an implicit UNDEF value. This is OK because
1354       // we will be shifting and then extracting the lower 8/16-bits.
1355       ImpDef2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF),
1356                         InRegLEA2);
1357       InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1358                    .addReg(InRegLEA2, RegState::Define, SubReg)
1359                    .addReg(Src2, getKillRegState(IsKill2));
1360       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1361     }
1362     if (LV && IsKill2 && InsMI2)
1363       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1364     break;
1365   }
1366   }
1367 
1368   MachineInstr *NewMI = MIB;
1369   MachineInstr *ExtMI =
1370       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1371           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1372           .addReg(OutRegLEA, RegState::Kill, SubReg);
1373 
1374   if (LV) {
1375     // Update live variables.
1376     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1377     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1378     if (IsKill)
1379       LV->replaceKillInstruction(Src, MI, *InsMI);
1380     if (IsDead)
1381       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1382   }
1383 
1384   if (LIS) {
1385     LIS->InsertMachineInstrInMaps(*ImpDef);
1386     SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI);
1387     if (ImpDef2)
1388       LIS->InsertMachineInstrInMaps(*ImpDef2);
1389     SlotIndex Ins2Idx;
1390     if (InsMI2)
1391       Ins2Idx = LIS->InsertMachineInstrInMaps(*InsMI2);
1392     SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1393     SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(*ExtMI);
1394     LIS->getInterval(InRegLEA);
1395     LIS->getInterval(OutRegLEA);
1396     if (InRegLEA2)
1397       LIS->getInterval(InRegLEA2);
1398 
1399     // Move the use of Src up to InsMI.
1400     LiveInterval &SrcLI = LIS->getInterval(Src);
1401     LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(NewIdx);
1402     if (SrcSeg->end == NewIdx.getRegSlot())
1403       SrcSeg->end = InsIdx.getRegSlot();
1404 
1405     if (InsMI2) {
1406       // Move the use of Src2 up to InsMI2.
1407       LiveInterval &Src2LI = LIS->getInterval(Src2);
1408       LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(NewIdx);
1409       if (Src2Seg->end == NewIdx.getRegSlot())
1410         Src2Seg->end = Ins2Idx.getRegSlot();
1411     }
1412 
1413     // Move the definition of Dest down to ExtMI.
1414     LiveInterval &DestLI = LIS->getInterval(Dest);
1415     LiveRange::Segment *DestSeg =
1416         DestLI.getSegmentContaining(NewIdx.getRegSlot());
1417     assert(DestSeg->start == NewIdx.getRegSlot() &&
1418            DestSeg->valno->def == NewIdx.getRegSlot());
1419     DestSeg->start = ExtIdx.getRegSlot();
1420     DestSeg->valno->def = ExtIdx.getRegSlot();
1421   }
1422 
1423   return ExtMI;
1424 }
1425 
1426 /// This method must be implemented by targets that
1427 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1428 /// may be able to convert a two-address instruction into a true
1429 /// three-address instruction on demand.  This allows the X86 target (for
1430 /// example) to convert ADD and SHL instructions into LEA instructions if they
1431 /// would require register copies due to two-addressness.
1432 ///
1433 /// This method returns a null pointer if the transformation cannot be
1434 /// performed, otherwise it returns the new instruction.
1435 ///
1436 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1437                                                   LiveVariables *LV,
1438                                                   LiveIntervals *LIS) const {
1439   // The following opcodes also sets the condition code register(s). Only
1440   // convert them to equivalent lea if the condition code register def's
1441   // are dead!
1442   if (hasLiveCondCodeDef(MI))
1443     return nullptr;
1444 
1445   MachineFunction &MF = *MI.getParent()->getParent();
1446   // All instructions input are two-addr instructions.  Get the known operands.
1447   const MachineOperand &Dest = MI.getOperand(0);
1448   const MachineOperand &Src = MI.getOperand(1);
1449 
1450   // Ideally, operations with undef should be folded before we get here, but we
1451   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1452   // Without this, we have to forward undef state to new register operands to
1453   // avoid machine verifier errors.
1454   if (Src.isUndef())
1455     return nullptr;
1456   if (MI.getNumOperands() > 2)
1457     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1458       return nullptr;
1459 
1460   MachineInstr *NewMI = nullptr;
1461   Register SrcReg, SrcReg2;
1462   bool Is64Bit = Subtarget.is64Bit();
1463 
1464   bool Is8BitOp = false;
1465   unsigned MIOpc = MI.getOpcode();
1466   switch (MIOpc) {
1467   default: llvm_unreachable("Unreachable!");
1468   case X86::SHL64ri: {
1469     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1470     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1471     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1472 
1473     // LEA can't handle RSP.
1474     if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1475                                         Src.getReg(), &X86::GR64_NOSPRegClass))
1476       return nullptr;
1477 
1478     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1479                 .add(Dest)
1480                 .addReg(0)
1481                 .addImm(1ULL << ShAmt)
1482                 .add(Src)
1483                 .addImm(0)
1484                 .addReg(0);
1485     break;
1486   }
1487   case X86::SHL32ri: {
1488     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1489     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1490     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1491 
1492     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1493 
1494     // LEA can't handle ESP.
1495     bool isKill;
1496     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1497     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1498                         ImplicitOp, LV, LIS))
1499       return nullptr;
1500 
1501     MachineInstrBuilder MIB =
1502         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1503             .add(Dest)
1504             .addReg(0)
1505             .addImm(1ULL << ShAmt)
1506             .addReg(SrcReg, getKillRegState(isKill))
1507             .addImm(0)
1508             .addReg(0);
1509     if (ImplicitOp.getReg() != 0)
1510       MIB.add(ImplicitOp);
1511     NewMI = MIB;
1512 
1513     break;
1514   }
1515   case X86::SHL8ri:
1516     Is8BitOp = true;
1517     LLVM_FALLTHROUGH;
1518   case X86::SHL16ri: {
1519     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1520     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1521     if (!isTruncatedShiftCountForLEA(ShAmt))
1522       return nullptr;
1523     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1524   }
1525   case X86::INC64r:
1526   case X86::INC32r: {
1527     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1528     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1529         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1530     bool isKill;
1531     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1532     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1533                         ImplicitOp, LV, LIS))
1534       return nullptr;
1535 
1536     MachineInstrBuilder MIB =
1537         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1538             .add(Dest)
1539             .addReg(SrcReg, getKillRegState(isKill));
1540     if (ImplicitOp.getReg() != 0)
1541       MIB.add(ImplicitOp);
1542 
1543     NewMI = addOffset(MIB, 1);
1544     break;
1545   }
1546   case X86::DEC64r:
1547   case X86::DEC32r: {
1548     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1549     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1550         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1551 
1552     bool isKill;
1553     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1554     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1555                         ImplicitOp, LV, LIS))
1556       return nullptr;
1557 
1558     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1559                                   .add(Dest)
1560                                   .addReg(SrcReg, getKillRegState(isKill));
1561     if (ImplicitOp.getReg() != 0)
1562       MIB.add(ImplicitOp);
1563 
1564     NewMI = addOffset(MIB, -1);
1565 
1566     break;
1567   }
1568   case X86::DEC8r:
1569   case X86::INC8r:
1570     Is8BitOp = true;
1571     LLVM_FALLTHROUGH;
1572   case X86::DEC16r:
1573   case X86::INC16r:
1574     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1575   case X86::ADD64rr:
1576   case X86::ADD64rr_DB:
1577   case X86::ADD32rr:
1578   case X86::ADD32rr_DB: {
1579     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1580     unsigned Opc;
1581     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1582       Opc = X86::LEA64r;
1583     else
1584       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1585 
1586     const MachineOperand &Src2 = MI.getOperand(2);
1587     bool isKill2;
1588     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1589     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/false, SrcReg2, isKill2,
1590                         ImplicitOp2, LV, LIS))
1591       return nullptr;
1592 
1593     bool isKill;
1594     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1595     if (Src.getReg() == Src2.getReg()) {
1596       // Don't call classify LEAReg a second time on the same register, in case
1597       // the first call inserted a COPY from Src2 and marked it as killed.
1598       isKill = isKill2;
1599       SrcReg = SrcReg2;
1600     } else {
1601       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1602                           ImplicitOp, LV, LIS))
1603         return nullptr;
1604     }
1605 
1606     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1607     if (ImplicitOp.getReg() != 0)
1608       MIB.add(ImplicitOp);
1609     if (ImplicitOp2.getReg() != 0)
1610       MIB.add(ImplicitOp2);
1611 
1612     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1613     if (LV && Src2.isKill())
1614       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1615     break;
1616   }
1617   case X86::ADD8rr:
1618   case X86::ADD8rr_DB:
1619     Is8BitOp = true;
1620     LLVM_FALLTHROUGH;
1621   case X86::ADD16rr:
1622   case X86::ADD16rr_DB:
1623     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1624   case X86::ADD64ri32:
1625   case X86::ADD64ri8:
1626   case X86::ADD64ri32_DB:
1627   case X86::ADD64ri8_DB:
1628     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1629     NewMI = addOffset(
1630         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1631         MI.getOperand(2));
1632     break;
1633   case X86::ADD32ri:
1634   case X86::ADD32ri8:
1635   case X86::ADD32ri_DB:
1636   case X86::ADD32ri8_DB: {
1637     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1638     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1639 
1640     bool isKill;
1641     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1642     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1643                         ImplicitOp, LV, LIS))
1644       return nullptr;
1645 
1646     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1647                                   .add(Dest)
1648                                   .addReg(SrcReg, getKillRegState(isKill));
1649     if (ImplicitOp.getReg() != 0)
1650       MIB.add(ImplicitOp);
1651 
1652     NewMI = addOffset(MIB, MI.getOperand(2));
1653     break;
1654   }
1655   case X86::ADD8ri:
1656   case X86::ADD8ri_DB:
1657     Is8BitOp = true;
1658     LLVM_FALLTHROUGH;
1659   case X86::ADD16ri:
1660   case X86::ADD16ri8:
1661   case X86::ADD16ri_DB:
1662   case X86::ADD16ri8_DB:
1663     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1664   case X86::SUB8ri:
1665   case X86::SUB16ri8:
1666   case X86::SUB16ri:
1667     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1668     return nullptr;
1669   case X86::SUB32ri8:
1670   case X86::SUB32ri: {
1671     if (!MI.getOperand(2).isImm())
1672       return nullptr;
1673     int64_t Imm = MI.getOperand(2).getImm();
1674     if (!isInt<32>(-Imm))
1675       return nullptr;
1676 
1677     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1678     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1679 
1680     bool isKill;
1681     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1682     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1683                         ImplicitOp, LV, LIS))
1684       return nullptr;
1685 
1686     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1687                                   .add(Dest)
1688                                   .addReg(SrcReg, getKillRegState(isKill));
1689     if (ImplicitOp.getReg() != 0)
1690       MIB.add(ImplicitOp);
1691 
1692     NewMI = addOffset(MIB, -Imm);
1693     break;
1694   }
1695 
1696   case X86::SUB64ri8:
1697   case X86::SUB64ri32: {
1698     if (!MI.getOperand(2).isImm())
1699       return nullptr;
1700     int64_t Imm = MI.getOperand(2).getImm();
1701     if (!isInt<32>(-Imm))
1702       return nullptr;
1703 
1704     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1705 
1706     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1707                                       get(X86::LEA64r)).add(Dest).add(Src);
1708     NewMI = addOffset(MIB, -Imm);
1709     break;
1710   }
1711 
1712   case X86::VMOVDQU8Z128rmk:
1713   case X86::VMOVDQU8Z256rmk:
1714   case X86::VMOVDQU8Zrmk:
1715   case X86::VMOVDQU16Z128rmk:
1716   case X86::VMOVDQU16Z256rmk:
1717   case X86::VMOVDQU16Zrmk:
1718   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1719   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1720   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1721   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1722   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1723   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1724   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1725   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1726   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1727   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1728   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1729   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1730   case X86::VBROADCASTSDZ256rmk:
1731   case X86::VBROADCASTSDZrmk:
1732   case X86::VBROADCASTSSZ128rmk:
1733   case X86::VBROADCASTSSZ256rmk:
1734   case X86::VBROADCASTSSZrmk:
1735   case X86::VPBROADCASTDZ128rmk:
1736   case X86::VPBROADCASTDZ256rmk:
1737   case X86::VPBROADCASTDZrmk:
1738   case X86::VPBROADCASTQZ128rmk:
1739   case X86::VPBROADCASTQZ256rmk:
1740   case X86::VPBROADCASTQZrmk: {
1741     unsigned Opc;
1742     switch (MIOpc) {
1743     default: llvm_unreachable("Unreachable!");
1744     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1745     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1746     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1747     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1748     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1749     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1750     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1751     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1752     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1753     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1754     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1755     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1756     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1757     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1758     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1759     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1760     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1761     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1762     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1763     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1764     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1765     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1766     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1767     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1768     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1769     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1770     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1771     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1772     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1773     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1774     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1775     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1776     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1777     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1778     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1779     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1780     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1781     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1782     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1783     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1784     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1785     }
1786 
1787     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1788               .add(Dest)
1789               .add(MI.getOperand(2))
1790               .add(Src)
1791               .add(MI.getOperand(3))
1792               .add(MI.getOperand(4))
1793               .add(MI.getOperand(5))
1794               .add(MI.getOperand(6))
1795               .add(MI.getOperand(7));
1796     break;
1797   }
1798 
1799   case X86::VMOVDQU8Z128rrk:
1800   case X86::VMOVDQU8Z256rrk:
1801   case X86::VMOVDQU8Zrrk:
1802   case X86::VMOVDQU16Z128rrk:
1803   case X86::VMOVDQU16Z256rrk:
1804   case X86::VMOVDQU16Zrrk:
1805   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1806   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1807   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1808   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1809   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1810   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1811   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1812   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1813   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1814   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1815   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1816   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1817     unsigned Opc;
1818     switch (MIOpc) {
1819     default: llvm_unreachable("Unreachable!");
1820     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1821     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1822     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1823     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1824     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1825     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1826     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1827     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1828     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1829     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1830     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1831     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1832     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1833     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1834     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1835     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1836     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1837     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1838     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1839     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1840     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1841     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1842     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1843     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1844     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1845     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1846     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1847     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1848     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1849     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1850     }
1851 
1852     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1853               .add(Dest)
1854               .add(MI.getOperand(2))
1855               .add(Src)
1856               .add(MI.getOperand(3));
1857     break;
1858   }
1859   }
1860 
1861   if (!NewMI) return nullptr;
1862 
1863   if (LV) {  // Update live variables
1864     if (Src.isKill())
1865       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1866     if (Dest.isDead())
1867       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1868   }
1869 
1870   MachineBasicBlock &MBB = *MI.getParent();
1871   MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
1872 
1873   if (LIS) {
1874     LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1875     if (SrcReg)
1876       LIS->getInterval(SrcReg);
1877     if (SrcReg2)
1878       LIS->getInterval(SrcReg2);
1879   }
1880 
1881   return NewMI;
1882 }
1883 
1884 /// This determines which of three possible cases of a three source commute
1885 /// the source indexes correspond to taking into account any mask operands.
1886 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1887 /// possible.
1888 /// Case 0 - Possible to commute the first and second operands.
1889 /// Case 1 - Possible to commute the first and third operands.
1890 /// Case 2 - Possible to commute the second and third operands.
1891 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1892                                        unsigned SrcOpIdx2) {
1893   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1894   if (SrcOpIdx1 > SrcOpIdx2)
1895     std::swap(SrcOpIdx1, SrcOpIdx2);
1896 
1897   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1898   if (X86II::isKMasked(TSFlags)) {
1899     Op2++;
1900     Op3++;
1901   }
1902 
1903   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1904     return 0;
1905   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1906     return 1;
1907   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1908     return 2;
1909   llvm_unreachable("Unknown three src commute case.");
1910 }
1911 
1912 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1913     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1914     const X86InstrFMA3Group &FMA3Group) const {
1915 
1916   unsigned Opc = MI.getOpcode();
1917 
1918   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1919   // analysis. The commute optimization is legal only if all users of FMA*_Int
1920   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1921   // not implemented yet. So, just return 0 in that case.
1922   // When such analysis are available this place will be the right place for
1923   // calling it.
1924   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1925          "Intrinsic instructions can't commute operand 1");
1926 
1927   // Determine which case this commute is or if it can't be done.
1928   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1929                                          SrcOpIdx2);
1930   assert(Case < 3 && "Unexpected case number!");
1931 
1932   // Define the FMA forms mapping array that helps to map input FMA form
1933   // to output FMA form to preserve the operation semantics after
1934   // commuting the operands.
1935   const unsigned Form132Index = 0;
1936   const unsigned Form213Index = 1;
1937   const unsigned Form231Index = 2;
1938   static const unsigned FormMapping[][3] = {
1939     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1940     // FMA132 A, C, b; ==> FMA231 C, A, b;
1941     // FMA213 B, A, c; ==> FMA213 A, B, c;
1942     // FMA231 C, A, b; ==> FMA132 A, C, b;
1943     { Form231Index, Form213Index, Form132Index },
1944     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1945     // FMA132 A, c, B; ==> FMA132 B, c, A;
1946     // FMA213 B, a, C; ==> FMA231 C, a, B;
1947     // FMA231 C, a, B; ==> FMA213 B, a, C;
1948     { Form132Index, Form231Index, Form213Index },
1949     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1950     // FMA132 a, C, B; ==> FMA213 a, B, C;
1951     // FMA213 b, A, C; ==> FMA132 b, C, A;
1952     // FMA231 c, A, B; ==> FMA231 c, B, A;
1953     { Form213Index, Form132Index, Form231Index }
1954   };
1955 
1956   unsigned FMAForms[3];
1957   FMAForms[0] = FMA3Group.get132Opcode();
1958   FMAForms[1] = FMA3Group.get213Opcode();
1959   FMAForms[2] = FMA3Group.get231Opcode();
1960 
1961   // Everything is ready, just adjust the FMA opcode and return it.
1962   for (unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
1963     if (Opc == FMAForms[FormIndex])
1964       return FMAForms[FormMapping[Case][FormIndex]];
1965 
1966   llvm_unreachable("Illegal FMA3 format");
1967 }
1968 
1969 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1970                              unsigned SrcOpIdx2) {
1971   // Determine which case this commute is or if it can't be done.
1972   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1973                                          SrcOpIdx2);
1974   assert(Case < 3 && "Unexpected case value!");
1975 
1976   // For each case we need to swap two pairs of bits in the final immediate.
1977   static const uint8_t SwapMasks[3][4] = {
1978     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1979     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1980     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1981   };
1982 
1983   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1984   // Clear out the bits we are swapping.
1985   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1986                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1987   // If the immediate had a bit of the pair set, then set the opposite bit.
1988   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1989   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1990   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1991   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1992   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1993 }
1994 
1995 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1996 // commuted.
1997 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1998 #define VPERM_CASES(Suffix) \
1999   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
2000   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
2001   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
2002   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
2003   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
2004   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
2005   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
2006   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
2007   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
2008   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
2009   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
2010   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
2011 
2012 #define VPERM_CASES_BROADCAST(Suffix) \
2013   VPERM_CASES(Suffix) \
2014   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
2015   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
2016   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
2017   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
2018   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
2019   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
2020 
2021   switch (Opcode) {
2022   default: return false;
2023   VPERM_CASES(B)
2024   VPERM_CASES_BROADCAST(D)
2025   VPERM_CASES_BROADCAST(PD)
2026   VPERM_CASES_BROADCAST(PS)
2027   VPERM_CASES_BROADCAST(Q)
2028   VPERM_CASES(W)
2029     return true;
2030   }
2031 #undef VPERM_CASES_BROADCAST
2032 #undef VPERM_CASES
2033 }
2034 
2035 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
2036 // from the I opcode to the T opcode and vice versa.
2037 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
2038 #define VPERM_CASES(Orig, New) \
2039   case X86::Orig##128rr:    return X86::New##128rr;   \
2040   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
2041   case X86::Orig##128rm:    return X86::New##128rm;   \
2042   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
2043   case X86::Orig##256rr:    return X86::New##256rr;   \
2044   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
2045   case X86::Orig##256rm:    return X86::New##256rm;   \
2046   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
2047   case X86::Orig##rr:       return X86::New##rr;      \
2048   case X86::Orig##rrkz:     return X86::New##rrkz;    \
2049   case X86::Orig##rm:       return X86::New##rm;      \
2050   case X86::Orig##rmkz:     return X86::New##rmkz;
2051 
2052 #define VPERM_CASES_BROADCAST(Orig, New) \
2053   VPERM_CASES(Orig, New) \
2054   case X86::Orig##128rmb:   return X86::New##128rmb;   \
2055   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
2056   case X86::Orig##256rmb:   return X86::New##256rmb;   \
2057   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
2058   case X86::Orig##rmb:      return X86::New##rmb;      \
2059   case X86::Orig##rmbkz:    return X86::New##rmbkz;
2060 
2061   switch (Opcode) {
2062   VPERM_CASES(VPERMI2B, VPERMT2B)
2063   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
2064   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
2065   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
2066   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
2067   VPERM_CASES(VPERMI2W, VPERMT2W)
2068   VPERM_CASES(VPERMT2B, VPERMI2B)
2069   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
2070   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2071   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2072   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
2073   VPERM_CASES(VPERMT2W, VPERMI2W)
2074   }
2075 
2076   llvm_unreachable("Unreachable!");
2077 #undef VPERM_CASES_BROADCAST
2078 #undef VPERM_CASES
2079 }
2080 
2081 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2082                                                    unsigned OpIdx1,
2083                                                    unsigned OpIdx2) const {
2084   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2085     if (NewMI)
2086       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2087     return MI;
2088   };
2089 
2090   switch (MI.getOpcode()) {
2091   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2092   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2093   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2094   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2095   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2096   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2097     unsigned Opc;
2098     unsigned Size;
2099     switch (MI.getOpcode()) {
2100     default: llvm_unreachable("Unreachable!");
2101     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2102     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2103     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2104     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2105     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2106     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2107     }
2108     unsigned Amt = MI.getOperand(3).getImm();
2109     auto &WorkingMI = cloneIfNew(MI);
2110     WorkingMI.setDesc(get(Opc));
2111     WorkingMI.getOperand(3).setImm(Size - Amt);
2112     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2113                                                    OpIdx1, OpIdx2);
2114   }
2115   case X86::PFSUBrr:
2116   case X86::PFSUBRrr: {
2117     // PFSUB  x, y: x = x - y
2118     // PFSUBR x, y: x = y - x
2119     unsigned Opc =
2120         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2121     auto &WorkingMI = cloneIfNew(MI);
2122     WorkingMI.setDesc(get(Opc));
2123     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2124                                                    OpIdx1, OpIdx2);
2125   }
2126   case X86::BLENDPDrri:
2127   case X86::BLENDPSrri:
2128   case X86::VBLENDPDrri:
2129   case X86::VBLENDPSrri:
2130     // If we're optimizing for size, try to use MOVSD/MOVSS.
2131     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2132       unsigned Mask, Opc;
2133       switch (MI.getOpcode()) {
2134       default: llvm_unreachable("Unreachable!");
2135       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
2136       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
2137       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2138       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2139       }
2140       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2141         auto &WorkingMI = cloneIfNew(MI);
2142         WorkingMI.setDesc(get(Opc));
2143         WorkingMI.removeOperand(3);
2144         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2145                                                        /*NewMI=*/false,
2146                                                        OpIdx1, OpIdx2);
2147       }
2148     }
2149     LLVM_FALLTHROUGH;
2150   case X86::PBLENDWrri:
2151   case X86::VBLENDPDYrri:
2152   case X86::VBLENDPSYrri:
2153   case X86::VPBLENDDrri:
2154   case X86::VPBLENDWrri:
2155   case X86::VPBLENDDYrri:
2156   case X86::VPBLENDWYrri:{
2157     int8_t Mask;
2158     switch (MI.getOpcode()) {
2159     default: llvm_unreachable("Unreachable!");
2160     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
2161     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
2162     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
2163     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
2164     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
2165     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
2166     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
2167     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
2168     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
2169     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
2170     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
2171     }
2172     // Only the least significant bits of Imm are used.
2173     // Using int8_t to ensure it will be sign extended to the int64_t that
2174     // setImm takes in order to match isel behavior.
2175     int8_t Imm = MI.getOperand(3).getImm() & Mask;
2176     auto &WorkingMI = cloneIfNew(MI);
2177     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2178     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2179                                                    OpIdx1, OpIdx2);
2180   }
2181   case X86::INSERTPSrr:
2182   case X86::VINSERTPSrr:
2183   case X86::VINSERTPSZrr: {
2184     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2185     unsigned ZMask = Imm & 15;
2186     unsigned DstIdx = (Imm >> 4) & 3;
2187     unsigned SrcIdx = (Imm >> 6) & 3;
2188 
2189     // We can commute insertps if we zero 2 of the elements, the insertion is
2190     // "inline" and we don't override the insertion with a zero.
2191     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2192         countPopulation(ZMask) == 2) {
2193       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2194       assert(AltIdx < 4 && "Illegal insertion index");
2195       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2196       auto &WorkingMI = cloneIfNew(MI);
2197       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2198       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2199                                                      OpIdx1, OpIdx2);
2200     }
2201     return nullptr;
2202   }
2203   case X86::MOVSDrr:
2204   case X86::MOVSSrr:
2205   case X86::VMOVSDrr:
2206   case X86::VMOVSSrr:{
2207     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2208     if (Subtarget.hasSSE41()) {
2209       unsigned Mask, Opc;
2210       switch (MI.getOpcode()) {
2211       default: llvm_unreachable("Unreachable!");
2212       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
2213       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
2214       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2215       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2216       }
2217 
2218       auto &WorkingMI = cloneIfNew(MI);
2219       WorkingMI.setDesc(get(Opc));
2220       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2221       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2222                                                      OpIdx1, OpIdx2);
2223     }
2224 
2225     // Convert to SHUFPD.
2226     assert(MI.getOpcode() == X86::MOVSDrr &&
2227            "Can only commute MOVSDrr without SSE4.1");
2228 
2229     auto &WorkingMI = cloneIfNew(MI);
2230     WorkingMI.setDesc(get(X86::SHUFPDrri));
2231     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2232     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2233                                                    OpIdx1, OpIdx2);
2234   }
2235   case X86::SHUFPDrri: {
2236     // Commute to MOVSD.
2237     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2238     auto &WorkingMI = cloneIfNew(MI);
2239     WorkingMI.setDesc(get(X86::MOVSDrr));
2240     WorkingMI.removeOperand(3);
2241     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2242                                                    OpIdx1, OpIdx2);
2243   }
2244   case X86::PCLMULQDQrr:
2245   case X86::VPCLMULQDQrr:
2246   case X86::VPCLMULQDQYrr:
2247   case X86::VPCLMULQDQZrr:
2248   case X86::VPCLMULQDQZ128rr:
2249   case X86::VPCLMULQDQZ256rr: {
2250     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2251     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2252     unsigned Imm = MI.getOperand(3).getImm();
2253     unsigned Src1Hi = Imm & 0x01;
2254     unsigned Src2Hi = Imm & 0x10;
2255     auto &WorkingMI = cloneIfNew(MI);
2256     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2257     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2258                                                    OpIdx1, OpIdx2);
2259   }
2260   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2261   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2262   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2263   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2264   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2265   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2266   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2267   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2268   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2269   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2270   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2271   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2272   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2273   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2274   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2275   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2276   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2277   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2278   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2279   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2280   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2281   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2282   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2283   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2284     // Flip comparison mode immediate (if necessary).
2285     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2286     Imm = X86::getSwappedVPCMPImm(Imm);
2287     auto &WorkingMI = cloneIfNew(MI);
2288     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2289     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2290                                                    OpIdx1, OpIdx2);
2291   }
2292   case X86::VPCOMBri: case X86::VPCOMUBri:
2293   case X86::VPCOMDri: case X86::VPCOMUDri:
2294   case X86::VPCOMQri: case X86::VPCOMUQri:
2295   case X86::VPCOMWri: case X86::VPCOMUWri: {
2296     // Flip comparison mode immediate (if necessary).
2297     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2298     Imm = X86::getSwappedVPCOMImm(Imm);
2299     auto &WorkingMI = cloneIfNew(MI);
2300     WorkingMI.getOperand(3).setImm(Imm);
2301     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2302                                                    OpIdx1, OpIdx2);
2303   }
2304   case X86::VCMPSDZrr:
2305   case X86::VCMPSSZrr:
2306   case X86::VCMPPDZrri:
2307   case X86::VCMPPSZrri:
2308   case X86::VCMPSHZrr:
2309   case X86::VCMPPHZrri:
2310   case X86::VCMPPHZ128rri:
2311   case X86::VCMPPHZ256rri:
2312   case X86::VCMPPDZ128rri:
2313   case X86::VCMPPSZ128rri:
2314   case X86::VCMPPDZ256rri:
2315   case X86::VCMPPSZ256rri:
2316   case X86::VCMPPDZrrik:
2317   case X86::VCMPPSZrrik:
2318   case X86::VCMPPDZ128rrik:
2319   case X86::VCMPPSZ128rrik:
2320   case X86::VCMPPDZ256rrik:
2321   case X86::VCMPPSZ256rrik: {
2322     unsigned Imm =
2323                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2324     Imm = X86::getSwappedVCMPImm(Imm);
2325     auto &WorkingMI = cloneIfNew(MI);
2326     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2327     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2328                                                    OpIdx1, OpIdx2);
2329   }
2330   case X86::VPERM2F128rr:
2331   case X86::VPERM2I128rr: {
2332     // Flip permute source immediate.
2333     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2334     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2335     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2336     auto &WorkingMI = cloneIfNew(MI);
2337     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2338     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2339                                                    OpIdx1, OpIdx2);
2340   }
2341   case X86::MOVHLPSrr:
2342   case X86::UNPCKHPDrr:
2343   case X86::VMOVHLPSrr:
2344   case X86::VUNPCKHPDrr:
2345   case X86::VMOVHLPSZrr:
2346   case X86::VUNPCKHPDZ128rr: {
2347     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2348 
2349     unsigned Opc = MI.getOpcode();
2350     switch (Opc) {
2351     default: llvm_unreachable("Unreachable!");
2352     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2353     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2354     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2355     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2356     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2357     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2358     }
2359     auto &WorkingMI = cloneIfNew(MI);
2360     WorkingMI.setDesc(get(Opc));
2361     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2362                                                    OpIdx1, OpIdx2);
2363   }
2364   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2365     auto &WorkingMI = cloneIfNew(MI);
2366     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2367     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2368     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2369     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2370                                                    OpIdx1, OpIdx2);
2371   }
2372   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2373   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2374   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2375   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2376   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2377   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2378   case X86::VPTERNLOGDZrrik:
2379   case X86::VPTERNLOGDZ128rrik:
2380   case X86::VPTERNLOGDZ256rrik:
2381   case X86::VPTERNLOGQZrrik:
2382   case X86::VPTERNLOGQZ128rrik:
2383   case X86::VPTERNLOGQZ256rrik:
2384   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2385   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2386   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2387   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2388   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2389   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2390   case X86::VPTERNLOGDZ128rmbi:
2391   case X86::VPTERNLOGDZ256rmbi:
2392   case X86::VPTERNLOGDZrmbi:
2393   case X86::VPTERNLOGQZ128rmbi:
2394   case X86::VPTERNLOGQZ256rmbi:
2395   case X86::VPTERNLOGQZrmbi:
2396   case X86::VPTERNLOGDZ128rmbikz:
2397   case X86::VPTERNLOGDZ256rmbikz:
2398   case X86::VPTERNLOGDZrmbikz:
2399   case X86::VPTERNLOGQZ128rmbikz:
2400   case X86::VPTERNLOGQZ256rmbikz:
2401   case X86::VPTERNLOGQZrmbikz: {
2402     auto &WorkingMI = cloneIfNew(MI);
2403     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2404     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2405                                                    OpIdx1, OpIdx2);
2406   }
2407   default: {
2408     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2409       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2410       auto &WorkingMI = cloneIfNew(MI);
2411       WorkingMI.setDesc(get(Opc));
2412       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2413                                                      OpIdx1, OpIdx2);
2414     }
2415 
2416     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2417                                                       MI.getDesc().TSFlags);
2418     if (FMA3Group) {
2419       unsigned Opc =
2420         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2421       auto &WorkingMI = cloneIfNew(MI);
2422       WorkingMI.setDesc(get(Opc));
2423       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2424                                                      OpIdx1, OpIdx2);
2425     }
2426 
2427     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2428   }
2429   }
2430 }
2431 
2432 bool
2433 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2434                                             unsigned &SrcOpIdx1,
2435                                             unsigned &SrcOpIdx2,
2436                                             bool IsIntrinsic) const {
2437   uint64_t TSFlags = MI.getDesc().TSFlags;
2438 
2439   unsigned FirstCommutableVecOp = 1;
2440   unsigned LastCommutableVecOp = 3;
2441   unsigned KMaskOp = -1U;
2442   if (X86II::isKMasked(TSFlags)) {
2443     // For k-zero-masked operations it is Ok to commute the first vector
2444     // operand. Unless this is an intrinsic instruction.
2445     // For regular k-masked operations a conservative choice is done as the
2446     // elements of the first vector operand, for which the corresponding bit
2447     // in the k-mask operand is set to 0, are copied to the result of the
2448     // instruction.
2449     // TODO/FIXME: The commute still may be legal if it is known that the
2450     // k-mask operand is set to either all ones or all zeroes.
2451     // It is also Ok to commute the 1st operand if all users of MI use only
2452     // the elements enabled by the k-mask operand. For example,
2453     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2454     //                                                     : v1[i];
2455     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2456     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2457 
2458     // The k-mask operand has index = 2 for masked and zero-masked operations.
2459     KMaskOp = 2;
2460 
2461     // The operand with index = 1 is used as a source for those elements for
2462     // which the corresponding bit in the k-mask is set to 0.
2463     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2464       FirstCommutableVecOp = 3;
2465 
2466     LastCommutableVecOp++;
2467   } else if (IsIntrinsic) {
2468     // Commuting the first operand of an intrinsic instruction isn't possible
2469     // unless we can prove that only the lowest element of the result is used.
2470     FirstCommutableVecOp = 2;
2471   }
2472 
2473   if (isMem(MI, LastCommutableVecOp))
2474     LastCommutableVecOp--;
2475 
2476   // Only the first RegOpsNum operands are commutable.
2477   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2478   // that the operand is not specified/fixed.
2479   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2480       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2481        SrcOpIdx1 == KMaskOp))
2482     return false;
2483   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2484       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2485        SrcOpIdx2 == KMaskOp))
2486     return false;
2487 
2488   // Look for two different register operands assumed to be commutable
2489   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2490   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2491       SrcOpIdx2 == CommuteAnyOperandIndex) {
2492     unsigned CommutableOpIdx2 = SrcOpIdx2;
2493 
2494     // At least one of operands to be commuted is not specified and
2495     // this method is free to choose appropriate commutable operands.
2496     if (SrcOpIdx1 == SrcOpIdx2)
2497       // Both of operands are not fixed. By default set one of commutable
2498       // operands to the last register operand of the instruction.
2499       CommutableOpIdx2 = LastCommutableVecOp;
2500     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2501       // Only one of operands is not fixed.
2502       CommutableOpIdx2 = SrcOpIdx1;
2503 
2504     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2505     // operand and assign its index to CommutableOpIdx1.
2506     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2507 
2508     unsigned CommutableOpIdx1;
2509     for (CommutableOpIdx1 = LastCommutableVecOp;
2510          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2511       // Just ignore and skip the k-mask operand.
2512       if (CommutableOpIdx1 == KMaskOp)
2513         continue;
2514 
2515       // The commuted operands must have different registers.
2516       // Otherwise, the commute transformation does not change anything and
2517       // is useless then.
2518       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2519         break;
2520     }
2521 
2522     // No appropriate commutable operands were found.
2523     if (CommutableOpIdx1 < FirstCommutableVecOp)
2524       return false;
2525 
2526     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2527     // to return those values.
2528     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2529                               CommutableOpIdx1, CommutableOpIdx2))
2530       return false;
2531   }
2532 
2533   return true;
2534 }
2535 
2536 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2537                                          unsigned &SrcOpIdx1,
2538                                          unsigned &SrcOpIdx2) const {
2539   const MCInstrDesc &Desc = MI.getDesc();
2540   if (!Desc.isCommutable())
2541     return false;
2542 
2543   switch (MI.getOpcode()) {
2544   case X86::CMPSDrr:
2545   case X86::CMPSSrr:
2546   case X86::CMPPDrri:
2547   case X86::CMPPSrri:
2548   case X86::VCMPSDrr:
2549   case X86::VCMPSSrr:
2550   case X86::VCMPPDrri:
2551   case X86::VCMPPSrri:
2552   case X86::VCMPPDYrri:
2553   case X86::VCMPPSYrri:
2554   case X86::VCMPSDZrr:
2555   case X86::VCMPSSZrr:
2556   case X86::VCMPPDZrri:
2557   case X86::VCMPPSZrri:
2558   case X86::VCMPSHZrr:
2559   case X86::VCMPPHZrri:
2560   case X86::VCMPPHZ128rri:
2561   case X86::VCMPPHZ256rri:
2562   case X86::VCMPPDZ128rri:
2563   case X86::VCMPPSZ128rri:
2564   case X86::VCMPPDZ256rri:
2565   case X86::VCMPPSZ256rri:
2566   case X86::VCMPPDZrrik:
2567   case X86::VCMPPSZrrik:
2568   case X86::VCMPPDZ128rrik:
2569   case X86::VCMPPSZ128rrik:
2570   case X86::VCMPPDZ256rrik:
2571   case X86::VCMPPSZ256rrik: {
2572     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2573 
2574     // Float comparison can be safely commuted for
2575     // Ordered/Unordered/Equal/NotEqual tests
2576     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2577     switch (Imm) {
2578     default:
2579       // EVEX versions can be commuted.
2580       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2581         break;
2582       return false;
2583     case 0x00: // EQUAL
2584     case 0x03: // UNORDERED
2585     case 0x04: // NOT EQUAL
2586     case 0x07: // ORDERED
2587       break;
2588     }
2589 
2590     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2591     // when masked).
2592     // Assign them to the returned operand indices here.
2593     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2594                                 2 + OpOffset);
2595   }
2596   case X86::MOVSSrr:
2597     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2598     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2599     // AVX implies sse4.1.
2600     if (Subtarget.hasSSE41())
2601       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2602     return false;
2603   case X86::SHUFPDrri:
2604     // We can commute this to MOVSD.
2605     if (MI.getOperand(3).getImm() == 0x02)
2606       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2607     return false;
2608   case X86::MOVHLPSrr:
2609   case X86::UNPCKHPDrr:
2610   case X86::VMOVHLPSrr:
2611   case X86::VUNPCKHPDrr:
2612   case X86::VMOVHLPSZrr:
2613   case X86::VUNPCKHPDZ128rr:
2614     if (Subtarget.hasSSE2())
2615       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2616     return false;
2617   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2618   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2619   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2620   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2621   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2622   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2623   case X86::VPTERNLOGDZrrik:
2624   case X86::VPTERNLOGDZ128rrik:
2625   case X86::VPTERNLOGDZ256rrik:
2626   case X86::VPTERNLOGQZrrik:
2627   case X86::VPTERNLOGQZ128rrik:
2628   case X86::VPTERNLOGQZ256rrik:
2629   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2630   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2631   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2632   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2633   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2634   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2635   case X86::VPTERNLOGDZ128rmbi:
2636   case X86::VPTERNLOGDZ256rmbi:
2637   case X86::VPTERNLOGDZrmbi:
2638   case X86::VPTERNLOGQZ128rmbi:
2639   case X86::VPTERNLOGQZ256rmbi:
2640   case X86::VPTERNLOGQZrmbi:
2641   case X86::VPTERNLOGDZ128rmbikz:
2642   case X86::VPTERNLOGDZ256rmbikz:
2643   case X86::VPTERNLOGDZrmbikz:
2644   case X86::VPTERNLOGQZ128rmbikz:
2645   case X86::VPTERNLOGQZ256rmbikz:
2646   case X86::VPTERNLOGQZrmbikz:
2647     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2648   case X86::VPDPWSSDYrr:
2649   case X86::VPDPWSSDrr:
2650   case X86::VPDPWSSDSYrr:
2651   case X86::VPDPWSSDSrr:
2652   case X86::VPDPWSSDZ128r:
2653   case X86::VPDPWSSDZ128rk:
2654   case X86::VPDPWSSDZ128rkz:
2655   case X86::VPDPWSSDZ256r:
2656   case X86::VPDPWSSDZ256rk:
2657   case X86::VPDPWSSDZ256rkz:
2658   case X86::VPDPWSSDZr:
2659   case X86::VPDPWSSDZrk:
2660   case X86::VPDPWSSDZrkz:
2661   case X86::VPDPWSSDSZ128r:
2662   case X86::VPDPWSSDSZ128rk:
2663   case X86::VPDPWSSDSZ128rkz:
2664   case X86::VPDPWSSDSZ256r:
2665   case X86::VPDPWSSDSZ256rk:
2666   case X86::VPDPWSSDSZ256rkz:
2667   case X86::VPDPWSSDSZr:
2668   case X86::VPDPWSSDSZrk:
2669   case X86::VPDPWSSDSZrkz:
2670   case X86::VPMADD52HUQZ128r:
2671   case X86::VPMADD52HUQZ128rk:
2672   case X86::VPMADD52HUQZ128rkz:
2673   case X86::VPMADD52HUQZ256r:
2674   case X86::VPMADD52HUQZ256rk:
2675   case X86::VPMADD52HUQZ256rkz:
2676   case X86::VPMADD52HUQZr:
2677   case X86::VPMADD52HUQZrk:
2678   case X86::VPMADD52HUQZrkz:
2679   case X86::VPMADD52LUQZ128r:
2680   case X86::VPMADD52LUQZ128rk:
2681   case X86::VPMADD52LUQZ128rkz:
2682   case X86::VPMADD52LUQZ256r:
2683   case X86::VPMADD52LUQZ256rk:
2684   case X86::VPMADD52LUQZ256rkz:
2685   case X86::VPMADD52LUQZr:
2686   case X86::VPMADD52LUQZrk:
2687   case X86::VPMADD52LUQZrkz:
2688   case X86::VFMADDCPHZr:
2689   case X86::VFMADDCPHZrk:
2690   case X86::VFMADDCPHZrkz:
2691   case X86::VFMADDCPHZ128r:
2692   case X86::VFMADDCPHZ128rk:
2693   case X86::VFMADDCPHZ128rkz:
2694   case X86::VFMADDCPHZ256r:
2695   case X86::VFMADDCPHZ256rk:
2696   case X86::VFMADDCPHZ256rkz:
2697   case X86::VFMADDCSHZr:
2698   case X86::VFMADDCSHZrk:
2699   case X86::VFMADDCSHZrkz: {
2700     unsigned CommutableOpIdx1 = 2;
2701     unsigned CommutableOpIdx2 = 3;
2702     if (X86II::isKMasked(Desc.TSFlags)) {
2703       // Skip the mask register.
2704       ++CommutableOpIdx1;
2705       ++CommutableOpIdx2;
2706     }
2707     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2708                               CommutableOpIdx1, CommutableOpIdx2))
2709       return false;
2710     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2711         !MI.getOperand(SrcOpIdx2).isReg())
2712       // No idea.
2713       return false;
2714     return true;
2715   }
2716 
2717   default:
2718     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2719                                                       MI.getDesc().TSFlags);
2720     if (FMA3Group)
2721       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2722                                            FMA3Group->isIntrinsic());
2723 
2724     // Handled masked instructions since we need to skip over the mask input
2725     // and the preserved input.
2726     if (X86II::isKMasked(Desc.TSFlags)) {
2727       // First assume that the first input is the mask operand and skip past it.
2728       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2729       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2730       // Check if the first input is tied. If there isn't one then we only
2731       // need to skip the mask operand which we did above.
2732       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2733                                              MCOI::TIED_TO) != -1)) {
2734         // If this is zero masking instruction with a tied operand, we need to
2735         // move the first index back to the first input since this must
2736         // be a 3 input instruction and we want the first two non-mask inputs.
2737         // Otherwise this is a 2 input instruction with a preserved input and
2738         // mask, so we need to move the indices to skip one more input.
2739         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2740           ++CommutableOpIdx1;
2741           ++CommutableOpIdx2;
2742         } else {
2743           --CommutableOpIdx1;
2744         }
2745       }
2746 
2747       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2748                                 CommutableOpIdx1, CommutableOpIdx2))
2749         return false;
2750 
2751       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2752           !MI.getOperand(SrcOpIdx2).isReg())
2753         // No idea.
2754         return false;
2755       return true;
2756     }
2757 
2758     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2759   }
2760   return false;
2761 }
2762 
2763 static bool isConvertibleLEA(MachineInstr *MI) {
2764   unsigned Opcode = MI->getOpcode();
2765   if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
2766       Opcode != X86::LEA64_32r)
2767     return false;
2768 
2769   const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
2770   const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
2771   const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
2772 
2773   if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
2774       Scale.getImm() > 1)
2775     return false;
2776 
2777   return true;
2778 }
2779 
2780 bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
2781   // Currently we're interested in following sequence only.
2782   //   r3 = lea r1, r2
2783   //   r5 = add r3, r4
2784   // Both r3 and r4 are killed in add, we hope the add instruction has the
2785   // operand order
2786   //   r5 = add r4, r3
2787   // So later in X86FixupLEAs the lea instruction can be rewritten as add.
2788   unsigned Opcode = MI.getOpcode();
2789   if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
2790     return false;
2791 
2792   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2793   Register Reg1 = MI.getOperand(1).getReg();
2794   Register Reg2 = MI.getOperand(2).getReg();
2795 
2796   // Check if Reg1 comes from LEA in the same MBB.
2797   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
2798     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2799       Commute = true;
2800       return true;
2801     }
2802   }
2803 
2804   // Check if Reg2 comes from LEA in the same MBB.
2805   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
2806     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2807       Commute = false;
2808       return true;
2809     }
2810   }
2811 
2812   return false;
2813 }
2814 
2815 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2816   switch (MI.getOpcode()) {
2817   default: return X86::COND_INVALID;
2818   case X86::JCC_1:
2819     return static_cast<X86::CondCode>(
2820         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2821   }
2822 }
2823 
2824 /// Return condition code of a SETCC opcode.
2825 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2826   switch (MI.getOpcode()) {
2827   default: return X86::COND_INVALID;
2828   case X86::SETCCr: case X86::SETCCm:
2829     return static_cast<X86::CondCode>(
2830         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2831   }
2832 }
2833 
2834 /// Return condition code of a CMov opcode.
2835 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2836   switch (MI.getOpcode()) {
2837   default: return X86::COND_INVALID;
2838   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2839   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2840     return static_cast<X86::CondCode>(
2841         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2842   }
2843 }
2844 
2845 /// Return the inverse of the specified condition,
2846 /// e.g. turning COND_E to COND_NE.
2847 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2848   switch (CC) {
2849   default: llvm_unreachable("Illegal condition code!");
2850   case X86::COND_E:  return X86::COND_NE;
2851   case X86::COND_NE: return X86::COND_E;
2852   case X86::COND_L:  return X86::COND_GE;
2853   case X86::COND_LE: return X86::COND_G;
2854   case X86::COND_G:  return X86::COND_LE;
2855   case X86::COND_GE: return X86::COND_L;
2856   case X86::COND_B:  return X86::COND_AE;
2857   case X86::COND_BE: return X86::COND_A;
2858   case X86::COND_A:  return X86::COND_BE;
2859   case X86::COND_AE: return X86::COND_B;
2860   case X86::COND_S:  return X86::COND_NS;
2861   case X86::COND_NS: return X86::COND_S;
2862   case X86::COND_P:  return X86::COND_NP;
2863   case X86::COND_NP: return X86::COND_P;
2864   case X86::COND_O:  return X86::COND_NO;
2865   case X86::COND_NO: return X86::COND_O;
2866   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2867   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2868   }
2869 }
2870 
2871 /// Assuming the flags are set by MI(a,b), return the condition code if we
2872 /// modify the instructions such that flags are set by MI(b,a).
2873 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2874   switch (CC) {
2875   default: return X86::COND_INVALID;
2876   case X86::COND_E:  return X86::COND_E;
2877   case X86::COND_NE: return X86::COND_NE;
2878   case X86::COND_L:  return X86::COND_G;
2879   case X86::COND_LE: return X86::COND_GE;
2880   case X86::COND_G:  return X86::COND_L;
2881   case X86::COND_GE: return X86::COND_LE;
2882   case X86::COND_B:  return X86::COND_A;
2883   case X86::COND_BE: return X86::COND_AE;
2884   case X86::COND_A:  return X86::COND_B;
2885   case X86::COND_AE: return X86::COND_BE;
2886   }
2887 }
2888 
2889 std::pair<X86::CondCode, bool>
2890 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2891   X86::CondCode CC = X86::COND_INVALID;
2892   bool NeedSwap = false;
2893   switch (Predicate) {
2894   default: break;
2895   // Floating-point Predicates
2896   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2897   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2898   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2899   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2900   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2901   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2902   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2903   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2904   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2905   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2906   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2907   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2908   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2909   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2910 
2911   // Integer Predicates
2912   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2913   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2914   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2915   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2916   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2917   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2918   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2919   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2920   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2921   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2922   }
2923 
2924   return std::make_pair(CC, NeedSwap);
2925 }
2926 
2927 /// Return a cmov opcode for the given register size in bytes, and operand type.
2928 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2929   switch(RegBytes) {
2930   default: llvm_unreachable("Illegal register size!");
2931   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2932   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2933   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2934   }
2935 }
2936 
2937 /// Get the VPCMP immediate for the given condition.
2938 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2939   switch (CC) {
2940   default: llvm_unreachable("Unexpected SETCC condition");
2941   case ISD::SETNE:  return 4;
2942   case ISD::SETEQ:  return 0;
2943   case ISD::SETULT:
2944   case ISD::SETLT: return 1;
2945   case ISD::SETUGT:
2946   case ISD::SETGT: return 6;
2947   case ISD::SETUGE:
2948   case ISD::SETGE: return 5;
2949   case ISD::SETULE:
2950   case ISD::SETLE: return 2;
2951   }
2952 }
2953 
2954 /// Get the VPCMP immediate if the operands are swapped.
2955 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2956   switch (Imm) {
2957   default: llvm_unreachable("Unreachable!");
2958   case 0x01: Imm = 0x06; break; // LT  -> NLE
2959   case 0x02: Imm = 0x05; break; // LE  -> NLT
2960   case 0x05: Imm = 0x02; break; // NLT -> LE
2961   case 0x06: Imm = 0x01; break; // NLE -> LT
2962   case 0x00: // EQ
2963   case 0x03: // FALSE
2964   case 0x04: // NE
2965   case 0x07: // TRUE
2966     break;
2967   }
2968 
2969   return Imm;
2970 }
2971 
2972 /// Get the VPCOM immediate if the operands are swapped.
2973 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2974   switch (Imm) {
2975   default: llvm_unreachable("Unreachable!");
2976   case 0x00: Imm = 0x02; break; // LT -> GT
2977   case 0x01: Imm = 0x03; break; // LE -> GE
2978   case 0x02: Imm = 0x00; break; // GT -> LT
2979   case 0x03: Imm = 0x01; break; // GE -> LE
2980   case 0x04: // EQ
2981   case 0x05: // NE
2982   case 0x06: // FALSE
2983   case 0x07: // TRUE
2984     break;
2985   }
2986 
2987   return Imm;
2988 }
2989 
2990 /// Get the VCMP immediate if the operands are swapped.
2991 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2992   // Only need the lower 2 bits to distinquish.
2993   switch (Imm & 0x3) {
2994   default: llvm_unreachable("Unreachable!");
2995   case 0x00: case 0x03:
2996     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2997     break;
2998   case 0x01: case 0x02:
2999     // Need to toggle bits 3:0. Bit 4 stays the same.
3000     Imm ^= 0xf;
3001     break;
3002   }
3003 
3004   return Imm;
3005 }
3006 
3007 /// Return true if the Reg is X87 register.
3008 static bool isX87Reg(unsigned Reg) {
3009   return (Reg == X86::FPCW || Reg == X86::FPSW ||
3010           (Reg >= X86::ST0 && Reg <= X86::ST7));
3011 }
3012 
3013 /// check if the instruction is X87 instruction
3014 bool X86::isX87Instruction(MachineInstr &MI) {
3015   for (const MachineOperand &MO : MI.operands()) {
3016     if (!MO.isReg())
3017       continue;
3018     if (isX87Reg(MO.getReg()))
3019       return true;
3020   }
3021   return false;
3022 }
3023 
3024 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
3025   switch (MI.getOpcode()) {
3026   case X86::TCRETURNdi:
3027   case X86::TCRETURNri:
3028   case X86::TCRETURNmi:
3029   case X86::TCRETURNdi64:
3030   case X86::TCRETURNri64:
3031   case X86::TCRETURNmi64:
3032     return true;
3033   default:
3034     return false;
3035   }
3036 }
3037 
3038 bool X86InstrInfo::canMakeTailCallConditional(
3039     SmallVectorImpl<MachineOperand> &BranchCond,
3040     const MachineInstr &TailCall) const {
3041   if (TailCall.getOpcode() != X86::TCRETURNdi &&
3042       TailCall.getOpcode() != X86::TCRETURNdi64) {
3043     // Only direct calls can be done with a conditional branch.
3044     return false;
3045   }
3046 
3047   const MachineFunction *MF = TailCall.getParent()->getParent();
3048   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
3049     // Conditional tail calls confuse the Win64 unwinder.
3050     return false;
3051   }
3052 
3053   assert(BranchCond.size() == 1);
3054   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
3055     // Can't make a conditional tail call with this condition.
3056     return false;
3057   }
3058 
3059   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3060   if (X86FI->getTCReturnAddrDelta() != 0 ||
3061       TailCall.getOperand(1).getImm() != 0) {
3062     // A conditional tail call cannot do any stack adjustment.
3063     return false;
3064   }
3065 
3066   return true;
3067 }
3068 
3069 void X86InstrInfo::replaceBranchWithTailCall(
3070     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
3071     const MachineInstr &TailCall) const {
3072   assert(canMakeTailCallConditional(BranchCond, TailCall));
3073 
3074   MachineBasicBlock::iterator I = MBB.end();
3075   while (I != MBB.begin()) {
3076     --I;
3077     if (I->isDebugInstr())
3078       continue;
3079     if (!I->isBranch())
3080       assert(0 && "Can't find the branch to replace!");
3081 
3082     X86::CondCode CC = X86::getCondFromBranch(*I);
3083     assert(BranchCond.size() == 1);
3084     if (CC != BranchCond[0].getImm())
3085       continue;
3086 
3087     break;
3088   }
3089 
3090   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3091                                                          : X86::TCRETURNdi64cc;
3092 
3093   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
3094   MIB->addOperand(TailCall.getOperand(0)); // Destination.
3095   MIB.addImm(0); // Stack offset (not used).
3096   MIB->addOperand(BranchCond[0]); // Condition.
3097   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
3098 
3099   // Add implicit uses and defs of all live regs potentially clobbered by the
3100   // call. This way they still appear live across the call.
3101   LivePhysRegs LiveRegs(getRegisterInfo());
3102   LiveRegs.addLiveOuts(MBB);
3103   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
3104   LiveRegs.stepForward(*MIB, Clobbers);
3105   for (const auto &C : Clobbers) {
3106     MIB.addReg(C.first, RegState::Implicit);
3107     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
3108   }
3109 
3110   I->eraseFromParent();
3111 }
3112 
3113 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3114 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
3115 // fallthrough MBB cannot be identified.
3116 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3117                                             MachineBasicBlock *TBB) {
3118   // Look for non-EHPad successors other than TBB. If we find exactly one, it
3119   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3120   // and fallthrough MBB. If we find more than one, we cannot identify the
3121   // fallthrough MBB and should return nullptr.
3122   MachineBasicBlock *FallthroughBB = nullptr;
3123   for (MachineBasicBlock *Succ : MBB->successors()) {
3124     if (Succ->isEHPad() || (Succ == TBB && FallthroughBB))
3125       continue;
3126     // Return a nullptr if we found more than one fallthrough successor.
3127     if (FallthroughBB && FallthroughBB != TBB)
3128       return nullptr;
3129     FallthroughBB = Succ;
3130   }
3131   return FallthroughBB;
3132 }
3133 
3134 bool X86InstrInfo::AnalyzeBranchImpl(
3135     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3136     SmallVectorImpl<MachineOperand> &Cond,
3137     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3138 
3139   // Start from the bottom of the block and work up, examining the
3140   // terminator instructions.
3141   MachineBasicBlock::iterator I = MBB.end();
3142   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3143   while (I != MBB.begin()) {
3144     --I;
3145     if (I->isDebugInstr())
3146       continue;
3147 
3148     // Working from the bottom, when we see a non-terminator instruction, we're
3149     // done.
3150     if (!isUnpredicatedTerminator(*I))
3151       break;
3152 
3153     // A terminator that isn't a branch can't easily be handled by this
3154     // analysis.
3155     if (!I->isBranch())
3156       return true;
3157 
3158     // Handle unconditional branches.
3159     if (I->getOpcode() == X86::JMP_1) {
3160       UnCondBrIter = I;
3161 
3162       if (!AllowModify) {
3163         TBB = I->getOperand(0).getMBB();
3164         continue;
3165       }
3166 
3167       // If the block has any instructions after a JMP, delete them.
3168       while (std::next(I) != MBB.end())
3169         std::next(I)->eraseFromParent();
3170 
3171       Cond.clear();
3172       FBB = nullptr;
3173 
3174       // Delete the JMP if it's equivalent to a fall-through.
3175       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3176         TBB = nullptr;
3177         I->eraseFromParent();
3178         I = MBB.end();
3179         UnCondBrIter = MBB.end();
3180         continue;
3181       }
3182 
3183       // TBB is used to indicate the unconditional destination.
3184       TBB = I->getOperand(0).getMBB();
3185       continue;
3186     }
3187 
3188     // Handle conditional branches.
3189     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3190     if (BranchCode == X86::COND_INVALID)
3191       return true;  // Can't handle indirect branch.
3192 
3193     // In practice we should never have an undef eflags operand, if we do
3194     // abort here as we are not prepared to preserve the flag.
3195     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3196       return true;
3197 
3198     // Working from the bottom, handle the first conditional branch.
3199     if (Cond.empty()) {
3200       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3201       if (AllowModify && UnCondBrIter != MBB.end() &&
3202           MBB.isLayoutSuccessor(TargetBB)) {
3203         // If we can modify the code and it ends in something like:
3204         //
3205         //     jCC L1
3206         //     jmp L2
3207         //   L1:
3208         //     ...
3209         //   L2:
3210         //
3211         // Then we can change this to:
3212         //
3213         //     jnCC L2
3214         //   L1:
3215         //     ...
3216         //   L2:
3217         //
3218         // Which is a bit more efficient.
3219         // We conditionally jump to the fall-through block.
3220         BranchCode = GetOppositeBranchCondition(BranchCode);
3221         MachineBasicBlock::iterator OldInst = I;
3222 
3223         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3224           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3225           .addImm(BranchCode);
3226         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3227           .addMBB(TargetBB);
3228 
3229         OldInst->eraseFromParent();
3230         UnCondBrIter->eraseFromParent();
3231 
3232         // Restart the analysis.
3233         UnCondBrIter = MBB.end();
3234         I = MBB.end();
3235         continue;
3236       }
3237 
3238       FBB = TBB;
3239       TBB = I->getOperand(0).getMBB();
3240       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3241       CondBranches.push_back(&*I);
3242       continue;
3243     }
3244 
3245     // Handle subsequent conditional branches. Only handle the case where all
3246     // conditional branches branch to the same destination and their condition
3247     // opcodes fit one of the special multi-branch idioms.
3248     assert(Cond.size() == 1);
3249     assert(TBB);
3250 
3251     // If the conditions are the same, we can leave them alone.
3252     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3253     auto NewTBB = I->getOperand(0).getMBB();
3254     if (OldBranchCode == BranchCode && TBB == NewTBB)
3255       continue;
3256 
3257     // If they differ, see if they fit one of the known patterns. Theoretically,
3258     // we could handle more patterns here, but we shouldn't expect to see them
3259     // if instruction selection has done a reasonable job.
3260     if (TBB == NewTBB &&
3261                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3262                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3263       BranchCode = X86::COND_NE_OR_P;
3264     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3265                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3266       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3267         return true;
3268 
3269       // X86::COND_E_AND_NP usually has two different branch destinations.
3270       //
3271       // JP B1
3272       // JE B2
3273       // JMP B1
3274       // B1:
3275       // B2:
3276       //
3277       // Here this condition branches to B2 only if NP && E. It has another
3278       // equivalent form:
3279       //
3280       // JNE B1
3281       // JNP B2
3282       // JMP B1
3283       // B1:
3284       // B2:
3285       //
3286       // Similarly it branches to B2 only if E && NP. That is why this condition
3287       // is named with COND_E_AND_NP.
3288       BranchCode = X86::COND_E_AND_NP;
3289     } else
3290       return true;
3291 
3292     // Update the MachineOperand.
3293     Cond[0].setImm(BranchCode);
3294     CondBranches.push_back(&*I);
3295   }
3296 
3297   return false;
3298 }
3299 
3300 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3301                                  MachineBasicBlock *&TBB,
3302                                  MachineBasicBlock *&FBB,
3303                                  SmallVectorImpl<MachineOperand> &Cond,
3304                                  bool AllowModify) const {
3305   SmallVector<MachineInstr *, 4> CondBranches;
3306   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3307 }
3308 
3309 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3310                                           MachineBranchPredicate &MBP,
3311                                           bool AllowModify) const {
3312   using namespace std::placeholders;
3313 
3314   SmallVector<MachineOperand, 4> Cond;
3315   SmallVector<MachineInstr *, 4> CondBranches;
3316   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3317                         AllowModify))
3318     return true;
3319 
3320   if (Cond.size() != 1)
3321     return true;
3322 
3323   assert(MBP.TrueDest && "expected!");
3324 
3325   if (!MBP.FalseDest)
3326     MBP.FalseDest = MBB.getNextNode();
3327 
3328   const TargetRegisterInfo *TRI = &getRegisterInfo();
3329 
3330   MachineInstr *ConditionDef = nullptr;
3331   bool SingleUseCondition = true;
3332 
3333   for (MachineInstr &MI : llvm::drop_begin(llvm::reverse(MBB))) {
3334     if (MI.modifiesRegister(X86::EFLAGS, TRI)) {
3335       ConditionDef = &MI;
3336       break;
3337     }
3338 
3339     if (MI.readsRegister(X86::EFLAGS, TRI))
3340       SingleUseCondition = false;
3341   }
3342 
3343   if (!ConditionDef)
3344     return true;
3345 
3346   if (SingleUseCondition) {
3347     for (auto *Succ : MBB.successors())
3348       if (Succ->isLiveIn(X86::EFLAGS))
3349         SingleUseCondition = false;
3350   }
3351 
3352   MBP.ConditionDef = ConditionDef;
3353   MBP.SingleUseCondition = SingleUseCondition;
3354 
3355   // Currently we only recognize the simple pattern:
3356   //
3357   //   test %reg, %reg
3358   //   je %label
3359   //
3360   const unsigned TestOpcode =
3361       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3362 
3363   if (ConditionDef->getOpcode() == TestOpcode &&
3364       ConditionDef->getNumOperands() == 3 &&
3365       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3366       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3367     MBP.LHS = ConditionDef->getOperand(0);
3368     MBP.RHS = MachineOperand::CreateImm(0);
3369     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3370                         ? MachineBranchPredicate::PRED_NE
3371                         : MachineBranchPredicate::PRED_EQ;
3372     return false;
3373   }
3374 
3375   return true;
3376 }
3377 
3378 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3379                                     int *BytesRemoved) const {
3380   assert(!BytesRemoved && "code size not handled");
3381 
3382   MachineBasicBlock::iterator I = MBB.end();
3383   unsigned Count = 0;
3384 
3385   while (I != MBB.begin()) {
3386     --I;
3387     if (I->isDebugInstr())
3388       continue;
3389     if (I->getOpcode() != X86::JMP_1 &&
3390         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3391       break;
3392     // Remove the branch.
3393     I->eraseFromParent();
3394     I = MBB.end();
3395     ++Count;
3396   }
3397 
3398   return Count;
3399 }
3400 
3401 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3402                                     MachineBasicBlock *TBB,
3403                                     MachineBasicBlock *FBB,
3404                                     ArrayRef<MachineOperand> Cond,
3405                                     const DebugLoc &DL,
3406                                     int *BytesAdded) const {
3407   // Shouldn't be a fall through.
3408   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3409   assert((Cond.size() == 1 || Cond.size() == 0) &&
3410          "X86 branch conditions have one component!");
3411   assert(!BytesAdded && "code size not handled");
3412 
3413   if (Cond.empty()) {
3414     // Unconditional branch?
3415     assert(!FBB && "Unconditional branch with multiple successors!");
3416     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3417     return 1;
3418   }
3419 
3420   // If FBB is null, it is implied to be a fall-through block.
3421   bool FallThru = FBB == nullptr;
3422 
3423   // Conditional branch.
3424   unsigned Count = 0;
3425   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3426   switch (CC) {
3427   case X86::COND_NE_OR_P:
3428     // Synthesize NE_OR_P with two branches.
3429     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3430     ++Count;
3431     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3432     ++Count;
3433     break;
3434   case X86::COND_E_AND_NP:
3435     // Use the next block of MBB as FBB if it is null.
3436     if (FBB == nullptr) {
3437       FBB = getFallThroughMBB(&MBB, TBB);
3438       assert(FBB && "MBB cannot be the last block in function when the false "
3439                     "body is a fall-through.");
3440     }
3441     // Synthesize COND_E_AND_NP with two branches.
3442     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3443     ++Count;
3444     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3445     ++Count;
3446     break;
3447   default: {
3448     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3449     ++Count;
3450   }
3451   }
3452   if (!FallThru) {
3453     // Two-way Conditional branch. Insert the second branch.
3454     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3455     ++Count;
3456   }
3457   return Count;
3458 }
3459 
3460 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3461                                    ArrayRef<MachineOperand> Cond,
3462                                    Register DstReg, Register TrueReg,
3463                                    Register FalseReg, int &CondCycles,
3464                                    int &TrueCycles, int &FalseCycles) const {
3465   // Not all subtargets have cmov instructions.
3466   if (!Subtarget.hasCMov())
3467     return false;
3468   if (Cond.size() != 1)
3469     return false;
3470   // We cannot do the composite conditions, at least not in SSA form.
3471   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3472     return false;
3473 
3474   // Check register classes.
3475   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3476   const TargetRegisterClass *RC =
3477     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3478   if (!RC)
3479     return false;
3480 
3481   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3482   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3483       X86::GR32RegClass.hasSubClassEq(RC) ||
3484       X86::GR64RegClass.hasSubClassEq(RC)) {
3485     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3486     // Bridge. Probably Ivy Bridge as well.
3487     CondCycles = 2;
3488     TrueCycles = 2;
3489     FalseCycles = 2;
3490     return true;
3491   }
3492 
3493   // Can't do vectors.
3494   return false;
3495 }
3496 
3497 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3498                                 MachineBasicBlock::iterator I,
3499                                 const DebugLoc &DL, Register DstReg,
3500                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3501                                 Register FalseReg) const {
3502   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3503   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3504   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3505   assert(Cond.size() == 1 && "Invalid Cond array");
3506   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3507                                     false /*HasMemoryOperand*/);
3508   BuildMI(MBB, I, DL, get(Opc), DstReg)
3509       .addReg(FalseReg)
3510       .addReg(TrueReg)
3511       .addImm(Cond[0].getImm());
3512 }
3513 
3514 /// Test if the given register is a physical h register.
3515 static bool isHReg(unsigned Reg) {
3516   return X86::GR8_ABCD_HRegClass.contains(Reg);
3517 }
3518 
3519 // Try and copy between VR128/VR64 and GR64 registers.
3520 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3521                                         const X86Subtarget &Subtarget) {
3522   bool HasAVX = Subtarget.hasAVX();
3523   bool HasAVX512 = Subtarget.hasAVX512();
3524 
3525   // SrcReg(MaskReg) -> DestReg(GR64)
3526   // SrcReg(MaskReg) -> DestReg(GR32)
3527 
3528   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3529   if (X86::VK16RegClass.contains(SrcReg)) {
3530     if (X86::GR64RegClass.contains(DestReg)) {
3531       assert(Subtarget.hasBWI());
3532       return X86::KMOVQrk;
3533     }
3534     if (X86::GR32RegClass.contains(DestReg))
3535       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3536   }
3537 
3538   // SrcReg(GR64) -> DestReg(MaskReg)
3539   // SrcReg(GR32) -> DestReg(MaskReg)
3540 
3541   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3542   if (X86::VK16RegClass.contains(DestReg)) {
3543     if (X86::GR64RegClass.contains(SrcReg)) {
3544       assert(Subtarget.hasBWI());
3545       return X86::KMOVQkr;
3546     }
3547     if (X86::GR32RegClass.contains(SrcReg))
3548       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3549   }
3550 
3551 
3552   // SrcReg(VR128) -> DestReg(GR64)
3553   // SrcReg(VR64)  -> DestReg(GR64)
3554   // SrcReg(GR64)  -> DestReg(VR128)
3555   // SrcReg(GR64)  -> DestReg(VR64)
3556 
3557   if (X86::GR64RegClass.contains(DestReg)) {
3558     if (X86::VR128XRegClass.contains(SrcReg))
3559       // Copy from a VR128 register to a GR64 register.
3560       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3561              HasAVX    ? X86::VMOVPQIto64rr  :
3562                          X86::MOVPQIto64rr;
3563     if (X86::VR64RegClass.contains(SrcReg))
3564       // Copy from a VR64 register to a GR64 register.
3565       return X86::MMX_MOVD64from64rr;
3566   } else if (X86::GR64RegClass.contains(SrcReg)) {
3567     // Copy from a GR64 register to a VR128 register.
3568     if (X86::VR128XRegClass.contains(DestReg))
3569       return HasAVX512 ? X86::VMOV64toPQIZrr :
3570              HasAVX    ? X86::VMOV64toPQIrr  :
3571                          X86::MOV64toPQIrr;
3572     // Copy from a GR64 register to a VR64 register.
3573     if (X86::VR64RegClass.contains(DestReg))
3574       return X86::MMX_MOVD64to64rr;
3575   }
3576 
3577   // SrcReg(VR128) -> DestReg(GR32)
3578   // SrcReg(GR32)  -> DestReg(VR128)
3579 
3580   if (X86::GR32RegClass.contains(DestReg) &&
3581       X86::VR128XRegClass.contains(SrcReg))
3582     // Copy from a VR128 register to a GR32 register.
3583     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3584            HasAVX    ? X86::VMOVPDI2DIrr  :
3585                        X86::MOVPDI2DIrr;
3586 
3587   if (X86::VR128XRegClass.contains(DestReg) &&
3588       X86::GR32RegClass.contains(SrcReg))
3589     // Copy from a VR128 register to a VR128 register.
3590     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3591            HasAVX    ? X86::VMOVDI2PDIrr  :
3592                        X86::MOVDI2PDIrr;
3593   return 0;
3594 }
3595 
3596 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3597                                MachineBasicBlock::iterator MI,
3598                                const DebugLoc &DL, MCRegister DestReg,
3599                                MCRegister SrcReg, bool KillSrc) const {
3600   // First deal with the normal symmetric copies.
3601   bool HasAVX = Subtarget.hasAVX();
3602   bool HasVLX = Subtarget.hasVLX();
3603   unsigned Opc = 0;
3604   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3605     Opc = X86::MOV64rr;
3606   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3607     Opc = X86::MOV32rr;
3608   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3609     Opc = X86::MOV16rr;
3610   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3611     // Copying to or from a physical H register on x86-64 requires a NOREX
3612     // move.  Otherwise use a normal move.
3613     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3614         Subtarget.is64Bit()) {
3615       Opc = X86::MOV8rr_NOREX;
3616       // Both operands must be encodable without an REX prefix.
3617       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3618              "8-bit H register can not be copied outside GR8_NOREX");
3619     } else
3620       Opc = X86::MOV8rr;
3621   }
3622   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3623     Opc = X86::MMX_MOVQ64rr;
3624   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3625     if (HasVLX)
3626       Opc = X86::VMOVAPSZ128rr;
3627     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3628       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3629     else {
3630       // If this an extended register and we don't have VLX we need to use a
3631       // 512-bit move.
3632       Opc = X86::VMOVAPSZrr;
3633       const TargetRegisterInfo *TRI = &getRegisterInfo();
3634       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3635                                          &X86::VR512RegClass);
3636       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3637                                         &X86::VR512RegClass);
3638     }
3639   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3640     if (HasVLX)
3641       Opc = X86::VMOVAPSZ256rr;
3642     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3643       Opc = X86::VMOVAPSYrr;
3644     else {
3645       // If this an extended register and we don't have VLX we need to use a
3646       // 512-bit move.
3647       Opc = X86::VMOVAPSZrr;
3648       const TargetRegisterInfo *TRI = &getRegisterInfo();
3649       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3650                                          &X86::VR512RegClass);
3651       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3652                                         &X86::VR512RegClass);
3653     }
3654   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3655     Opc = X86::VMOVAPSZrr;
3656   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3657   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3658     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3659   if (!Opc)
3660     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3661 
3662   if (Opc) {
3663     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3664       .addReg(SrcReg, getKillRegState(KillSrc));
3665     return;
3666   }
3667 
3668   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3669     // FIXME: We use a fatal error here because historically LLVM has tried
3670     // lower some of these physreg copies and we want to ensure we get
3671     // reasonable bug reports if someone encounters a case no other testing
3672     // found. This path should be removed after the LLVM 7 release.
3673     report_fatal_error("Unable to copy EFLAGS physical register!");
3674   }
3675 
3676   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3677                     << RI.getName(DestReg) << '\n');
3678   report_fatal_error("Cannot emit physreg copy instruction");
3679 }
3680 
3681 Optional<DestSourcePair>
3682 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3683   if (MI.isMoveReg())
3684     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3685   return None;
3686 }
3687 
3688 static unsigned getLoadStoreRegOpcode(Register Reg,
3689                                       const TargetRegisterClass *RC,
3690                                       bool IsStackAligned,
3691                                       const X86Subtarget &STI, bool load) {
3692   bool HasAVX = STI.hasAVX();
3693   bool HasAVX512 = STI.hasAVX512();
3694   bool HasVLX = STI.hasVLX();
3695 
3696   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3697   default:
3698     llvm_unreachable("Unknown spill size");
3699   case 1:
3700     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3701     if (STI.is64Bit())
3702       // Copying to or from a physical H register on x86-64 requires a NOREX
3703       // move.  Otherwise use a normal move.
3704       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3705         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3706     return load ? X86::MOV8rm : X86::MOV8mr;
3707   case 2:
3708     if (X86::VK16RegClass.hasSubClassEq(RC))
3709       return load ? X86::KMOVWkm : X86::KMOVWmk;
3710     if (X86::FR16XRegClass.hasSubClassEq(RC)) {
3711       assert(STI.hasFP16());
3712       return load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
3713     }
3714     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3715     return load ? X86::MOV16rm : X86::MOV16mr;
3716   case 4:
3717     if (X86::GR32RegClass.hasSubClassEq(RC))
3718       return load ? X86::MOV32rm : X86::MOV32mr;
3719     if (X86::FR32XRegClass.hasSubClassEq(RC))
3720       return load ?
3721         (HasAVX512 ? X86::VMOVSSZrm_alt :
3722          HasAVX    ? X86::VMOVSSrm_alt :
3723                      X86::MOVSSrm_alt) :
3724         (HasAVX512 ? X86::VMOVSSZmr :
3725          HasAVX    ? X86::VMOVSSmr :
3726                      X86::MOVSSmr);
3727     if (X86::RFP32RegClass.hasSubClassEq(RC))
3728       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3729     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3730       assert(STI.hasBWI() && "KMOVD requires BWI");
3731       return load ? X86::KMOVDkm : X86::KMOVDmk;
3732     }
3733     // All of these mask pair classes have the same spill size, the same kind
3734     // of kmov instructions can be used with all of them.
3735     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3736         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3737         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3738         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3739         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3740       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3741     llvm_unreachable("Unknown 4-byte regclass");
3742   case 8:
3743     if (X86::GR64RegClass.hasSubClassEq(RC))
3744       return load ? X86::MOV64rm : X86::MOV64mr;
3745     if (X86::FR64XRegClass.hasSubClassEq(RC))
3746       return load ?
3747         (HasAVX512 ? X86::VMOVSDZrm_alt :
3748          HasAVX    ? X86::VMOVSDrm_alt :
3749                      X86::MOVSDrm_alt) :
3750         (HasAVX512 ? X86::VMOVSDZmr :
3751          HasAVX    ? X86::VMOVSDmr :
3752                      X86::MOVSDmr);
3753     if (X86::VR64RegClass.hasSubClassEq(RC))
3754       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3755     if (X86::RFP64RegClass.hasSubClassEq(RC))
3756       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3757     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3758       assert(STI.hasBWI() && "KMOVQ requires BWI");
3759       return load ? X86::KMOVQkm : X86::KMOVQmk;
3760     }
3761     llvm_unreachable("Unknown 8-byte regclass");
3762   case 10:
3763     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3764     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3765   case 16: {
3766     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3767       // If stack is realigned we can use aligned stores.
3768       if (IsStackAligned)
3769         return load ?
3770           (HasVLX    ? X86::VMOVAPSZ128rm :
3771            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3772            HasAVX    ? X86::VMOVAPSrm :
3773                        X86::MOVAPSrm):
3774           (HasVLX    ? X86::VMOVAPSZ128mr :
3775            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3776            HasAVX    ? X86::VMOVAPSmr :
3777                        X86::MOVAPSmr);
3778       else
3779         return load ?
3780           (HasVLX    ? X86::VMOVUPSZ128rm :
3781            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3782            HasAVX    ? X86::VMOVUPSrm :
3783                        X86::MOVUPSrm):
3784           (HasVLX    ? X86::VMOVUPSZ128mr :
3785            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3786            HasAVX    ? X86::VMOVUPSmr :
3787                        X86::MOVUPSmr);
3788     }
3789     llvm_unreachable("Unknown 16-byte regclass");
3790   }
3791   case 32:
3792     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3793     // If stack is realigned we can use aligned stores.
3794     if (IsStackAligned)
3795       return load ?
3796         (HasVLX    ? X86::VMOVAPSZ256rm :
3797          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3798                      X86::VMOVAPSYrm) :
3799         (HasVLX    ? X86::VMOVAPSZ256mr :
3800          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3801                      X86::VMOVAPSYmr);
3802     else
3803       return load ?
3804         (HasVLX    ? X86::VMOVUPSZ256rm :
3805          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3806                      X86::VMOVUPSYrm) :
3807         (HasVLX    ? X86::VMOVUPSZ256mr :
3808          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3809                      X86::VMOVUPSYmr);
3810   case 64:
3811     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3812     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3813     if (IsStackAligned)
3814       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3815     else
3816       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3817   }
3818 }
3819 
3820 Optional<ExtAddrMode>
3821 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3822                                       const TargetRegisterInfo *TRI) const {
3823   const MCInstrDesc &Desc = MemI.getDesc();
3824   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3825   if (MemRefBegin < 0)
3826     return None;
3827 
3828   MemRefBegin += X86II::getOperandBias(Desc);
3829 
3830   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3831   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3832     return None;
3833 
3834   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3835   // Displacement can be symbolic
3836   if (!DispMO.isImm())
3837     return None;
3838 
3839   ExtAddrMode AM;
3840   AM.BaseReg = BaseOp.getReg();
3841   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3842   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3843   AM.Displacement = DispMO.getImm();
3844   return AM;
3845 }
3846 
3847 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3848                                            const Register Reg,
3849                                            int64_t &ImmVal) const {
3850   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3851     return false;
3852   // Mov Src can be a global address.
3853   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3854     return false;
3855   ImmVal = MI.getOperand(1).getImm();
3856   return true;
3857 }
3858 
3859 bool X86InstrInfo::preservesZeroValueInReg(
3860     const MachineInstr *MI, const Register NullValueReg,
3861     const TargetRegisterInfo *TRI) const {
3862   if (!MI->modifiesRegister(NullValueReg, TRI))
3863     return true;
3864   switch (MI->getOpcode()) {
3865   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3866   // X.
3867   case X86::SHR64ri:
3868   case X86::SHR32ri:
3869   case X86::SHL64ri:
3870   case X86::SHL32ri:
3871     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3872            "expected for shift opcode!");
3873     return MI->getOperand(0).getReg() == NullValueReg &&
3874            MI->getOperand(1).getReg() == NullValueReg;
3875   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3876   // null value.
3877   case X86::MOV32rr:
3878     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3879       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3880     });
3881   default:
3882     return false;
3883   }
3884   llvm_unreachable("Should be handled above!");
3885 }
3886 
3887 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3888     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3889     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3890     const TargetRegisterInfo *TRI) const {
3891   const MCInstrDesc &Desc = MemOp.getDesc();
3892   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3893   if (MemRefBegin < 0)
3894     return false;
3895 
3896   MemRefBegin += X86II::getOperandBias(Desc);
3897 
3898   const MachineOperand *BaseOp =
3899       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3900   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3901     return false;
3902 
3903   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3904     return false;
3905 
3906   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3907       X86::NoRegister)
3908     return false;
3909 
3910   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3911 
3912   // Displacement can be symbolic
3913   if (!DispMO.isImm())
3914     return false;
3915 
3916   Offset = DispMO.getImm();
3917 
3918   if (!BaseOp->isReg())
3919     return false;
3920 
3921   OffsetIsScalable = false;
3922   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3923   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3924   // there is no use of `Width` for X86 back-end at the moment.
3925   Width =
3926       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3927   BaseOps.push_back(BaseOp);
3928   return true;
3929 }
3930 
3931 static unsigned getStoreRegOpcode(Register SrcReg,
3932                                   const TargetRegisterClass *RC,
3933                                   bool IsStackAligned,
3934                                   const X86Subtarget &STI) {
3935   return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3936 }
3937 
3938 static unsigned getLoadRegOpcode(Register DestReg,
3939                                  const TargetRegisterClass *RC,
3940                                  bool IsStackAligned, const X86Subtarget &STI) {
3941   return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3942 }
3943 
3944 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3945                                        MachineBasicBlock::iterator MI,
3946                                        Register SrcReg, bool isKill, int FrameIdx,
3947                                        const TargetRegisterClass *RC,
3948                                        const TargetRegisterInfo *TRI) const {
3949   const MachineFunction &MF = *MBB.getParent();
3950   const MachineFrameInfo &MFI = MF.getFrameInfo();
3951   assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3952          "Stack slot too small for store");
3953   if (RC->getID() == X86::TILERegClassID) {
3954     unsigned Opc = X86::TILESTORED;
3955     // tilestored %tmm, (%sp, %idx)
3956     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3957     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3958     BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3959     MachineInstr *NewMI =
3960         addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3961             .addReg(SrcReg, getKillRegState(isKill));
3962     MachineOperand &MO = NewMI->getOperand(2);
3963     MO.setReg(VirtReg);
3964     MO.setIsKill(true);
3965   } else {
3966     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3967     bool isAligned =
3968         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3969         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3970     unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3971     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3972         .addReg(SrcReg, getKillRegState(isKill));
3973   }
3974 }
3975 
3976 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3977                                         MachineBasicBlock::iterator MI,
3978                                         Register DestReg, int FrameIdx,
3979                                         const TargetRegisterClass *RC,
3980                                         const TargetRegisterInfo *TRI) const {
3981   if (RC->getID() == X86::TILERegClassID) {
3982     unsigned Opc = X86::TILELOADD;
3983     // tileloadd (%sp, %idx), %tmm
3984     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3985     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3986     MachineInstr *NewMI =
3987         BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3988     NewMI = addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3989                               FrameIdx);
3990     MachineOperand &MO = NewMI->getOperand(3);
3991     MO.setReg(VirtReg);
3992     MO.setIsKill(true);
3993   } else {
3994     const MachineFunction &MF = *MBB.getParent();
3995     const MachineFrameInfo &MFI = MF.getFrameInfo();
3996     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3997     bool isAligned =
3998         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3999         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
4000     unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4001     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
4002                       FrameIdx);
4003   }
4004 }
4005 
4006 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
4007                                   Register &SrcReg2, int64_t &CmpMask,
4008                                   int64_t &CmpValue) const {
4009   switch (MI.getOpcode()) {
4010   default: break;
4011   case X86::CMP64ri32:
4012   case X86::CMP64ri8:
4013   case X86::CMP32ri:
4014   case X86::CMP32ri8:
4015   case X86::CMP16ri:
4016   case X86::CMP16ri8:
4017   case X86::CMP8ri:
4018     SrcReg = MI.getOperand(0).getReg();
4019     SrcReg2 = 0;
4020     if (MI.getOperand(1).isImm()) {
4021       CmpMask = ~0;
4022       CmpValue = MI.getOperand(1).getImm();
4023     } else {
4024       CmpMask = CmpValue = 0;
4025     }
4026     return true;
4027   // A SUB can be used to perform comparison.
4028   case X86::SUB64rm:
4029   case X86::SUB32rm:
4030   case X86::SUB16rm:
4031   case X86::SUB8rm:
4032     SrcReg = MI.getOperand(1).getReg();
4033     SrcReg2 = 0;
4034     CmpMask = 0;
4035     CmpValue = 0;
4036     return true;
4037   case X86::SUB64rr:
4038   case X86::SUB32rr:
4039   case X86::SUB16rr:
4040   case X86::SUB8rr:
4041     SrcReg = MI.getOperand(1).getReg();
4042     SrcReg2 = MI.getOperand(2).getReg();
4043     CmpMask = 0;
4044     CmpValue = 0;
4045     return true;
4046   case X86::SUB64ri32:
4047   case X86::SUB64ri8:
4048   case X86::SUB32ri:
4049   case X86::SUB32ri8:
4050   case X86::SUB16ri:
4051   case X86::SUB16ri8:
4052   case X86::SUB8ri:
4053     SrcReg = MI.getOperand(1).getReg();
4054     SrcReg2 = 0;
4055     if (MI.getOperand(2).isImm()) {
4056       CmpMask = ~0;
4057       CmpValue = MI.getOperand(2).getImm();
4058     } else {
4059       CmpMask = CmpValue = 0;
4060     }
4061     return true;
4062   case X86::CMP64rr:
4063   case X86::CMP32rr:
4064   case X86::CMP16rr:
4065   case X86::CMP8rr:
4066     SrcReg = MI.getOperand(0).getReg();
4067     SrcReg2 = MI.getOperand(1).getReg();
4068     CmpMask = 0;
4069     CmpValue = 0;
4070     return true;
4071   case X86::TEST8rr:
4072   case X86::TEST16rr:
4073   case X86::TEST32rr:
4074   case X86::TEST64rr:
4075     SrcReg = MI.getOperand(0).getReg();
4076     if (MI.getOperand(1).getReg() != SrcReg)
4077       return false;
4078     // Compare against zero.
4079     SrcReg2 = 0;
4080     CmpMask = ~0;
4081     CmpValue = 0;
4082     return true;
4083   }
4084   return false;
4085 }
4086 
4087 bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
4088                                         Register SrcReg, Register SrcReg2,
4089                                         int64_t ImmMask, int64_t ImmValue,
4090                                         const MachineInstr &OI, bool *IsSwapped,
4091                                         int64_t *ImmDelta) const {
4092   switch (OI.getOpcode()) {
4093   case X86::CMP64rr:
4094   case X86::CMP32rr:
4095   case X86::CMP16rr:
4096   case X86::CMP8rr:
4097   case X86::SUB64rr:
4098   case X86::SUB32rr:
4099   case X86::SUB16rr:
4100   case X86::SUB8rr: {
4101     Register OISrcReg;
4102     Register OISrcReg2;
4103     int64_t OIMask;
4104     int64_t OIValue;
4105     if (!analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) ||
4106         OIMask != ImmMask || OIValue != ImmValue)
4107       return false;
4108     if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
4109       *IsSwapped = false;
4110       return true;
4111     }
4112     if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
4113       *IsSwapped = true;
4114       return true;
4115     }
4116     return false;
4117   }
4118   case X86::CMP64ri32:
4119   case X86::CMP64ri8:
4120   case X86::CMP32ri:
4121   case X86::CMP32ri8:
4122   case X86::CMP16ri:
4123   case X86::CMP16ri8:
4124   case X86::CMP8ri:
4125   case X86::SUB64ri32:
4126   case X86::SUB64ri8:
4127   case X86::SUB32ri:
4128   case X86::SUB32ri8:
4129   case X86::SUB16ri:
4130   case X86::SUB16ri8:
4131   case X86::SUB8ri:
4132   case X86::TEST64rr:
4133   case X86::TEST32rr:
4134   case X86::TEST16rr:
4135   case X86::TEST8rr: {
4136     if (ImmMask != 0) {
4137       Register OISrcReg;
4138       Register OISrcReg2;
4139       int64_t OIMask;
4140       int64_t OIValue;
4141       if (analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) &&
4142           SrcReg == OISrcReg && ImmMask == OIMask) {
4143         if (OIValue == ImmValue) {
4144           *ImmDelta = 0;
4145           return true;
4146         } else if (static_cast<uint64_t>(ImmValue) ==
4147                    static_cast<uint64_t>(OIValue) - 1) {
4148           *ImmDelta = -1;
4149           return true;
4150         } else if (static_cast<uint64_t>(ImmValue) ==
4151                    static_cast<uint64_t>(OIValue) + 1) {
4152           *ImmDelta = 1;
4153           return true;
4154         } else {
4155           return false;
4156         }
4157       }
4158     }
4159     return FlagI.isIdenticalTo(OI);
4160   }
4161   default:
4162     return false;
4163   }
4164 }
4165 
4166 /// Check whether the definition can be converted
4167 /// to remove a comparison against zero.
4168 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
4169                                     bool &ClearsOverflowFlag) {
4170   NoSignFlag = false;
4171   ClearsOverflowFlag = false;
4172 
4173   switch (MI.getOpcode()) {
4174   default: return false;
4175 
4176   // The shift instructions only modify ZF if their shift count is non-zero.
4177   // N.B.: The processor truncates the shift count depending on the encoding.
4178   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4179   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4180      return getTruncatedShiftCount(MI, 2) != 0;
4181 
4182   // Some left shift instructions can be turned into LEA instructions but only
4183   // if their flags aren't used. Avoid transforming such instructions.
4184   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4185     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4186     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4187     return ShAmt != 0;
4188   }
4189 
4190   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4191   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4192      return getTruncatedShiftCount(MI, 3) != 0;
4193 
4194   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4195   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4196   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4197   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4198   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4199   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4200   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4201   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4202   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4203   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4204   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4205   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4206   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
4207   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
4208   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
4209   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
4210   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
4211   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4212   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
4213   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
4214   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
4215   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
4216   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4217   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4218   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4219   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4220   case X86::LZCNT16rr: case X86::LZCNT16rm:
4221   case X86::LZCNT32rr: case X86::LZCNT32rm:
4222   case X86::LZCNT64rr: case X86::LZCNT64rm:
4223   case X86::POPCNT16rr:case X86::POPCNT16rm:
4224   case X86::POPCNT32rr:case X86::POPCNT32rm:
4225   case X86::POPCNT64rr:case X86::POPCNT64rm:
4226   case X86::TZCNT16rr: case X86::TZCNT16rm:
4227   case X86::TZCNT32rr: case X86::TZCNT32rm:
4228   case X86::TZCNT64rr: case X86::TZCNT64rm:
4229     return true;
4230   case X86::AND64ri32:   case X86::AND64ri8:  case X86::AND32ri:
4231   case X86::AND32ri8:    case X86::AND16ri:   case X86::AND16ri8:
4232   case X86::AND8ri:      case X86::AND64rr:   case X86::AND32rr:
4233   case X86::AND16rr:     case X86::AND8rr:    case X86::AND64rm:
4234   case X86::AND32rm:     case X86::AND16rm:   case X86::AND8rm:
4235   case X86::XOR64ri32:   case X86::XOR64ri8:  case X86::XOR32ri:
4236   case X86::XOR32ri8:    case X86::XOR16ri:   case X86::XOR16ri8:
4237   case X86::XOR8ri:      case X86::XOR64rr:   case X86::XOR32rr:
4238   case X86::XOR16rr:     case X86::XOR8rr:    case X86::XOR64rm:
4239   case X86::XOR32rm:     case X86::XOR16rm:   case X86::XOR8rm:
4240   case X86::OR64ri32:    case X86::OR64ri8:   case X86::OR32ri:
4241   case X86::OR32ri8:     case X86::OR16ri:    case X86::OR16ri8:
4242   case X86::OR8ri:       case X86::OR64rr:    case X86::OR32rr:
4243   case X86::OR16rr:      case X86::OR8rr:     case X86::OR64rm:
4244   case X86::OR32rm:      case X86::OR16rm:    case X86::OR8rm:
4245   case X86::ANDN32rr:    case X86::ANDN32rm:
4246   case X86::ANDN64rr:    case X86::ANDN64rm:
4247   case X86::BLSI32rr:    case X86::BLSI32rm:
4248   case X86::BLSI64rr:    case X86::BLSI64rm:
4249   case X86::BLSMSK32rr:  case X86::BLSMSK32rm:
4250   case X86::BLSMSK64rr:  case X86::BLSMSK64rm:
4251   case X86::BLSR32rr:    case X86::BLSR32rm:
4252   case X86::BLSR64rr:    case X86::BLSR64rm:
4253   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4254   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4255   case X86::BLCI32rr:    case X86::BLCI32rm:
4256   case X86::BLCI64rr:    case X86::BLCI64rm:
4257   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4258   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4259   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4260   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4261   case X86::BLCS32rr:    case X86::BLCS32rm:
4262   case X86::BLCS64rr:    case X86::BLCS64rm:
4263   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4264   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4265   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4266   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4267   case X86::BZHI32rr:    case X86::BZHI32rm:
4268   case X86::BZHI64rr:    case X86::BZHI64rm:
4269   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4270   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4271   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4272   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4273     // These instructions clear the overflow flag just like TEST.
4274     // FIXME: These are not the only instructions in this switch that clear the
4275     // overflow flag.
4276     ClearsOverflowFlag = true;
4277     return true;
4278   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4279   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4280   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4281   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4282     // BEXTR doesn't update the sign flag so we can't use it. It does clear
4283     // the overflow flag, but that's not useful without the sign flag.
4284     NoSignFlag = true;
4285     return true;
4286   }
4287 }
4288 
4289 /// Check whether the use can be converted to remove a comparison against zero.
4290 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4291   switch (MI.getOpcode()) {
4292   default: return X86::COND_INVALID;
4293   case X86::NEG8r:
4294   case X86::NEG16r:
4295   case X86::NEG32r:
4296   case X86::NEG64r:
4297     return X86::COND_AE;
4298   case X86::LZCNT16rr:
4299   case X86::LZCNT32rr:
4300   case X86::LZCNT64rr:
4301     return X86::COND_B;
4302   case X86::POPCNT16rr:
4303   case X86::POPCNT32rr:
4304   case X86::POPCNT64rr:
4305     return X86::COND_E;
4306   case X86::TZCNT16rr:
4307   case X86::TZCNT32rr:
4308   case X86::TZCNT64rr:
4309     return X86::COND_B;
4310   case X86::BSF16rr:
4311   case X86::BSF32rr:
4312   case X86::BSF64rr:
4313   case X86::BSR16rr:
4314   case X86::BSR32rr:
4315   case X86::BSR64rr:
4316     return X86::COND_E;
4317   case X86::BLSI32rr:
4318   case X86::BLSI64rr:
4319     return X86::COND_AE;
4320   case X86::BLSR32rr:
4321   case X86::BLSR64rr:
4322   case X86::BLSMSK32rr:
4323   case X86::BLSMSK64rr:
4324     return X86::COND_B;
4325   // TODO: TBM instructions.
4326   }
4327 }
4328 
4329 /// Check if there exists an earlier instruction that
4330 /// operates on the same source operands and sets flags in the same way as
4331 /// Compare; remove Compare if possible.
4332 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4333                                         Register SrcReg2, int64_t CmpMask,
4334                                         int64_t CmpValue,
4335                                         const MachineRegisterInfo *MRI) const {
4336   // Check whether we can replace SUB with CMP.
4337   switch (CmpInstr.getOpcode()) {
4338   default: break;
4339   case X86::SUB64ri32:
4340   case X86::SUB64ri8:
4341   case X86::SUB32ri:
4342   case X86::SUB32ri8:
4343   case X86::SUB16ri:
4344   case X86::SUB16ri8:
4345   case X86::SUB8ri:
4346   case X86::SUB64rm:
4347   case X86::SUB32rm:
4348   case X86::SUB16rm:
4349   case X86::SUB8rm:
4350   case X86::SUB64rr:
4351   case X86::SUB32rr:
4352   case X86::SUB16rr:
4353   case X86::SUB8rr: {
4354     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4355       return false;
4356     // There is no use of the destination register, we can replace SUB with CMP.
4357     unsigned NewOpcode = 0;
4358     switch (CmpInstr.getOpcode()) {
4359     default: llvm_unreachable("Unreachable!");
4360     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4361     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4362     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4363     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4364     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4365     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4366     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4367     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4368     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4369     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4370     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4371     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4372     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4373     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4374     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4375     }
4376     CmpInstr.setDesc(get(NewOpcode));
4377     CmpInstr.removeOperand(0);
4378     // Mutating this instruction invalidates any debug data associated with it.
4379     CmpInstr.dropDebugNumber();
4380     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4381     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4382         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4383       return false;
4384   }
4385   }
4386 
4387   // The following code tries to remove the comparison by re-using EFLAGS
4388   // from earlier instructions.
4389 
4390   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4391 
4392   // Transformation currently requires SSA values.
4393   if (SrcReg2.isPhysical())
4394     return false;
4395   MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
4396   assert(SrcRegDef && "Must have a definition (SSA)");
4397 
4398   MachineInstr *MI = nullptr;
4399   MachineInstr *Sub = nullptr;
4400   MachineInstr *Movr0Inst = nullptr;
4401   bool NoSignFlag = false;
4402   bool ClearsOverflowFlag = false;
4403   bool ShouldUpdateCC = false;
4404   bool IsSwapped = false;
4405   X86::CondCode NewCC = X86::COND_INVALID;
4406   int64_t ImmDelta = 0;
4407 
4408   // Search backward from CmpInstr for the next instruction defining EFLAGS.
4409   const TargetRegisterInfo *TRI = &getRegisterInfo();
4410   MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
4411   MachineBasicBlock::reverse_iterator From =
4412       std::next(MachineBasicBlock::reverse_iterator(CmpInstr));
4413   for (MachineBasicBlock *MBB = &CmpMBB;;) {
4414     for (MachineInstr &Inst : make_range(From, MBB->rend())) {
4415       // Try to use EFLAGS from the instruction defining %SrcReg. Example:
4416       //     %eax = addl ...
4417       //     ...                // EFLAGS not changed
4418       //     testl %eax, %eax   // <-- can be removed
4419       if (&Inst == SrcRegDef) {
4420         if (IsCmpZero &&
4421             isDefConvertible(Inst, NoSignFlag, ClearsOverflowFlag)) {
4422           MI = &Inst;
4423           break;
4424         }
4425         // Cannot find other candidates before definition of SrcReg.
4426         return false;
4427       }
4428 
4429       if (Inst.modifiesRegister(X86::EFLAGS, TRI)) {
4430         // Try to use EFLAGS produced by an instruction reading %SrcReg.
4431         // Example:
4432         //      %eax = ...
4433         //      ...
4434         //      popcntl %eax
4435         //      ...                 // EFLAGS not changed
4436         //      testl %eax, %eax    // <-- can be removed
4437         if (IsCmpZero) {
4438           NewCC = isUseDefConvertible(Inst);
4439           if (NewCC != X86::COND_INVALID && Inst.getOperand(1).isReg() &&
4440               Inst.getOperand(1).getReg() == SrcReg) {
4441             ShouldUpdateCC = true;
4442             MI = &Inst;
4443             break;
4444           }
4445         }
4446 
4447         // Try to use EFLAGS from an instruction with similar flag results.
4448         // Example:
4449         //     sub x, y  or  cmp x, y
4450         //     ...           // EFLAGS not changed
4451         //     cmp x, y      // <-- can be removed
4452         if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
4453                                  Inst, &IsSwapped, &ImmDelta)) {
4454           Sub = &Inst;
4455           break;
4456         }
4457 
4458         // MOV32r0 is implemented with xor which clobbers condition code. It is
4459         // safe to move up, if the definition to EFLAGS is dead and earlier
4460         // instructions do not read or write EFLAGS.
4461         if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
4462             Inst.registerDefIsDead(X86::EFLAGS, TRI)) {
4463           Movr0Inst = &Inst;
4464           continue;
4465         }
4466 
4467         // Cannot do anything for any other EFLAG changes.
4468         return false;
4469       }
4470     }
4471 
4472     if (MI || Sub)
4473       break;
4474 
4475     // Reached begin of basic block. Continue in predecessor if there is
4476     // exactly one.
4477     if (MBB->pred_size() != 1)
4478       return false;
4479     MBB = *MBB->pred_begin();
4480     From = MBB->rbegin();
4481   }
4482 
4483   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4484   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4485   // If we are done with the basic block, we need to check whether EFLAGS is
4486   // live-out.
4487   bool FlagsMayLiveOut = true;
4488   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4489   MachineBasicBlock::iterator AfterCmpInstr =
4490       std::next(MachineBasicBlock::iterator(CmpInstr));
4491   for (MachineInstr &Instr : make_range(AfterCmpInstr, CmpMBB.end())) {
4492     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4493     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4494     // We should check the usage if this instruction uses and updates EFLAGS.
4495     if (!UseEFLAGS && ModifyEFLAGS) {
4496       // It is safe to remove CmpInstr if EFLAGS is updated again.
4497       FlagsMayLiveOut = false;
4498       break;
4499     }
4500     if (!UseEFLAGS && !ModifyEFLAGS)
4501       continue;
4502 
4503     // EFLAGS is used by this instruction.
4504     X86::CondCode OldCC = X86::COND_INVALID;
4505     if (MI || IsSwapped || ImmDelta != 0) {
4506       // We decode the condition code from opcode.
4507       if (Instr.isBranch())
4508         OldCC = X86::getCondFromBranch(Instr);
4509       else {
4510         OldCC = X86::getCondFromSETCC(Instr);
4511         if (OldCC == X86::COND_INVALID)
4512           OldCC = X86::getCondFromCMov(Instr);
4513       }
4514       if (OldCC == X86::COND_INVALID) return false;
4515     }
4516     X86::CondCode ReplacementCC = X86::COND_INVALID;
4517     if (MI) {
4518       switch (OldCC) {
4519       default: break;
4520       case X86::COND_A: case X86::COND_AE:
4521       case X86::COND_B: case X86::COND_BE:
4522         // CF is used, we can't perform this optimization.
4523         return false;
4524       case X86::COND_G: case X86::COND_GE:
4525       case X86::COND_L: case X86::COND_LE:
4526       case X86::COND_O: case X86::COND_NO:
4527         // If OF is used, the instruction needs to clear it like CmpZero does.
4528         if (!ClearsOverflowFlag)
4529           return false;
4530         break;
4531       case X86::COND_S: case X86::COND_NS:
4532         // If SF is used, but the instruction doesn't update the SF, then we
4533         // can't do the optimization.
4534         if (NoSignFlag)
4535           return false;
4536         break;
4537       }
4538 
4539       // If we're updating the condition code check if we have to reverse the
4540       // condition.
4541       if (ShouldUpdateCC)
4542         switch (OldCC) {
4543         default:
4544           return false;
4545         case X86::COND_E:
4546           ReplacementCC = NewCC;
4547           break;
4548         case X86::COND_NE:
4549           ReplacementCC = GetOppositeBranchCondition(NewCC);
4550           break;
4551         }
4552     } else if (IsSwapped) {
4553       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4554       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4555       // We swap the condition code and synthesize the new opcode.
4556       ReplacementCC = getSwappedCondition(OldCC);
4557       if (ReplacementCC == X86::COND_INVALID)
4558         return false;
4559       ShouldUpdateCC = true;
4560     } else if (ImmDelta != 0) {
4561       unsigned BitWidth = TRI->getRegSizeInBits(*MRI->getRegClass(SrcReg));
4562       // Shift amount for min/max constants to adjust for 8/16/32 instruction
4563       // sizes.
4564       switch (OldCC) {
4565       case X86::COND_L: // x <s (C + 1)  -->  x <=s C
4566         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4567           return false;
4568         ReplacementCC = X86::COND_LE;
4569         break;
4570       case X86::COND_B: // x <u (C + 1)  -->  x <=u C
4571         if (ImmDelta != 1 || CmpValue == 0)
4572           return false;
4573         ReplacementCC = X86::COND_BE;
4574         break;
4575       case X86::COND_GE: // x >=s (C + 1)  -->  x >s C
4576         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4577           return false;
4578         ReplacementCC = X86::COND_G;
4579         break;
4580       case X86::COND_AE: // x >=u (C + 1)  -->  x >u C
4581         if (ImmDelta != 1 || CmpValue == 0)
4582           return false;
4583         ReplacementCC = X86::COND_A;
4584         break;
4585       case X86::COND_G: // x >s (C - 1)  -->  x >=s C
4586         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4587           return false;
4588         ReplacementCC = X86::COND_GE;
4589         break;
4590       case X86::COND_A: // x >u (C - 1)  -->  x >=u C
4591         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4592           return false;
4593         ReplacementCC = X86::COND_AE;
4594         break;
4595       case X86::COND_LE: // x <=s (C - 1)  -->  x <s C
4596         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4597           return false;
4598         ReplacementCC = X86::COND_L;
4599         break;
4600       case X86::COND_BE: // x <=u (C - 1)  -->  x <u C
4601         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4602           return false;
4603         ReplacementCC = X86::COND_B;
4604         break;
4605       default:
4606         return false;
4607       }
4608       ShouldUpdateCC = true;
4609     }
4610 
4611     if (ShouldUpdateCC && ReplacementCC != OldCC) {
4612       // Push the MachineInstr to OpsToUpdate.
4613       // If it is safe to remove CmpInstr, the condition code of these
4614       // instructions will be modified.
4615       OpsToUpdate.push_back(std::make_pair(&Instr, ReplacementCC));
4616     }
4617     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4618       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4619       FlagsMayLiveOut = false;
4620       break;
4621     }
4622   }
4623 
4624   // If we have to update users but EFLAGS is live-out abort, since we cannot
4625   // easily find all of the users.
4626   if ((MI != nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
4627     for (MachineBasicBlock *Successor : CmpMBB.successors())
4628       if (Successor->isLiveIn(X86::EFLAGS))
4629         return false;
4630   }
4631 
4632   // The instruction to be updated is either Sub or MI.
4633   assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
4634   Sub = MI != nullptr ? MI : Sub;
4635   MachineBasicBlock *SubBB = Sub->getParent();
4636   // Move Movr0Inst to the appropriate place before Sub.
4637   if (Movr0Inst) {
4638     // Only move within the same block so we don't accidentally move to a
4639     // block with higher execution frequency.
4640     if (&CmpMBB != SubBB)
4641       return false;
4642     // Look backwards until we find a def that doesn't use the current EFLAGS.
4643     MachineBasicBlock::reverse_iterator InsertI = Sub,
4644                                         InsertE = Sub->getParent()->rend();
4645     for (; InsertI != InsertE; ++InsertI) {
4646       MachineInstr *Instr = &*InsertI;
4647       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4648           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4649         Movr0Inst->getParent()->remove(Movr0Inst);
4650         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4651                                    Movr0Inst);
4652         break;
4653       }
4654     }
4655     if (InsertI == InsertE)
4656       return false;
4657   }
4658 
4659   // Make sure Sub instruction defines EFLAGS and mark the def live.
4660   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4661   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4662   FlagDef->setIsDead(false);
4663 
4664   CmpInstr.eraseFromParent();
4665 
4666   // Modify the condition code of instructions in OpsToUpdate.
4667   for (auto &Op : OpsToUpdate) {
4668     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4669         .setImm(Op.second);
4670   }
4671   // Add EFLAGS to block live-ins between CmpBB and block of flags producer.
4672   for (MachineBasicBlock *MBB = &CmpMBB; MBB != SubBB;
4673        MBB = *MBB->pred_begin()) {
4674     assert(MBB->pred_size() == 1 && "Expected exactly one predecessor");
4675     if (!MBB->isLiveIn(X86::EFLAGS))
4676       MBB->addLiveIn(X86::EFLAGS);
4677   }
4678   return true;
4679 }
4680 
4681 /// Try to remove the load by folding it to a register
4682 /// operand at the use. We fold the load instructions if load defines a virtual
4683 /// register, the virtual register is used once in the same BB, and the
4684 /// instructions in-between do not load or store, and have no side effects.
4685 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4686                                               const MachineRegisterInfo *MRI,
4687                                               Register &FoldAsLoadDefReg,
4688                                               MachineInstr *&DefMI) const {
4689   // Check whether we can move DefMI here.
4690   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4691   assert(DefMI);
4692   bool SawStore = false;
4693   if (!DefMI->isSafeToMove(nullptr, SawStore))
4694     return nullptr;
4695 
4696   // Collect information about virtual register operands of MI.
4697   SmallVector<unsigned, 1> SrcOperandIds;
4698   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4699     MachineOperand &MO = MI.getOperand(i);
4700     if (!MO.isReg())
4701       continue;
4702     Register Reg = MO.getReg();
4703     if (Reg != FoldAsLoadDefReg)
4704       continue;
4705     // Do not fold if we have a subreg use or a def.
4706     if (MO.getSubReg() || MO.isDef())
4707       return nullptr;
4708     SrcOperandIds.push_back(i);
4709   }
4710   if (SrcOperandIds.empty())
4711     return nullptr;
4712 
4713   // Check whether we can fold the def into SrcOperandId.
4714   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4715     FoldAsLoadDefReg = 0;
4716     return FoldMI;
4717   }
4718 
4719   return nullptr;
4720 }
4721 
4722 /// Expand a single-def pseudo instruction to a two-addr
4723 /// instruction with two undef reads of the register being defined.
4724 /// This is used for mapping:
4725 ///   %xmm4 = V_SET0
4726 /// to:
4727 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4728 ///
4729 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4730                              const MCInstrDesc &Desc) {
4731   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4732   Register Reg = MIB.getReg(0);
4733   MIB->setDesc(Desc);
4734 
4735   // MachineInstr::addOperand() will insert explicit operands before any
4736   // implicit operands.
4737   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4738   // But we don't trust that.
4739   assert(MIB.getReg(1) == Reg &&
4740          MIB.getReg(2) == Reg && "Misplaced operand");
4741   return true;
4742 }
4743 
4744 /// Expand a single-def pseudo instruction to a two-addr
4745 /// instruction with two %k0 reads.
4746 /// This is used for mapping:
4747 ///   %k4 = K_SET1
4748 /// to:
4749 ///   %k4 = KXNORrr %k0, %k0
4750 static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4751                             Register Reg) {
4752   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4753   MIB->setDesc(Desc);
4754   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4755   return true;
4756 }
4757 
4758 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4759                           bool MinusOne) {
4760   MachineBasicBlock &MBB = *MIB->getParent();
4761   const DebugLoc &DL = MIB->getDebugLoc();
4762   Register Reg = MIB.getReg(0);
4763 
4764   // Insert the XOR.
4765   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4766       .addReg(Reg, RegState::Undef)
4767       .addReg(Reg, RegState::Undef);
4768 
4769   // Turn the pseudo into an INC or DEC.
4770   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4771   MIB.addReg(Reg);
4772 
4773   return true;
4774 }
4775 
4776 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4777                                const TargetInstrInfo &TII,
4778                                const X86Subtarget &Subtarget) {
4779   MachineBasicBlock &MBB = *MIB->getParent();
4780   const DebugLoc &DL = MIB->getDebugLoc();
4781   int64_t Imm = MIB->getOperand(1).getImm();
4782   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4783   MachineBasicBlock::iterator I = MIB.getInstr();
4784 
4785   int StackAdjustment;
4786 
4787   if (Subtarget.is64Bit()) {
4788     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4789            MIB->getOpcode() == X86::MOV32ImmSExti8);
4790 
4791     // Can't use push/pop lowering if the function might write to the red zone.
4792     X86MachineFunctionInfo *X86FI =
4793         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4794     if (X86FI->getUsesRedZone()) {
4795       MIB->setDesc(TII.get(MIB->getOpcode() ==
4796                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4797       return true;
4798     }
4799 
4800     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4801     // widen the register if necessary.
4802     StackAdjustment = 8;
4803     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4804     MIB->setDesc(TII.get(X86::POP64r));
4805     MIB->getOperand(0)
4806         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4807   } else {
4808     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4809     StackAdjustment = 4;
4810     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4811     MIB->setDesc(TII.get(X86::POP32r));
4812   }
4813   MIB->removeOperand(1);
4814   MIB->addImplicitDefUseOperands(*MBB.getParent());
4815 
4816   // Build CFI if necessary.
4817   MachineFunction &MF = *MBB.getParent();
4818   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4819   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4820   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4821   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4822   if (EmitCFI) {
4823     TFL->BuildCFI(MBB, I, DL,
4824         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4825     TFL->BuildCFI(MBB, std::next(I), DL,
4826         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4827   }
4828 
4829   return true;
4830 }
4831 
4832 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4833 // code sequence is needed for other targets.
4834 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4835                                  const TargetInstrInfo &TII) {
4836   MachineBasicBlock &MBB = *MIB->getParent();
4837   const DebugLoc &DL = MIB->getDebugLoc();
4838   Register Reg = MIB.getReg(0);
4839   const GlobalValue *GV =
4840       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4841   auto Flags = MachineMemOperand::MOLoad |
4842                MachineMemOperand::MODereferenceable |
4843                MachineMemOperand::MOInvariant;
4844   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4845       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4846   MachineBasicBlock::iterator I = MIB.getInstr();
4847 
4848   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4849       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4850       .addMemOperand(MMO);
4851   MIB->setDebugLoc(DL);
4852   MIB->setDesc(TII.get(X86::MOV64rm));
4853   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4854 }
4855 
4856 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4857   MachineBasicBlock &MBB = *MIB->getParent();
4858   MachineFunction &MF = *MBB.getParent();
4859   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4860   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4861   unsigned XorOp =
4862       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4863   MIB->setDesc(TII.get(XorOp));
4864   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4865   return true;
4866 }
4867 
4868 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4869 // but not VLX. If it uses an extended register we need to use an instruction
4870 // that loads the lower 128/256-bit, but is available with only AVX512F.
4871 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4872                             const TargetRegisterInfo *TRI,
4873                             const MCInstrDesc &LoadDesc,
4874                             const MCInstrDesc &BroadcastDesc,
4875                             unsigned SubIdx) {
4876   Register DestReg = MIB.getReg(0);
4877   // Check if DestReg is XMM16-31 or YMM16-31.
4878   if (TRI->getEncodingValue(DestReg) < 16) {
4879     // We can use a normal VEX encoded load.
4880     MIB->setDesc(LoadDesc);
4881   } else {
4882     // Use a 128/256-bit VBROADCAST instruction.
4883     MIB->setDesc(BroadcastDesc);
4884     // Change the destination to a 512-bit register.
4885     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4886     MIB->getOperand(0).setReg(DestReg);
4887   }
4888   return true;
4889 }
4890 
4891 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4892 // but not VLX. If it uses an extended register we need to use an instruction
4893 // that stores the lower 128/256-bit, but is available with only AVX512F.
4894 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4895                              const TargetRegisterInfo *TRI,
4896                              const MCInstrDesc &StoreDesc,
4897                              const MCInstrDesc &ExtractDesc,
4898                              unsigned SubIdx) {
4899   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4900   // Check if DestReg is XMM16-31 or YMM16-31.
4901   if (TRI->getEncodingValue(SrcReg) < 16) {
4902     // We can use a normal VEX encoded store.
4903     MIB->setDesc(StoreDesc);
4904   } else {
4905     // Use a VEXTRACTF instruction.
4906     MIB->setDesc(ExtractDesc);
4907     // Change the destination to a 512-bit register.
4908     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4909     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4910     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4911   }
4912 
4913   return true;
4914 }
4915 
4916 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4917   MIB->setDesc(Desc);
4918   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4919   // Temporarily remove the immediate so we can add another source register.
4920   MIB->removeOperand(2);
4921   // Add the register. Don't copy the kill flag if there is one.
4922   MIB.addReg(MIB.getReg(1),
4923              getUndefRegState(MIB->getOperand(1).isUndef()));
4924   // Add back the immediate.
4925   MIB.addImm(ShiftAmt);
4926   return true;
4927 }
4928 
4929 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4930   bool HasAVX = Subtarget.hasAVX();
4931   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4932   switch (MI.getOpcode()) {
4933   case X86::MOV32r0:
4934     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4935   case X86::MOV32r1:
4936     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4937   case X86::MOV32r_1:
4938     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4939   case X86::MOV32ImmSExti8:
4940   case X86::MOV64ImmSExti8:
4941     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4942   case X86::SETB_C32r:
4943     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4944   case X86::SETB_C64r:
4945     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4946   case X86::MMX_SET0:
4947     return Expand2AddrUndef(MIB, get(X86::MMX_PXORrr));
4948   case X86::V_SET0:
4949   case X86::FsFLD0SS:
4950   case X86::FsFLD0SD:
4951   case X86::FsFLD0F128:
4952     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4953   case X86::AVX_SET0: {
4954     assert(HasAVX && "AVX not supported");
4955     const TargetRegisterInfo *TRI = &getRegisterInfo();
4956     Register SrcReg = MIB.getReg(0);
4957     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4958     MIB->getOperand(0).setReg(XReg);
4959     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4960     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4961     return true;
4962   }
4963   case X86::AVX512_128_SET0:
4964   case X86::AVX512_FsFLD0SH:
4965   case X86::AVX512_FsFLD0SS:
4966   case X86::AVX512_FsFLD0SD:
4967   case X86::AVX512_FsFLD0F128: {
4968     bool HasVLX = Subtarget.hasVLX();
4969     Register SrcReg = MIB.getReg(0);
4970     const TargetRegisterInfo *TRI = &getRegisterInfo();
4971     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4972       return Expand2AddrUndef(MIB,
4973                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4974     // Extended register without VLX. Use a larger XOR.
4975     SrcReg =
4976         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4977     MIB->getOperand(0).setReg(SrcReg);
4978     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4979   }
4980   case X86::AVX512_256_SET0:
4981   case X86::AVX512_512_SET0: {
4982     bool HasVLX = Subtarget.hasVLX();
4983     Register SrcReg = MIB.getReg(0);
4984     const TargetRegisterInfo *TRI = &getRegisterInfo();
4985     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4986       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4987       MIB->getOperand(0).setReg(XReg);
4988       Expand2AddrUndef(MIB,
4989                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4990       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4991       return true;
4992     }
4993     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4994       // No VLX so we must reference a zmm.
4995       unsigned ZReg =
4996         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4997       MIB->getOperand(0).setReg(ZReg);
4998     }
4999     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5000   }
5001   case X86::V_SETALLONES:
5002     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5003   case X86::AVX2_SETALLONES:
5004     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5005   case X86::AVX1_SETALLONES: {
5006     Register Reg = MIB.getReg(0);
5007     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
5008     MIB->setDesc(get(X86::VCMPPSYrri));
5009     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
5010     return true;
5011   }
5012   case X86::AVX512_512_SETALLONES: {
5013     Register Reg = MIB.getReg(0);
5014     MIB->setDesc(get(X86::VPTERNLOGDZrri));
5015     // VPTERNLOGD needs 3 register inputs and an immediate.
5016     // 0xff will return 1s for any input.
5017     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5018        .addReg(Reg, RegState::Undef).addImm(0xff);
5019     return true;
5020   }
5021   case X86::AVX512_512_SEXT_MASK_32:
5022   case X86::AVX512_512_SEXT_MASK_64: {
5023     Register Reg = MIB.getReg(0);
5024     Register MaskReg = MIB.getReg(1);
5025     unsigned MaskState = getRegState(MIB->getOperand(1));
5026     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
5027                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
5028     MI.removeOperand(1);
5029     MIB->setDesc(get(Opc));
5030     // VPTERNLOG needs 3 register inputs and an immediate.
5031     // 0xff will return 1s for any input.
5032     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
5033        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
5034     return true;
5035   }
5036   case X86::VMOVAPSZ128rm_NOVLX:
5037     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
5038                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
5039   case X86::VMOVUPSZ128rm_NOVLX:
5040     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
5041                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
5042   case X86::VMOVAPSZ256rm_NOVLX:
5043     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
5044                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
5045   case X86::VMOVUPSZ256rm_NOVLX:
5046     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
5047                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
5048   case X86::VMOVAPSZ128mr_NOVLX:
5049     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
5050                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
5051   case X86::VMOVUPSZ128mr_NOVLX:
5052     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
5053                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
5054   case X86::VMOVAPSZ256mr_NOVLX:
5055     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
5056                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
5057   case X86::VMOVUPSZ256mr_NOVLX:
5058     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
5059                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
5060   case X86::MOV32ri64: {
5061     Register Reg = MIB.getReg(0);
5062     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
5063     MI.setDesc(get(X86::MOV32ri));
5064     MIB->getOperand(0).setReg(Reg32);
5065     MIB.addReg(Reg, RegState::ImplicitDefine);
5066     return true;
5067   }
5068 
5069   // KNL does not recognize dependency-breaking idioms for mask registers,
5070   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5071   // Using %k0 as the undef input register is a performance heuristic based
5072   // on the assumption that %k0 is used less frequently than the other mask
5073   // registers, since it is not usable as a write mask.
5074   // FIXME: A more advanced approach would be to choose the best input mask
5075   // register based on context.
5076   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5077   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5078   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5079   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5080   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5081   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5082   case TargetOpcode::LOAD_STACK_GUARD:
5083     expandLoadStackGuard(MIB, *this);
5084     return true;
5085   case X86::XOR64_FP:
5086   case X86::XOR32_FP:
5087     return expandXorFP(MIB, *this);
5088   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
5089   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
5090   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
5091   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
5092   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
5093   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
5094   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
5095   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
5096   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
5097   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
5098   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
5099   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
5100   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
5101   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
5102   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
5103   }
5104   return false;
5105 }
5106 
5107 /// Return true for all instructions that only update
5108 /// the first 32 or 64-bits of the destination register and leave the rest
5109 /// unmodified. This can be used to avoid folding loads if the instructions
5110 /// only update part of the destination register, and the non-updated part is
5111 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5112 /// instructions breaks the partial register dependency and it can improve
5113 /// performance. e.g.:
5114 ///
5115 ///   movss (%rdi), %xmm0
5116 ///   cvtss2sd %xmm0, %xmm0
5117 ///
5118 /// Instead of
5119 ///   cvtss2sd (%rdi), %xmm0
5120 ///
5121 /// FIXME: This should be turned into a TSFlags.
5122 ///
5123 static bool hasPartialRegUpdate(unsigned Opcode,
5124                                 const X86Subtarget &Subtarget,
5125                                 bool ForLoadFold = false) {
5126   switch (Opcode) {
5127   case X86::CVTSI2SSrr:
5128   case X86::CVTSI2SSrm:
5129   case X86::CVTSI642SSrr:
5130   case X86::CVTSI642SSrm:
5131   case X86::CVTSI2SDrr:
5132   case X86::CVTSI2SDrm:
5133   case X86::CVTSI642SDrr:
5134   case X86::CVTSI642SDrm:
5135     // Load folding won't effect the undef register update since the input is
5136     // a GPR.
5137     return !ForLoadFold;
5138   case X86::CVTSD2SSrr:
5139   case X86::CVTSD2SSrm:
5140   case X86::CVTSS2SDrr:
5141   case X86::CVTSS2SDrm:
5142   case X86::MOVHPDrm:
5143   case X86::MOVHPSrm:
5144   case X86::MOVLPDrm:
5145   case X86::MOVLPSrm:
5146   case X86::RCPSSr:
5147   case X86::RCPSSm:
5148   case X86::RCPSSr_Int:
5149   case X86::RCPSSm_Int:
5150   case X86::ROUNDSDr:
5151   case X86::ROUNDSDm:
5152   case X86::ROUNDSSr:
5153   case X86::ROUNDSSm:
5154   case X86::RSQRTSSr:
5155   case X86::RSQRTSSm:
5156   case X86::RSQRTSSr_Int:
5157   case X86::RSQRTSSm_Int:
5158   case X86::SQRTSSr:
5159   case X86::SQRTSSm:
5160   case X86::SQRTSSr_Int:
5161   case X86::SQRTSSm_Int:
5162   case X86::SQRTSDr:
5163   case X86::SQRTSDm:
5164   case X86::SQRTSDr_Int:
5165   case X86::SQRTSDm_Int:
5166     return true;
5167   // GPR
5168   case X86::POPCNT32rm:
5169   case X86::POPCNT32rr:
5170   case X86::POPCNT64rm:
5171   case X86::POPCNT64rr:
5172     return Subtarget.hasPOPCNTFalseDeps();
5173   case X86::LZCNT32rm:
5174   case X86::LZCNT32rr:
5175   case X86::LZCNT64rm:
5176   case X86::LZCNT64rr:
5177   case X86::TZCNT32rm:
5178   case X86::TZCNT32rr:
5179   case X86::TZCNT64rm:
5180   case X86::TZCNT64rr:
5181     return Subtarget.hasLZCNTFalseDeps();
5182   }
5183 
5184   return false;
5185 }
5186 
5187 /// Inform the BreakFalseDeps pass how many idle
5188 /// instructions we would like before a partial register update.
5189 unsigned X86InstrInfo::getPartialRegUpdateClearance(
5190     const MachineInstr &MI, unsigned OpNum,
5191     const TargetRegisterInfo *TRI) const {
5192   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
5193     return 0;
5194 
5195   // If MI is marked as reading Reg, the partial register update is wanted.
5196   const MachineOperand &MO = MI.getOperand(0);
5197   Register Reg = MO.getReg();
5198   if (Reg.isVirtual()) {
5199     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
5200       return 0;
5201   } else {
5202     if (MI.readsRegister(Reg, TRI))
5203       return 0;
5204   }
5205 
5206   // If any instructions in the clearance range are reading Reg, insert a
5207   // dependency breaking instruction, which is inexpensive and is likely to
5208   // be hidden in other instruction's cycles.
5209   return PartialRegUpdateClearance;
5210 }
5211 
5212 // Return true for any instruction the copies the high bits of the first source
5213 // operand into the unused high bits of the destination operand.
5214 // Also returns true for instructions that have two inputs where one may
5215 // be undef and we want it to use the same register as the other input.
5216 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
5217                               bool ForLoadFold = false) {
5218   // Set the OpNum parameter to the first source operand.
5219   switch (Opcode) {
5220   case X86::MMX_PUNPCKHBWrr:
5221   case X86::MMX_PUNPCKHWDrr:
5222   case X86::MMX_PUNPCKHDQrr:
5223   case X86::MMX_PUNPCKLBWrr:
5224   case X86::MMX_PUNPCKLWDrr:
5225   case X86::MMX_PUNPCKLDQrr:
5226   case X86::MOVHLPSrr:
5227   case X86::PACKSSWBrr:
5228   case X86::PACKUSWBrr:
5229   case X86::PACKSSDWrr:
5230   case X86::PACKUSDWrr:
5231   case X86::PUNPCKHBWrr:
5232   case X86::PUNPCKLBWrr:
5233   case X86::PUNPCKHWDrr:
5234   case X86::PUNPCKLWDrr:
5235   case X86::PUNPCKHDQrr:
5236   case X86::PUNPCKLDQrr:
5237   case X86::PUNPCKHQDQrr:
5238   case X86::PUNPCKLQDQrr:
5239   case X86::SHUFPDrri:
5240   case X86::SHUFPSrri:
5241     // These instructions are sometimes used with an undef first or second
5242     // source. Return true here so BreakFalseDeps will assign this source to the
5243     // same register as the first source to avoid a false dependency.
5244     // Operand 1 of these instructions is tied so they're separate from their
5245     // VEX counterparts.
5246     return OpNum == 2 && !ForLoadFold;
5247 
5248   case X86::VMOVLHPSrr:
5249   case X86::VMOVLHPSZrr:
5250   case X86::VPACKSSWBrr:
5251   case X86::VPACKUSWBrr:
5252   case X86::VPACKSSDWrr:
5253   case X86::VPACKUSDWrr:
5254   case X86::VPACKSSWBZ128rr:
5255   case X86::VPACKUSWBZ128rr:
5256   case X86::VPACKSSDWZ128rr:
5257   case X86::VPACKUSDWZ128rr:
5258   case X86::VPERM2F128rr:
5259   case X86::VPERM2I128rr:
5260   case X86::VSHUFF32X4Z256rri:
5261   case X86::VSHUFF32X4Zrri:
5262   case X86::VSHUFF64X2Z256rri:
5263   case X86::VSHUFF64X2Zrri:
5264   case X86::VSHUFI32X4Z256rri:
5265   case X86::VSHUFI32X4Zrri:
5266   case X86::VSHUFI64X2Z256rri:
5267   case X86::VSHUFI64X2Zrri:
5268   case X86::VPUNPCKHBWrr:
5269   case X86::VPUNPCKLBWrr:
5270   case X86::VPUNPCKHBWYrr:
5271   case X86::VPUNPCKLBWYrr:
5272   case X86::VPUNPCKHBWZ128rr:
5273   case X86::VPUNPCKLBWZ128rr:
5274   case X86::VPUNPCKHBWZ256rr:
5275   case X86::VPUNPCKLBWZ256rr:
5276   case X86::VPUNPCKHBWZrr:
5277   case X86::VPUNPCKLBWZrr:
5278   case X86::VPUNPCKHWDrr:
5279   case X86::VPUNPCKLWDrr:
5280   case X86::VPUNPCKHWDYrr:
5281   case X86::VPUNPCKLWDYrr:
5282   case X86::VPUNPCKHWDZ128rr:
5283   case X86::VPUNPCKLWDZ128rr:
5284   case X86::VPUNPCKHWDZ256rr:
5285   case X86::VPUNPCKLWDZ256rr:
5286   case X86::VPUNPCKHWDZrr:
5287   case X86::VPUNPCKLWDZrr:
5288   case X86::VPUNPCKHDQrr:
5289   case X86::VPUNPCKLDQrr:
5290   case X86::VPUNPCKHDQYrr:
5291   case X86::VPUNPCKLDQYrr:
5292   case X86::VPUNPCKHDQZ128rr:
5293   case X86::VPUNPCKLDQZ128rr:
5294   case X86::VPUNPCKHDQZ256rr:
5295   case X86::VPUNPCKLDQZ256rr:
5296   case X86::VPUNPCKHDQZrr:
5297   case X86::VPUNPCKLDQZrr:
5298   case X86::VPUNPCKHQDQrr:
5299   case X86::VPUNPCKLQDQrr:
5300   case X86::VPUNPCKHQDQYrr:
5301   case X86::VPUNPCKLQDQYrr:
5302   case X86::VPUNPCKHQDQZ128rr:
5303   case X86::VPUNPCKLQDQZ128rr:
5304   case X86::VPUNPCKHQDQZ256rr:
5305   case X86::VPUNPCKLQDQZ256rr:
5306   case X86::VPUNPCKHQDQZrr:
5307   case X86::VPUNPCKLQDQZrr:
5308     // These instructions are sometimes used with an undef first or second
5309     // source. Return true here so BreakFalseDeps will assign this source to the
5310     // same register as the first source to avoid a false dependency.
5311     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5312 
5313   case X86::VCVTSI2SSrr:
5314   case X86::VCVTSI2SSrm:
5315   case X86::VCVTSI2SSrr_Int:
5316   case X86::VCVTSI2SSrm_Int:
5317   case X86::VCVTSI642SSrr:
5318   case X86::VCVTSI642SSrm:
5319   case X86::VCVTSI642SSrr_Int:
5320   case X86::VCVTSI642SSrm_Int:
5321   case X86::VCVTSI2SDrr:
5322   case X86::VCVTSI2SDrm:
5323   case X86::VCVTSI2SDrr_Int:
5324   case X86::VCVTSI2SDrm_Int:
5325   case X86::VCVTSI642SDrr:
5326   case X86::VCVTSI642SDrm:
5327   case X86::VCVTSI642SDrr_Int:
5328   case X86::VCVTSI642SDrm_Int:
5329   // AVX-512
5330   case X86::VCVTSI2SSZrr:
5331   case X86::VCVTSI2SSZrm:
5332   case X86::VCVTSI2SSZrr_Int:
5333   case X86::VCVTSI2SSZrrb_Int:
5334   case X86::VCVTSI2SSZrm_Int:
5335   case X86::VCVTSI642SSZrr:
5336   case X86::VCVTSI642SSZrm:
5337   case X86::VCVTSI642SSZrr_Int:
5338   case X86::VCVTSI642SSZrrb_Int:
5339   case X86::VCVTSI642SSZrm_Int:
5340   case X86::VCVTSI2SDZrr:
5341   case X86::VCVTSI2SDZrm:
5342   case X86::VCVTSI2SDZrr_Int:
5343   case X86::VCVTSI2SDZrm_Int:
5344   case X86::VCVTSI642SDZrr:
5345   case X86::VCVTSI642SDZrm:
5346   case X86::VCVTSI642SDZrr_Int:
5347   case X86::VCVTSI642SDZrrb_Int:
5348   case X86::VCVTSI642SDZrm_Int:
5349   case X86::VCVTUSI2SSZrr:
5350   case X86::VCVTUSI2SSZrm:
5351   case X86::VCVTUSI2SSZrr_Int:
5352   case X86::VCVTUSI2SSZrrb_Int:
5353   case X86::VCVTUSI2SSZrm_Int:
5354   case X86::VCVTUSI642SSZrr:
5355   case X86::VCVTUSI642SSZrm:
5356   case X86::VCVTUSI642SSZrr_Int:
5357   case X86::VCVTUSI642SSZrrb_Int:
5358   case X86::VCVTUSI642SSZrm_Int:
5359   case X86::VCVTUSI2SDZrr:
5360   case X86::VCVTUSI2SDZrm:
5361   case X86::VCVTUSI2SDZrr_Int:
5362   case X86::VCVTUSI2SDZrm_Int:
5363   case X86::VCVTUSI642SDZrr:
5364   case X86::VCVTUSI642SDZrm:
5365   case X86::VCVTUSI642SDZrr_Int:
5366   case X86::VCVTUSI642SDZrrb_Int:
5367   case X86::VCVTUSI642SDZrm_Int:
5368   case X86::VCVTSI2SHZrr:
5369   case X86::VCVTSI2SHZrm:
5370   case X86::VCVTSI2SHZrr_Int:
5371   case X86::VCVTSI2SHZrrb_Int:
5372   case X86::VCVTSI2SHZrm_Int:
5373   case X86::VCVTSI642SHZrr:
5374   case X86::VCVTSI642SHZrm:
5375   case X86::VCVTSI642SHZrr_Int:
5376   case X86::VCVTSI642SHZrrb_Int:
5377   case X86::VCVTSI642SHZrm_Int:
5378   case X86::VCVTUSI2SHZrr:
5379   case X86::VCVTUSI2SHZrm:
5380   case X86::VCVTUSI2SHZrr_Int:
5381   case X86::VCVTUSI2SHZrrb_Int:
5382   case X86::VCVTUSI2SHZrm_Int:
5383   case X86::VCVTUSI642SHZrr:
5384   case X86::VCVTUSI642SHZrm:
5385   case X86::VCVTUSI642SHZrr_Int:
5386   case X86::VCVTUSI642SHZrrb_Int:
5387   case X86::VCVTUSI642SHZrm_Int:
5388     // Load folding won't effect the undef register update since the input is
5389     // a GPR.
5390     return OpNum == 1 && !ForLoadFold;
5391   case X86::VCVTSD2SSrr:
5392   case X86::VCVTSD2SSrm:
5393   case X86::VCVTSD2SSrr_Int:
5394   case X86::VCVTSD2SSrm_Int:
5395   case X86::VCVTSS2SDrr:
5396   case X86::VCVTSS2SDrm:
5397   case X86::VCVTSS2SDrr_Int:
5398   case X86::VCVTSS2SDrm_Int:
5399   case X86::VRCPSSr:
5400   case X86::VRCPSSr_Int:
5401   case X86::VRCPSSm:
5402   case X86::VRCPSSm_Int:
5403   case X86::VROUNDSDr:
5404   case X86::VROUNDSDm:
5405   case X86::VROUNDSDr_Int:
5406   case X86::VROUNDSDm_Int:
5407   case X86::VROUNDSSr:
5408   case X86::VROUNDSSm:
5409   case X86::VROUNDSSr_Int:
5410   case X86::VROUNDSSm_Int:
5411   case X86::VRSQRTSSr:
5412   case X86::VRSQRTSSr_Int:
5413   case X86::VRSQRTSSm:
5414   case X86::VRSQRTSSm_Int:
5415   case X86::VSQRTSSr:
5416   case X86::VSQRTSSr_Int:
5417   case X86::VSQRTSSm:
5418   case X86::VSQRTSSm_Int:
5419   case X86::VSQRTSDr:
5420   case X86::VSQRTSDr_Int:
5421   case X86::VSQRTSDm:
5422   case X86::VSQRTSDm_Int:
5423   // AVX-512
5424   case X86::VCVTSD2SSZrr:
5425   case X86::VCVTSD2SSZrr_Int:
5426   case X86::VCVTSD2SSZrrb_Int:
5427   case X86::VCVTSD2SSZrm:
5428   case X86::VCVTSD2SSZrm_Int:
5429   case X86::VCVTSS2SDZrr:
5430   case X86::VCVTSS2SDZrr_Int:
5431   case X86::VCVTSS2SDZrrb_Int:
5432   case X86::VCVTSS2SDZrm:
5433   case X86::VCVTSS2SDZrm_Int:
5434   case X86::VGETEXPSDZr:
5435   case X86::VGETEXPSDZrb:
5436   case X86::VGETEXPSDZm:
5437   case X86::VGETEXPSSZr:
5438   case X86::VGETEXPSSZrb:
5439   case X86::VGETEXPSSZm:
5440   case X86::VGETMANTSDZrri:
5441   case X86::VGETMANTSDZrrib:
5442   case X86::VGETMANTSDZrmi:
5443   case X86::VGETMANTSSZrri:
5444   case X86::VGETMANTSSZrrib:
5445   case X86::VGETMANTSSZrmi:
5446   case X86::VRNDSCALESDZr:
5447   case X86::VRNDSCALESDZr_Int:
5448   case X86::VRNDSCALESDZrb_Int:
5449   case X86::VRNDSCALESDZm:
5450   case X86::VRNDSCALESDZm_Int:
5451   case X86::VRNDSCALESSZr:
5452   case X86::VRNDSCALESSZr_Int:
5453   case X86::VRNDSCALESSZrb_Int:
5454   case X86::VRNDSCALESSZm:
5455   case X86::VRNDSCALESSZm_Int:
5456   case X86::VRCP14SDZrr:
5457   case X86::VRCP14SDZrm:
5458   case X86::VRCP14SSZrr:
5459   case X86::VRCP14SSZrm:
5460   case X86::VRCPSHZrr:
5461   case X86::VRCPSHZrm:
5462   case X86::VRSQRTSHZrr:
5463   case X86::VRSQRTSHZrm:
5464   case X86::VREDUCESHZrmi:
5465   case X86::VREDUCESHZrri:
5466   case X86::VREDUCESHZrrib:
5467   case X86::VGETEXPSHZr:
5468   case X86::VGETEXPSHZrb:
5469   case X86::VGETEXPSHZm:
5470   case X86::VGETMANTSHZrri:
5471   case X86::VGETMANTSHZrrib:
5472   case X86::VGETMANTSHZrmi:
5473   case X86::VRNDSCALESHZr:
5474   case X86::VRNDSCALESHZr_Int:
5475   case X86::VRNDSCALESHZrb_Int:
5476   case X86::VRNDSCALESHZm:
5477   case X86::VRNDSCALESHZm_Int:
5478   case X86::VSQRTSHZr:
5479   case X86::VSQRTSHZr_Int:
5480   case X86::VSQRTSHZrb_Int:
5481   case X86::VSQRTSHZm:
5482   case X86::VSQRTSHZm_Int:
5483   case X86::VRCP28SDZr:
5484   case X86::VRCP28SDZrb:
5485   case X86::VRCP28SDZm:
5486   case X86::VRCP28SSZr:
5487   case X86::VRCP28SSZrb:
5488   case X86::VRCP28SSZm:
5489   case X86::VREDUCESSZrmi:
5490   case X86::VREDUCESSZrri:
5491   case X86::VREDUCESSZrrib:
5492   case X86::VRSQRT14SDZrr:
5493   case X86::VRSQRT14SDZrm:
5494   case X86::VRSQRT14SSZrr:
5495   case X86::VRSQRT14SSZrm:
5496   case X86::VRSQRT28SDZr:
5497   case X86::VRSQRT28SDZrb:
5498   case X86::VRSQRT28SDZm:
5499   case X86::VRSQRT28SSZr:
5500   case X86::VRSQRT28SSZrb:
5501   case X86::VRSQRT28SSZm:
5502   case X86::VSQRTSSZr:
5503   case X86::VSQRTSSZr_Int:
5504   case X86::VSQRTSSZrb_Int:
5505   case X86::VSQRTSSZm:
5506   case X86::VSQRTSSZm_Int:
5507   case X86::VSQRTSDZr:
5508   case X86::VSQRTSDZr_Int:
5509   case X86::VSQRTSDZrb_Int:
5510   case X86::VSQRTSDZm:
5511   case X86::VSQRTSDZm_Int:
5512   case X86::VCVTSD2SHZrr:
5513   case X86::VCVTSD2SHZrr_Int:
5514   case X86::VCVTSD2SHZrrb_Int:
5515   case X86::VCVTSD2SHZrm:
5516   case X86::VCVTSD2SHZrm_Int:
5517   case X86::VCVTSS2SHZrr:
5518   case X86::VCVTSS2SHZrr_Int:
5519   case X86::VCVTSS2SHZrrb_Int:
5520   case X86::VCVTSS2SHZrm:
5521   case X86::VCVTSS2SHZrm_Int:
5522   case X86::VCVTSH2SDZrr:
5523   case X86::VCVTSH2SDZrr_Int:
5524   case X86::VCVTSH2SDZrrb_Int:
5525   case X86::VCVTSH2SDZrm:
5526   case X86::VCVTSH2SDZrm_Int:
5527   case X86::VCVTSH2SSZrr:
5528   case X86::VCVTSH2SSZrr_Int:
5529   case X86::VCVTSH2SSZrrb_Int:
5530   case X86::VCVTSH2SSZrm:
5531   case X86::VCVTSH2SSZrm_Int:
5532     return OpNum == 1;
5533   case X86::VMOVSSZrrk:
5534   case X86::VMOVSDZrrk:
5535     return OpNum == 3 && !ForLoadFold;
5536   case X86::VMOVSSZrrkz:
5537   case X86::VMOVSDZrrkz:
5538     return OpNum == 2 && !ForLoadFold;
5539   }
5540 
5541   return false;
5542 }
5543 
5544 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5545 /// before certain undef register reads.
5546 ///
5547 /// This catches the VCVTSI2SD family of instructions:
5548 ///
5549 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5550 ///
5551 /// We should to be careful *not* to catch VXOR idioms which are presumably
5552 /// handled specially in the pipeline:
5553 ///
5554 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5555 ///
5556 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5557 /// high bits that are passed-through are not live.
5558 unsigned
5559 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5560                                    const TargetRegisterInfo *TRI) const {
5561   const MachineOperand &MO = MI.getOperand(OpNum);
5562   if (Register::isPhysicalRegister(MO.getReg()) &&
5563       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5564     return UndefRegClearance;
5565 
5566   return 0;
5567 }
5568 
5569 void X86InstrInfo::breakPartialRegDependency(
5570     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5571   Register Reg = MI.getOperand(OpNum).getReg();
5572   // If MI kills this register, the false dependence is already broken.
5573   if (MI.killsRegister(Reg, TRI))
5574     return;
5575 
5576   if (X86::VR128RegClass.contains(Reg)) {
5577     // These instructions are all floating point domain, so xorps is the best
5578     // choice.
5579     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5580     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5581         .addReg(Reg, RegState::Undef)
5582         .addReg(Reg, RegState::Undef);
5583     MI.addRegisterKilled(Reg, TRI, true);
5584   } else if (X86::VR256RegClass.contains(Reg)) {
5585     // Use vxorps to clear the full ymm register.
5586     // It wants to read and write the xmm sub-register.
5587     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5588     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5589         .addReg(XReg, RegState::Undef)
5590         .addReg(XReg, RegState::Undef)
5591         .addReg(Reg, RegState::ImplicitDefine);
5592     MI.addRegisterKilled(Reg, TRI, true);
5593   } else if (X86::GR64RegClass.contains(Reg)) {
5594     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5595     // as well.
5596     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5597     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5598         .addReg(XReg, RegState::Undef)
5599         .addReg(XReg, RegState::Undef)
5600         .addReg(Reg, RegState::ImplicitDefine);
5601     MI.addRegisterKilled(Reg, TRI, true);
5602   } else if (X86::GR32RegClass.contains(Reg)) {
5603     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5604         .addReg(Reg, RegState::Undef)
5605         .addReg(Reg, RegState::Undef);
5606     MI.addRegisterKilled(Reg, TRI, true);
5607   }
5608 }
5609 
5610 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5611                         int PtrOffset = 0) {
5612   unsigned NumAddrOps = MOs.size();
5613 
5614   if (NumAddrOps < 4) {
5615     // FrameIndex only - add an immediate offset (whether its zero or not).
5616     for (unsigned i = 0; i != NumAddrOps; ++i)
5617       MIB.add(MOs[i]);
5618     addOffset(MIB, PtrOffset);
5619   } else {
5620     // General Memory Addressing - we need to add any offset to an existing
5621     // offset.
5622     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5623     for (unsigned i = 0; i != NumAddrOps; ++i) {
5624       const MachineOperand &MO = MOs[i];
5625       if (i == 3 && PtrOffset != 0) {
5626         MIB.addDisp(MO, PtrOffset);
5627       } else {
5628         MIB.add(MO);
5629       }
5630     }
5631   }
5632 }
5633 
5634 static void updateOperandRegConstraints(MachineFunction &MF,
5635                                         MachineInstr &NewMI,
5636                                         const TargetInstrInfo &TII) {
5637   MachineRegisterInfo &MRI = MF.getRegInfo();
5638   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5639 
5640   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5641     MachineOperand &MO = NewMI.getOperand(Idx);
5642     // We only need to update constraints on virtual register operands.
5643     if (!MO.isReg())
5644       continue;
5645     Register Reg = MO.getReg();
5646     if (!Reg.isVirtual())
5647       continue;
5648 
5649     auto *NewRC = MRI.constrainRegClass(
5650         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5651     if (!NewRC) {
5652       LLVM_DEBUG(
5653           dbgs() << "WARNING: Unable to update register constraint for operand "
5654                  << Idx << " of instruction:\n";
5655           NewMI.dump(); dbgs() << "\n");
5656     }
5657   }
5658 }
5659 
5660 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5661                                      ArrayRef<MachineOperand> MOs,
5662                                      MachineBasicBlock::iterator InsertPt,
5663                                      MachineInstr &MI,
5664                                      const TargetInstrInfo &TII) {
5665   // Create the base instruction with the memory operand as the first part.
5666   // Omit the implicit operands, something BuildMI can't do.
5667   MachineInstr *NewMI =
5668       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5669   MachineInstrBuilder MIB(MF, NewMI);
5670   addOperands(MIB, MOs);
5671 
5672   // Loop over the rest of the ri operands, converting them over.
5673   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5674   for (unsigned i = 0; i != NumOps; ++i) {
5675     MachineOperand &MO = MI.getOperand(i + 2);
5676     MIB.add(MO);
5677   }
5678   for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), NumOps + 2))
5679     MIB.add(MO);
5680 
5681   updateOperandRegConstraints(MF, *NewMI, TII);
5682 
5683   MachineBasicBlock *MBB = InsertPt->getParent();
5684   MBB->insert(InsertPt, NewMI);
5685 
5686   return MIB;
5687 }
5688 
5689 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5690                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5691                               MachineBasicBlock::iterator InsertPt,
5692                               MachineInstr &MI, const TargetInstrInfo &TII,
5693                               int PtrOffset = 0) {
5694   // Omit the implicit operands, something BuildMI can't do.
5695   MachineInstr *NewMI =
5696       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5697   MachineInstrBuilder MIB(MF, NewMI);
5698 
5699   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5700     MachineOperand &MO = MI.getOperand(i);
5701     if (i == OpNo) {
5702       assert(MO.isReg() && "Expected to fold into reg operand!");
5703       addOperands(MIB, MOs, PtrOffset);
5704     } else {
5705       MIB.add(MO);
5706     }
5707   }
5708 
5709   updateOperandRegConstraints(MF, *NewMI, TII);
5710 
5711   // Copy the NoFPExcept flag from the instruction we're fusing.
5712   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5713     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5714 
5715   MachineBasicBlock *MBB = InsertPt->getParent();
5716   MBB->insert(InsertPt, NewMI);
5717 
5718   return MIB;
5719 }
5720 
5721 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5722                                 ArrayRef<MachineOperand> MOs,
5723                                 MachineBasicBlock::iterator InsertPt,
5724                                 MachineInstr &MI) {
5725   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5726                                     MI.getDebugLoc(), TII.get(Opcode));
5727   addOperands(MIB, MOs);
5728   return MIB.addImm(0);
5729 }
5730 
5731 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5732     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5733     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5734     unsigned Size, Align Alignment) const {
5735   switch (MI.getOpcode()) {
5736   case X86::INSERTPSrr:
5737   case X86::VINSERTPSrr:
5738   case X86::VINSERTPSZrr:
5739     // Attempt to convert the load of inserted vector into a fold load
5740     // of a single float.
5741     if (OpNum == 2) {
5742       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5743       unsigned ZMask = Imm & 15;
5744       unsigned DstIdx = (Imm >> 4) & 3;
5745       unsigned SrcIdx = (Imm >> 6) & 3;
5746 
5747       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5748       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5749       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5750       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5751         int PtrOffset = SrcIdx * 4;
5752         unsigned NewImm = (DstIdx << 4) | ZMask;
5753         unsigned NewOpCode =
5754             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5755             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5756                                                     X86::INSERTPSrm;
5757         MachineInstr *NewMI =
5758             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5759         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5760         return NewMI;
5761       }
5762     }
5763     break;
5764   case X86::MOVHLPSrr:
5765   case X86::VMOVHLPSrr:
5766   case X86::VMOVHLPSZrr:
5767     // Move the upper 64-bits of the second operand to the lower 64-bits.
5768     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5769     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5770     if (OpNum == 2) {
5771       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5772       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5773       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5774       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5775         unsigned NewOpCode =
5776             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5777             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5778                                                    X86::MOVLPSrm;
5779         MachineInstr *NewMI =
5780             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5781         return NewMI;
5782       }
5783     }
5784     break;
5785   case X86::UNPCKLPDrr:
5786     // If we won't be able to fold this to the memory form of UNPCKL, use
5787     // MOVHPD instead. Done as custom because we can't have this in the load
5788     // table twice.
5789     if (OpNum == 2) {
5790       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5791       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5792       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5793       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5794         MachineInstr *NewMI =
5795             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5796         return NewMI;
5797       }
5798     }
5799     break;
5800   }
5801 
5802   return nullptr;
5803 }
5804 
5805 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5806                                                MachineInstr &MI) {
5807   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5808       !MI.getOperand(1).isReg())
5809     return false;
5810 
5811   // The are two cases we need to handle depending on where in the pipeline
5812   // the folding attempt is being made.
5813   // -Register has the undef flag set.
5814   // -Register is produced by the IMPLICIT_DEF instruction.
5815 
5816   if (MI.getOperand(1).isUndef())
5817     return true;
5818 
5819   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5820   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5821   return VRegDef && VRegDef->isImplicitDef();
5822 }
5823 
5824 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5825     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5826     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5827     unsigned Size, Align Alignment, bool AllowCommute) const {
5828   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5829   bool isTwoAddrFold = false;
5830 
5831   // For CPUs that favor the register form of a call or push,
5832   // do not fold loads into calls or pushes, unless optimizing for size
5833   // aggressively.
5834   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5835       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5836        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5837        MI.getOpcode() == X86::PUSH64r))
5838     return nullptr;
5839 
5840   // Avoid partial and undef register update stalls unless optimizing for size.
5841   if (!MF.getFunction().hasOptSize() &&
5842       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5843        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5844     return nullptr;
5845 
5846   unsigned NumOps = MI.getDesc().getNumOperands();
5847   bool isTwoAddr =
5848       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5849 
5850   // FIXME: AsmPrinter doesn't know how to handle
5851   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5852   if (MI.getOpcode() == X86::ADD32ri &&
5853       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5854     return nullptr;
5855 
5856   // GOTTPOFF relocation loads can only be folded into add instructions.
5857   // FIXME: Need to exclude other relocations that only support specific
5858   // instructions.
5859   if (MOs.size() == X86::AddrNumOperands &&
5860       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5861       MI.getOpcode() != X86::ADD64rr)
5862     return nullptr;
5863 
5864   MachineInstr *NewMI = nullptr;
5865 
5866   // Attempt to fold any custom cases we have.
5867   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5868           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5869     return CustomMI;
5870 
5871   const X86MemoryFoldTableEntry *I = nullptr;
5872 
5873   // Folding a memory location into the two-address part of a two-address
5874   // instruction is different than folding it other places.  It requires
5875   // replacing the *two* registers with the memory location.
5876   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5877       MI.getOperand(1).isReg() &&
5878       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5879     I = lookupTwoAddrFoldTable(MI.getOpcode());
5880     isTwoAddrFold = true;
5881   } else {
5882     if (OpNum == 0) {
5883       if (MI.getOpcode() == X86::MOV32r0) {
5884         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5885         if (NewMI)
5886           return NewMI;
5887       }
5888     }
5889 
5890     I = lookupFoldTable(MI.getOpcode(), OpNum);
5891   }
5892 
5893   if (I != nullptr) {
5894     unsigned Opcode = I->DstOp;
5895     bool FoldedLoad =
5896         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5897     bool FoldedStore =
5898         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5899     MaybeAlign MinAlign =
5900         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5901     if (MinAlign && Alignment < *MinAlign)
5902       return nullptr;
5903     bool NarrowToMOV32rm = false;
5904     if (Size) {
5905       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5906       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5907                                                   &RI, MF);
5908       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5909       // Check if it's safe to fold the load. If the size of the object is
5910       // narrower than the load width, then it's not.
5911       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5912       if (FoldedLoad && Size < RCSize) {
5913         // If this is a 64-bit load, but the spill slot is 32, then we can do
5914         // a 32-bit load which is implicitly zero-extended. This likely is
5915         // due to live interval analysis remat'ing a load from stack slot.
5916         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5917           return nullptr;
5918         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5919           return nullptr;
5920         Opcode = X86::MOV32rm;
5921         NarrowToMOV32rm = true;
5922       }
5923       // For stores, make sure the size of the object is equal to the size of
5924       // the store. If the object is larger, the extra bits would be garbage. If
5925       // the object is smaller we might overwrite another object or fault.
5926       if (FoldedStore && Size != RCSize)
5927         return nullptr;
5928     }
5929 
5930     if (isTwoAddrFold)
5931       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5932     else
5933       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5934 
5935     if (NarrowToMOV32rm) {
5936       // If this is the special case where we use a MOV32rm to load a 32-bit
5937       // value and zero-extend the top bits. Change the destination register
5938       // to a 32-bit one.
5939       Register DstReg = NewMI->getOperand(0).getReg();
5940       if (DstReg.isPhysical())
5941         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5942       else
5943         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5944     }
5945     return NewMI;
5946   }
5947 
5948   // If the instruction and target operand are commutable, commute the
5949   // instruction and try again.
5950   if (AllowCommute) {
5951     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5952     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5953       bool HasDef = MI.getDesc().getNumDefs();
5954       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5955       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5956       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5957       bool Tied1 =
5958           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5959       bool Tied2 =
5960           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5961 
5962       // If either of the commutable operands are tied to the destination
5963       // then we can not commute + fold.
5964       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5965           (HasDef && Reg0 == Reg2 && Tied2))
5966         return nullptr;
5967 
5968       MachineInstr *CommutedMI =
5969           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5970       if (!CommutedMI) {
5971         // Unable to commute.
5972         return nullptr;
5973       }
5974       if (CommutedMI != &MI) {
5975         // New instruction. We can't fold from this.
5976         CommutedMI->eraseFromParent();
5977         return nullptr;
5978       }
5979 
5980       // Attempt to fold with the commuted version of the instruction.
5981       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5982                                     Alignment, /*AllowCommute=*/false);
5983       if (NewMI)
5984         return NewMI;
5985 
5986       // Folding failed again - undo the commute before returning.
5987       MachineInstr *UncommutedMI =
5988           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5989       if (!UncommutedMI) {
5990         // Unable to commute.
5991         return nullptr;
5992       }
5993       if (UncommutedMI != &MI) {
5994         // New instruction. It doesn't need to be kept.
5995         UncommutedMI->eraseFromParent();
5996         return nullptr;
5997       }
5998 
5999       // Return here to prevent duplicate fuse failure report.
6000       return nullptr;
6001     }
6002   }
6003 
6004   // No fusion
6005   if (PrintFailedFusing && !MI.isCopy())
6006     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
6007   return nullptr;
6008 }
6009 
6010 MachineInstr *
6011 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6012                                     ArrayRef<unsigned> Ops,
6013                                     MachineBasicBlock::iterator InsertPt,
6014                                     int FrameIndex, LiveIntervals *LIS,
6015                                     VirtRegMap *VRM) const {
6016   // Check switch flag
6017   if (NoFusing)
6018     return nullptr;
6019 
6020   // Avoid partial and undef register update stalls unless optimizing for size.
6021   if (!MF.getFunction().hasOptSize() &&
6022       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
6023        shouldPreventUndefRegUpdateMemFold(MF, MI)))
6024     return nullptr;
6025 
6026   // Don't fold subreg spills, or reloads that use a high subreg.
6027   for (auto Op : Ops) {
6028     MachineOperand &MO = MI.getOperand(Op);
6029     auto SubReg = MO.getSubReg();
6030     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
6031       return nullptr;
6032   }
6033 
6034   const MachineFrameInfo &MFI = MF.getFrameInfo();
6035   unsigned Size = MFI.getObjectSize(FrameIndex);
6036   Align Alignment = MFI.getObjectAlign(FrameIndex);
6037   // If the function stack isn't realigned we don't want to fold instructions
6038   // that need increased alignment.
6039   if (!RI.hasStackRealignment(MF))
6040     Alignment =
6041         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
6042   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6043     unsigned NewOpc = 0;
6044     unsigned RCSize = 0;
6045     switch (MI.getOpcode()) {
6046     default: return nullptr;
6047     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6048     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6049     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6050     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6051     }
6052     // Check if it's safe to fold the load. If the size of the object is
6053     // narrower than the load width, then it's not.
6054     if (Size < RCSize)
6055       return nullptr;
6056     // Change to CMPXXri r, 0 first.
6057     MI.setDesc(get(NewOpc));
6058     MI.getOperand(1).ChangeToImmediate(0);
6059   } else if (Ops.size() != 1)
6060     return nullptr;
6061 
6062   return foldMemoryOperandImpl(MF, MI, Ops[0],
6063                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6064                                Size, Alignment, /*AllowCommute=*/true);
6065 }
6066 
6067 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6068 /// because the latter uses contents that wouldn't be defined in the folded
6069 /// version.  For instance, this transformation isn't legal:
6070 ///   movss (%rdi), %xmm0
6071 ///   addps %xmm0, %xmm0
6072 /// ->
6073 ///   addps (%rdi), %xmm0
6074 ///
6075 /// But this one is:
6076 ///   movss (%rdi), %xmm0
6077 ///   addss %xmm0, %xmm0
6078 /// ->
6079 ///   addss (%rdi), %xmm0
6080 ///
6081 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6082                                              const MachineInstr &UserMI,
6083                                              const MachineFunction &MF) {
6084   unsigned Opc = LoadMI.getOpcode();
6085   unsigned UserOpc = UserMI.getOpcode();
6086   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6087   const TargetRegisterClass *RC =
6088       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
6089   unsigned RegSize = TRI.getRegSizeInBits(*RC);
6090 
6091   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
6092        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
6093        Opc == X86::VMOVSSZrm_alt) &&
6094       RegSize > 32) {
6095     // These instructions only load 32 bits, we can't fold them if the
6096     // destination register is wider than 32 bits (4 bytes), and its user
6097     // instruction isn't scalar (SS).
6098     switch (UserOpc) {
6099     case X86::CVTSS2SDrr_Int:
6100     case X86::VCVTSS2SDrr_Int:
6101     case X86::VCVTSS2SDZrr_Int:
6102     case X86::VCVTSS2SDZrr_Intk:
6103     case X86::VCVTSS2SDZrr_Intkz:
6104     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
6105     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
6106     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
6107     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
6108     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
6109     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
6110     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
6111     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
6112     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
6113     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
6114     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
6115     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
6116     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
6117     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
6118     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
6119     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
6120     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
6121     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
6122     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6123     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
6124     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
6125     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
6126     case X86::VCMPSSZrr_Intk:
6127     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
6128     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
6129     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
6130     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
6131     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
6132     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
6133     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
6134     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
6135     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
6136     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
6137     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
6138     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
6139     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
6140     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
6141     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
6142     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
6143     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
6144     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
6145     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
6146     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
6147     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
6148     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
6149     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
6150     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
6151     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
6152     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
6153     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
6154     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
6155     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
6156     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
6157     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
6158     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
6159     case X86::VFIXUPIMMSSZrri:
6160     case X86::VFIXUPIMMSSZrrik:
6161     case X86::VFIXUPIMMSSZrrikz:
6162     case X86::VFPCLASSSSZrr:
6163     case X86::VFPCLASSSSZrrk:
6164     case X86::VGETEXPSSZr:
6165     case X86::VGETEXPSSZrk:
6166     case X86::VGETEXPSSZrkz:
6167     case X86::VGETMANTSSZrri:
6168     case X86::VGETMANTSSZrrik:
6169     case X86::VGETMANTSSZrrikz:
6170     case X86::VRANGESSZrri:
6171     case X86::VRANGESSZrrik:
6172     case X86::VRANGESSZrrikz:
6173     case X86::VRCP14SSZrr:
6174     case X86::VRCP14SSZrrk:
6175     case X86::VRCP14SSZrrkz:
6176     case X86::VRCP28SSZr:
6177     case X86::VRCP28SSZrk:
6178     case X86::VRCP28SSZrkz:
6179     case X86::VREDUCESSZrri:
6180     case X86::VREDUCESSZrrik:
6181     case X86::VREDUCESSZrrikz:
6182     case X86::VRNDSCALESSZr_Int:
6183     case X86::VRNDSCALESSZr_Intk:
6184     case X86::VRNDSCALESSZr_Intkz:
6185     case X86::VRSQRT14SSZrr:
6186     case X86::VRSQRT14SSZrrk:
6187     case X86::VRSQRT14SSZrrkz:
6188     case X86::VRSQRT28SSZr:
6189     case X86::VRSQRT28SSZrk:
6190     case X86::VRSQRT28SSZrkz:
6191     case X86::VSCALEFSSZrr:
6192     case X86::VSCALEFSSZrrk:
6193     case X86::VSCALEFSSZrrkz:
6194       return false;
6195     default:
6196       return true;
6197     }
6198   }
6199 
6200   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
6201        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
6202        Opc == X86::VMOVSDZrm_alt) &&
6203       RegSize > 64) {
6204     // These instructions only load 64 bits, we can't fold them if the
6205     // destination register is wider than 64 bits (8 bytes), and its user
6206     // instruction isn't scalar (SD).
6207     switch (UserOpc) {
6208     case X86::CVTSD2SSrr_Int:
6209     case X86::VCVTSD2SSrr_Int:
6210     case X86::VCVTSD2SSZrr_Int:
6211     case X86::VCVTSD2SSZrr_Intk:
6212     case X86::VCVTSD2SSZrr_Intkz:
6213     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
6214     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
6215     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
6216     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
6217     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
6218     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
6219     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
6220     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
6221     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
6222     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
6223     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
6224     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6225     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
6226     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6227     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6228     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
6229     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6230     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
6231     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6232     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
6233     case X86::VCMPSDZrr_Intk:
6234     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
6235     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
6236     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
6237     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
6238     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
6239     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
6240     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
6241     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
6242     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
6243     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
6244     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
6245     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
6246     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
6247     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
6248     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6249     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6250     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6251     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6252     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6253     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
6254     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
6255     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
6256     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
6257     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
6258     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
6259     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
6260     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
6261     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
6262     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
6263     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
6264     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
6265     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
6266     case X86::VFIXUPIMMSDZrri:
6267     case X86::VFIXUPIMMSDZrrik:
6268     case X86::VFIXUPIMMSDZrrikz:
6269     case X86::VFPCLASSSDZrr:
6270     case X86::VFPCLASSSDZrrk:
6271     case X86::VGETEXPSDZr:
6272     case X86::VGETEXPSDZrk:
6273     case X86::VGETEXPSDZrkz:
6274     case X86::VGETMANTSDZrri:
6275     case X86::VGETMANTSDZrrik:
6276     case X86::VGETMANTSDZrrikz:
6277     case X86::VRANGESDZrri:
6278     case X86::VRANGESDZrrik:
6279     case X86::VRANGESDZrrikz:
6280     case X86::VRCP14SDZrr:
6281     case X86::VRCP14SDZrrk:
6282     case X86::VRCP14SDZrrkz:
6283     case X86::VRCP28SDZr:
6284     case X86::VRCP28SDZrk:
6285     case X86::VRCP28SDZrkz:
6286     case X86::VREDUCESDZrri:
6287     case X86::VREDUCESDZrrik:
6288     case X86::VREDUCESDZrrikz:
6289     case X86::VRNDSCALESDZr_Int:
6290     case X86::VRNDSCALESDZr_Intk:
6291     case X86::VRNDSCALESDZr_Intkz:
6292     case X86::VRSQRT14SDZrr:
6293     case X86::VRSQRT14SDZrrk:
6294     case X86::VRSQRT14SDZrrkz:
6295     case X86::VRSQRT28SDZr:
6296     case X86::VRSQRT28SDZrk:
6297     case X86::VRSQRT28SDZrkz:
6298     case X86::VSCALEFSDZrr:
6299     case X86::VSCALEFSDZrrk:
6300     case X86::VSCALEFSDZrrkz:
6301       return false;
6302     default:
6303       return true;
6304     }
6305   }
6306 
6307   if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
6308     // These instructions only load 16 bits, we can't fold them if the
6309     // destination register is wider than 16 bits (2 bytes), and its user
6310     // instruction isn't scalar (SH).
6311     switch (UserOpc) {
6312     case X86::VADDSHZrr_Int:
6313     case X86::VCMPSHZrr_Int:
6314     case X86::VDIVSHZrr_Int:
6315     case X86::VMAXSHZrr_Int:
6316     case X86::VMINSHZrr_Int:
6317     case X86::VMULSHZrr_Int:
6318     case X86::VSUBSHZrr_Int:
6319     case X86::VADDSHZrr_Intk: case X86::VADDSHZrr_Intkz:
6320     case X86::VCMPSHZrr_Intk:
6321     case X86::VDIVSHZrr_Intk: case X86::VDIVSHZrr_Intkz:
6322     case X86::VMAXSHZrr_Intk: case X86::VMAXSHZrr_Intkz:
6323     case X86::VMINSHZrr_Intk: case X86::VMINSHZrr_Intkz:
6324     case X86::VMULSHZrr_Intk: case X86::VMULSHZrr_Intkz:
6325     case X86::VSUBSHZrr_Intk: case X86::VSUBSHZrr_Intkz:
6326     case X86::VFMADD132SHZr_Int: case X86::VFNMADD132SHZr_Int:
6327     case X86::VFMADD213SHZr_Int: case X86::VFNMADD213SHZr_Int:
6328     case X86::VFMADD231SHZr_Int: case X86::VFNMADD231SHZr_Int:
6329     case X86::VFMSUB132SHZr_Int: case X86::VFNMSUB132SHZr_Int:
6330     case X86::VFMSUB213SHZr_Int: case X86::VFNMSUB213SHZr_Int:
6331     case X86::VFMSUB231SHZr_Int: case X86::VFNMSUB231SHZr_Int:
6332     case X86::VFMADD132SHZr_Intk: case X86::VFNMADD132SHZr_Intk:
6333     case X86::VFMADD213SHZr_Intk: case X86::VFNMADD213SHZr_Intk:
6334     case X86::VFMADD231SHZr_Intk: case X86::VFNMADD231SHZr_Intk:
6335     case X86::VFMSUB132SHZr_Intk: case X86::VFNMSUB132SHZr_Intk:
6336     case X86::VFMSUB213SHZr_Intk: case X86::VFNMSUB213SHZr_Intk:
6337     case X86::VFMSUB231SHZr_Intk: case X86::VFNMSUB231SHZr_Intk:
6338     case X86::VFMADD132SHZr_Intkz: case X86::VFNMADD132SHZr_Intkz:
6339     case X86::VFMADD213SHZr_Intkz: case X86::VFNMADD213SHZr_Intkz:
6340     case X86::VFMADD231SHZr_Intkz: case X86::VFNMADD231SHZr_Intkz:
6341     case X86::VFMSUB132SHZr_Intkz: case X86::VFNMSUB132SHZr_Intkz:
6342     case X86::VFMSUB213SHZr_Intkz: case X86::VFNMSUB213SHZr_Intkz:
6343     case X86::VFMSUB231SHZr_Intkz: case X86::VFNMSUB231SHZr_Intkz:
6344       return false;
6345     default:
6346       return true;
6347     }
6348   }
6349 
6350   return false;
6351 }
6352 
6353 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6354     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6355     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6356     LiveIntervals *LIS) const {
6357 
6358   // TODO: Support the case where LoadMI loads a wide register, but MI
6359   // only uses a subreg.
6360   for (auto Op : Ops) {
6361     if (MI.getOperand(Op).getSubReg())
6362       return nullptr;
6363   }
6364 
6365   // If loading from a FrameIndex, fold directly from the FrameIndex.
6366   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6367   int FrameIndex;
6368   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6369     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6370       return nullptr;
6371     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6372   }
6373 
6374   // Check switch flag
6375   if (NoFusing) return nullptr;
6376 
6377   // Avoid partial and undef register update stalls unless optimizing for size.
6378   if (!MF.getFunction().hasOptSize() &&
6379       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
6380        shouldPreventUndefRegUpdateMemFold(MF, MI)))
6381     return nullptr;
6382 
6383   // Determine the alignment of the load.
6384   Align Alignment;
6385   if (LoadMI.hasOneMemOperand())
6386     Alignment = (*LoadMI.memoperands_begin())->getAlign();
6387   else
6388     switch (LoadMI.getOpcode()) {
6389     case X86::AVX512_512_SET0:
6390     case X86::AVX512_512_SETALLONES:
6391       Alignment = Align(64);
6392       break;
6393     case X86::AVX2_SETALLONES:
6394     case X86::AVX1_SETALLONES:
6395     case X86::AVX_SET0:
6396     case X86::AVX512_256_SET0:
6397       Alignment = Align(32);
6398       break;
6399     case X86::V_SET0:
6400     case X86::V_SETALLONES:
6401     case X86::AVX512_128_SET0:
6402     case X86::FsFLD0F128:
6403     case X86::AVX512_FsFLD0F128:
6404       Alignment = Align(16);
6405       break;
6406     case X86::MMX_SET0:
6407     case X86::FsFLD0SD:
6408     case X86::AVX512_FsFLD0SD:
6409       Alignment = Align(8);
6410       break;
6411     case X86::FsFLD0SS:
6412     case X86::AVX512_FsFLD0SS:
6413       Alignment = Align(4);
6414       break;
6415     case X86::AVX512_FsFLD0SH:
6416       Alignment = Align(2);
6417       break;
6418     default:
6419       return nullptr;
6420     }
6421   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6422     unsigned NewOpc = 0;
6423     switch (MI.getOpcode()) {
6424     default: return nullptr;
6425     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6426     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6427     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6428     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6429     }
6430     // Change to CMPXXri r, 0 first.
6431     MI.setDesc(get(NewOpc));
6432     MI.getOperand(1).ChangeToImmediate(0);
6433   } else if (Ops.size() != 1)
6434     return nullptr;
6435 
6436   // Make sure the subregisters match.
6437   // Otherwise we risk changing the size of the load.
6438   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6439     return nullptr;
6440 
6441   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6442   switch (LoadMI.getOpcode()) {
6443   case X86::MMX_SET0:
6444   case X86::V_SET0:
6445   case X86::V_SETALLONES:
6446   case X86::AVX2_SETALLONES:
6447   case X86::AVX1_SETALLONES:
6448   case X86::AVX_SET0:
6449   case X86::AVX512_128_SET0:
6450   case X86::AVX512_256_SET0:
6451   case X86::AVX512_512_SET0:
6452   case X86::AVX512_512_SETALLONES:
6453   case X86::AVX512_FsFLD0SH:
6454   case X86::FsFLD0SD:
6455   case X86::AVX512_FsFLD0SD:
6456   case X86::FsFLD0SS:
6457   case X86::AVX512_FsFLD0SS:
6458   case X86::FsFLD0F128:
6459   case X86::AVX512_FsFLD0F128: {
6460     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6461     // Create a constant-pool entry and operands to load from it.
6462 
6463     // Medium and large mode can't fold loads this way.
6464     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6465         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6466       return nullptr;
6467 
6468     // x86-32 PIC requires a PIC base register for constant pools.
6469     unsigned PICBase = 0;
6470     // Since we're using Small or Kernel code model, we can always use
6471     // RIP-relative addressing for a smaller encoding.
6472     if (Subtarget.is64Bit()) {
6473       PICBase = X86::RIP;
6474     } else if (MF.getTarget().isPositionIndependent()) {
6475       // FIXME: PICBase = getGlobalBaseReg(&MF);
6476       // This doesn't work for several reasons.
6477       // 1. GlobalBaseReg may have been spilled.
6478       // 2. It may not be live at MI.
6479       return nullptr;
6480     }
6481 
6482     // Create a constant-pool entry.
6483     MachineConstantPool &MCP = *MF.getConstantPool();
6484     Type *Ty;
6485     unsigned Opc = LoadMI.getOpcode();
6486     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6487       Ty = Type::getFloatTy(MF.getFunction().getContext());
6488     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6489       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6490     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6491       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6492     else if (Opc == X86::AVX512_FsFLD0SH)
6493       Ty = Type::getHalfTy(MF.getFunction().getContext());
6494     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6495       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6496                                 16);
6497     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6498              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6499       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6500                                 8);
6501     else if (Opc == X86::MMX_SET0)
6502       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6503                                 2);
6504     else
6505       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6506                                 4);
6507 
6508     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6509                       Opc == X86::AVX512_512_SETALLONES ||
6510                       Opc == X86::AVX1_SETALLONES);
6511     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6512                                     Constant::getNullValue(Ty);
6513     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6514 
6515     // Create operands to load from the constant pool entry.
6516     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6517     MOs.push_back(MachineOperand::CreateImm(1));
6518     MOs.push_back(MachineOperand::CreateReg(0, false));
6519     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6520     MOs.push_back(MachineOperand::CreateReg(0, false));
6521     break;
6522   }
6523   default: {
6524     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6525       return nullptr;
6526 
6527     // Folding a normal load. Just copy the load's address operands.
6528     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6529                LoadMI.operands_begin() + NumOps);
6530     break;
6531   }
6532   }
6533   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6534                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6535 }
6536 
6537 static SmallVector<MachineMemOperand *, 2>
6538 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6539   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6540 
6541   for (MachineMemOperand *MMO : MMOs) {
6542     if (!MMO->isLoad())
6543       continue;
6544 
6545     if (!MMO->isStore()) {
6546       // Reuse the MMO.
6547       LoadMMOs.push_back(MMO);
6548     } else {
6549       // Clone the MMO and unset the store flag.
6550       LoadMMOs.push_back(MF.getMachineMemOperand(
6551           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6552     }
6553   }
6554 
6555   return LoadMMOs;
6556 }
6557 
6558 static SmallVector<MachineMemOperand *, 2>
6559 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6560   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6561 
6562   for (MachineMemOperand *MMO : MMOs) {
6563     if (!MMO->isStore())
6564       continue;
6565 
6566     if (!MMO->isLoad()) {
6567       // Reuse the MMO.
6568       StoreMMOs.push_back(MMO);
6569     } else {
6570       // Clone the MMO and unset the load flag.
6571       StoreMMOs.push_back(MF.getMachineMemOperand(
6572           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6573     }
6574   }
6575 
6576   return StoreMMOs;
6577 }
6578 
6579 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6580                                    const TargetRegisterClass *RC,
6581                                    const X86Subtarget &STI) {
6582   assert(STI.hasAVX512() && "Expected at least AVX512!");
6583   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6584   assert((SpillSize == 64 || STI.hasVLX()) &&
6585          "Can't broadcast less than 64 bytes without AVX512VL!");
6586 
6587   switch (I->Flags & TB_BCAST_MASK) {
6588   default: llvm_unreachable("Unexpected broadcast type!");
6589   case TB_BCAST_D:
6590     switch (SpillSize) {
6591     default: llvm_unreachable("Unknown spill size");
6592     case 16: return X86::VPBROADCASTDZ128rm;
6593     case 32: return X86::VPBROADCASTDZ256rm;
6594     case 64: return X86::VPBROADCASTDZrm;
6595     }
6596     break;
6597   case TB_BCAST_Q:
6598     switch (SpillSize) {
6599     default: llvm_unreachable("Unknown spill size");
6600     case 16: return X86::VPBROADCASTQZ128rm;
6601     case 32: return X86::VPBROADCASTQZ256rm;
6602     case 64: return X86::VPBROADCASTQZrm;
6603     }
6604     break;
6605   case TB_BCAST_SS:
6606     switch (SpillSize) {
6607     default: llvm_unreachable("Unknown spill size");
6608     case 16: return X86::VBROADCASTSSZ128rm;
6609     case 32: return X86::VBROADCASTSSZ256rm;
6610     case 64: return X86::VBROADCASTSSZrm;
6611     }
6612     break;
6613   case TB_BCAST_SD:
6614     switch (SpillSize) {
6615     default: llvm_unreachable("Unknown spill size");
6616     case 16: return X86::VMOVDDUPZ128rm;
6617     case 32: return X86::VBROADCASTSDZ256rm;
6618     case 64: return X86::VBROADCASTSDZrm;
6619     }
6620     break;
6621   }
6622 }
6623 
6624 bool X86InstrInfo::unfoldMemoryOperand(
6625     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6626     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6627   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6628   if (I == nullptr)
6629     return false;
6630   unsigned Opc = I->DstOp;
6631   unsigned Index = I->Flags & TB_INDEX_MASK;
6632   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6633   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6634   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6635   if (UnfoldLoad && !FoldedLoad)
6636     return false;
6637   UnfoldLoad &= FoldedLoad;
6638   if (UnfoldStore && !FoldedStore)
6639     return false;
6640   UnfoldStore &= FoldedStore;
6641 
6642   const MCInstrDesc &MCID = get(Opc);
6643 
6644   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6645   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6646   // TODO: Check if 32-byte or greater accesses are slow too?
6647   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6648       Subtarget.isUnalignedMem16Slow())
6649     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6650     // conservatively assume the address is unaligned. That's bad for
6651     // performance.
6652     return false;
6653   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6654   SmallVector<MachineOperand,2> BeforeOps;
6655   SmallVector<MachineOperand,2> AfterOps;
6656   SmallVector<MachineOperand,4> ImpOps;
6657   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6658     MachineOperand &Op = MI.getOperand(i);
6659     if (i >= Index && i < Index + X86::AddrNumOperands)
6660       AddrOps.push_back(Op);
6661     else if (Op.isReg() && Op.isImplicit())
6662       ImpOps.push_back(Op);
6663     else if (i < Index)
6664       BeforeOps.push_back(Op);
6665     else if (i > Index)
6666       AfterOps.push_back(Op);
6667   }
6668 
6669   // Emit the load or broadcast instruction.
6670   if (UnfoldLoad) {
6671     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6672 
6673     unsigned Opc;
6674     if (FoldedBCast) {
6675       Opc = getBroadcastOpcode(I, RC, Subtarget);
6676     } else {
6677       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6678       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6679       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6680     }
6681 
6682     DebugLoc DL;
6683     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6684     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6685       MIB.add(AddrOps[i]);
6686     MIB.setMemRefs(MMOs);
6687     NewMIs.push_back(MIB);
6688 
6689     if (UnfoldStore) {
6690       // Address operands cannot be marked isKill.
6691       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6692         MachineOperand &MO = NewMIs[0]->getOperand(i);
6693         if (MO.isReg())
6694           MO.setIsKill(false);
6695       }
6696     }
6697   }
6698 
6699   // Emit the data processing instruction.
6700   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6701   MachineInstrBuilder MIB(MF, DataMI);
6702 
6703   if (FoldedStore)
6704     MIB.addReg(Reg, RegState::Define);
6705   for (MachineOperand &BeforeOp : BeforeOps)
6706     MIB.add(BeforeOp);
6707   if (FoldedLoad)
6708     MIB.addReg(Reg);
6709   for (MachineOperand &AfterOp : AfterOps)
6710     MIB.add(AfterOp);
6711   for (MachineOperand &ImpOp : ImpOps) {
6712     MIB.addReg(ImpOp.getReg(),
6713                getDefRegState(ImpOp.isDef()) |
6714                RegState::Implicit |
6715                getKillRegState(ImpOp.isKill()) |
6716                getDeadRegState(ImpOp.isDead()) |
6717                getUndefRegState(ImpOp.isUndef()));
6718   }
6719   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6720   switch (DataMI->getOpcode()) {
6721   default: break;
6722   case X86::CMP64ri32:
6723   case X86::CMP64ri8:
6724   case X86::CMP32ri:
6725   case X86::CMP32ri8:
6726   case X86::CMP16ri:
6727   case X86::CMP16ri8:
6728   case X86::CMP8ri: {
6729     MachineOperand &MO0 = DataMI->getOperand(0);
6730     MachineOperand &MO1 = DataMI->getOperand(1);
6731     if (MO1.isImm() && MO1.getImm() == 0) {
6732       unsigned NewOpc;
6733       switch (DataMI->getOpcode()) {
6734       default: llvm_unreachable("Unreachable!");
6735       case X86::CMP64ri8:
6736       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6737       case X86::CMP32ri8:
6738       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6739       case X86::CMP16ri8:
6740       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6741       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6742       }
6743       DataMI->setDesc(get(NewOpc));
6744       MO1.ChangeToRegister(MO0.getReg(), false);
6745     }
6746   }
6747   }
6748   NewMIs.push_back(DataMI);
6749 
6750   // Emit the store instruction.
6751   if (UnfoldStore) {
6752     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6753     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6754     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6755     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6756     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6757     DebugLoc DL;
6758     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6759     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6760       MIB.add(AddrOps[i]);
6761     MIB.addReg(Reg, RegState::Kill);
6762     MIB.setMemRefs(MMOs);
6763     NewMIs.push_back(MIB);
6764   }
6765 
6766   return true;
6767 }
6768 
6769 bool
6770 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6771                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6772   if (!N->isMachineOpcode())
6773     return false;
6774 
6775   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6776   if (I == nullptr)
6777     return false;
6778   unsigned Opc = I->DstOp;
6779   unsigned Index = I->Flags & TB_INDEX_MASK;
6780   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6781   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6782   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6783   const MCInstrDesc &MCID = get(Opc);
6784   MachineFunction &MF = DAG.getMachineFunction();
6785   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6786   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6787   unsigned NumDefs = MCID.NumDefs;
6788   std::vector<SDValue> AddrOps;
6789   std::vector<SDValue> BeforeOps;
6790   std::vector<SDValue> AfterOps;
6791   SDLoc dl(N);
6792   unsigned NumOps = N->getNumOperands();
6793   for (unsigned i = 0; i != NumOps-1; ++i) {
6794     SDValue Op = N->getOperand(i);
6795     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6796       AddrOps.push_back(Op);
6797     else if (i < Index-NumDefs)
6798       BeforeOps.push_back(Op);
6799     else if (i > Index-NumDefs)
6800       AfterOps.push_back(Op);
6801   }
6802   SDValue Chain = N->getOperand(NumOps-1);
6803   AddrOps.push_back(Chain);
6804 
6805   // Emit the load instruction.
6806   SDNode *Load = nullptr;
6807   if (FoldedLoad) {
6808     EVT VT = *TRI.legalclasstypes_begin(*RC);
6809     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6810     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6811         Subtarget.isUnalignedMem16Slow())
6812       // Do not introduce a slow unaligned load.
6813       return false;
6814     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6815     // memory access is slow above.
6816 
6817     unsigned Opc;
6818     if (FoldedBCast) {
6819       Opc = getBroadcastOpcode(I, RC, Subtarget);
6820     } else {
6821       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6822       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6823       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6824     }
6825 
6826     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6827     NewNodes.push_back(Load);
6828 
6829     // Preserve memory reference information.
6830     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6831   }
6832 
6833   // Emit the data processing instruction.
6834   std::vector<EVT> VTs;
6835   const TargetRegisterClass *DstRC = nullptr;
6836   if (MCID.getNumDefs() > 0) {
6837     DstRC = getRegClass(MCID, 0, &RI, MF);
6838     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6839   }
6840   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6841     EVT VT = N->getValueType(i);
6842     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6843       VTs.push_back(VT);
6844   }
6845   if (Load)
6846     BeforeOps.push_back(SDValue(Load, 0));
6847   llvm::append_range(BeforeOps, AfterOps);
6848   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6849   switch (Opc) {
6850     default: break;
6851     case X86::CMP64ri32:
6852     case X86::CMP64ri8:
6853     case X86::CMP32ri:
6854     case X86::CMP32ri8:
6855     case X86::CMP16ri:
6856     case X86::CMP16ri8:
6857     case X86::CMP8ri:
6858       if (isNullConstant(BeforeOps[1])) {
6859         switch (Opc) {
6860           default: llvm_unreachable("Unreachable!");
6861           case X86::CMP64ri8:
6862           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6863           case X86::CMP32ri8:
6864           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6865           case X86::CMP16ri8:
6866           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6867           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6868         }
6869         BeforeOps[1] = BeforeOps[0];
6870       }
6871   }
6872   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6873   NewNodes.push_back(NewNode);
6874 
6875   // Emit the store instruction.
6876   if (FoldedStore) {
6877     AddrOps.pop_back();
6878     AddrOps.push_back(SDValue(NewNode, 0));
6879     AddrOps.push_back(Chain);
6880     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6881     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6882         Subtarget.isUnalignedMem16Slow())
6883       // Do not introduce a slow unaligned store.
6884       return false;
6885     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6886     // memory access is slow above.
6887     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6888     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6889     SDNode *Store =
6890         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6891                            dl, MVT::Other, AddrOps);
6892     NewNodes.push_back(Store);
6893 
6894     // Preserve memory reference information.
6895     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6896   }
6897 
6898   return true;
6899 }
6900 
6901 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6902                                       bool UnfoldLoad, bool UnfoldStore,
6903                                       unsigned *LoadRegIndex) const {
6904   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6905   if (I == nullptr)
6906     return 0;
6907   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6908   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6909   if (UnfoldLoad && !FoldedLoad)
6910     return 0;
6911   if (UnfoldStore && !FoldedStore)
6912     return 0;
6913   if (LoadRegIndex)
6914     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6915   return I->DstOp;
6916 }
6917 
6918 bool
6919 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6920                                      int64_t &Offset1, int64_t &Offset2) const {
6921   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6922     return false;
6923   unsigned Opc1 = Load1->getMachineOpcode();
6924   unsigned Opc2 = Load2->getMachineOpcode();
6925   switch (Opc1) {
6926   default: return false;
6927   case X86::MOV8rm:
6928   case X86::MOV16rm:
6929   case X86::MOV32rm:
6930   case X86::MOV64rm:
6931   case X86::LD_Fp32m:
6932   case X86::LD_Fp64m:
6933   case X86::LD_Fp80m:
6934   case X86::MOVSSrm:
6935   case X86::MOVSSrm_alt:
6936   case X86::MOVSDrm:
6937   case X86::MOVSDrm_alt:
6938   case X86::MMX_MOVD64rm:
6939   case X86::MMX_MOVQ64rm:
6940   case X86::MOVAPSrm:
6941   case X86::MOVUPSrm:
6942   case X86::MOVAPDrm:
6943   case X86::MOVUPDrm:
6944   case X86::MOVDQArm:
6945   case X86::MOVDQUrm:
6946   // AVX load instructions
6947   case X86::VMOVSSrm:
6948   case X86::VMOVSSrm_alt:
6949   case X86::VMOVSDrm:
6950   case X86::VMOVSDrm_alt:
6951   case X86::VMOVAPSrm:
6952   case X86::VMOVUPSrm:
6953   case X86::VMOVAPDrm:
6954   case X86::VMOVUPDrm:
6955   case X86::VMOVDQArm:
6956   case X86::VMOVDQUrm:
6957   case X86::VMOVAPSYrm:
6958   case X86::VMOVUPSYrm:
6959   case X86::VMOVAPDYrm:
6960   case X86::VMOVUPDYrm:
6961   case X86::VMOVDQAYrm:
6962   case X86::VMOVDQUYrm:
6963   // AVX512 load instructions
6964   case X86::VMOVSSZrm:
6965   case X86::VMOVSSZrm_alt:
6966   case X86::VMOVSDZrm:
6967   case X86::VMOVSDZrm_alt:
6968   case X86::VMOVAPSZ128rm:
6969   case X86::VMOVUPSZ128rm:
6970   case X86::VMOVAPSZ128rm_NOVLX:
6971   case X86::VMOVUPSZ128rm_NOVLX:
6972   case X86::VMOVAPDZ128rm:
6973   case X86::VMOVUPDZ128rm:
6974   case X86::VMOVDQU8Z128rm:
6975   case X86::VMOVDQU16Z128rm:
6976   case X86::VMOVDQA32Z128rm:
6977   case X86::VMOVDQU32Z128rm:
6978   case X86::VMOVDQA64Z128rm:
6979   case X86::VMOVDQU64Z128rm:
6980   case X86::VMOVAPSZ256rm:
6981   case X86::VMOVUPSZ256rm:
6982   case X86::VMOVAPSZ256rm_NOVLX:
6983   case X86::VMOVUPSZ256rm_NOVLX:
6984   case X86::VMOVAPDZ256rm:
6985   case X86::VMOVUPDZ256rm:
6986   case X86::VMOVDQU8Z256rm:
6987   case X86::VMOVDQU16Z256rm:
6988   case X86::VMOVDQA32Z256rm:
6989   case X86::VMOVDQU32Z256rm:
6990   case X86::VMOVDQA64Z256rm:
6991   case X86::VMOVDQU64Z256rm:
6992   case X86::VMOVAPSZrm:
6993   case X86::VMOVUPSZrm:
6994   case X86::VMOVAPDZrm:
6995   case X86::VMOVUPDZrm:
6996   case X86::VMOVDQU8Zrm:
6997   case X86::VMOVDQU16Zrm:
6998   case X86::VMOVDQA32Zrm:
6999   case X86::VMOVDQU32Zrm:
7000   case X86::VMOVDQA64Zrm:
7001   case X86::VMOVDQU64Zrm:
7002   case X86::KMOVBkm:
7003   case X86::KMOVWkm:
7004   case X86::KMOVDkm:
7005   case X86::KMOVQkm:
7006     break;
7007   }
7008   switch (Opc2) {
7009   default: return false;
7010   case X86::MOV8rm:
7011   case X86::MOV16rm:
7012   case X86::MOV32rm:
7013   case X86::MOV64rm:
7014   case X86::LD_Fp32m:
7015   case X86::LD_Fp64m:
7016   case X86::LD_Fp80m:
7017   case X86::MOVSSrm:
7018   case X86::MOVSSrm_alt:
7019   case X86::MOVSDrm:
7020   case X86::MOVSDrm_alt:
7021   case X86::MMX_MOVD64rm:
7022   case X86::MMX_MOVQ64rm:
7023   case X86::MOVAPSrm:
7024   case X86::MOVUPSrm:
7025   case X86::MOVAPDrm:
7026   case X86::MOVUPDrm:
7027   case X86::MOVDQArm:
7028   case X86::MOVDQUrm:
7029   // AVX load instructions
7030   case X86::VMOVSSrm:
7031   case X86::VMOVSSrm_alt:
7032   case X86::VMOVSDrm:
7033   case X86::VMOVSDrm_alt:
7034   case X86::VMOVAPSrm:
7035   case X86::VMOVUPSrm:
7036   case X86::VMOVAPDrm:
7037   case X86::VMOVUPDrm:
7038   case X86::VMOVDQArm:
7039   case X86::VMOVDQUrm:
7040   case X86::VMOVAPSYrm:
7041   case X86::VMOVUPSYrm:
7042   case X86::VMOVAPDYrm:
7043   case X86::VMOVUPDYrm:
7044   case X86::VMOVDQAYrm:
7045   case X86::VMOVDQUYrm:
7046   // AVX512 load instructions
7047   case X86::VMOVSSZrm:
7048   case X86::VMOVSSZrm_alt:
7049   case X86::VMOVSDZrm:
7050   case X86::VMOVSDZrm_alt:
7051   case X86::VMOVAPSZ128rm:
7052   case X86::VMOVUPSZ128rm:
7053   case X86::VMOVAPSZ128rm_NOVLX:
7054   case X86::VMOVUPSZ128rm_NOVLX:
7055   case X86::VMOVAPDZ128rm:
7056   case X86::VMOVUPDZ128rm:
7057   case X86::VMOVDQU8Z128rm:
7058   case X86::VMOVDQU16Z128rm:
7059   case X86::VMOVDQA32Z128rm:
7060   case X86::VMOVDQU32Z128rm:
7061   case X86::VMOVDQA64Z128rm:
7062   case X86::VMOVDQU64Z128rm:
7063   case X86::VMOVAPSZ256rm:
7064   case X86::VMOVUPSZ256rm:
7065   case X86::VMOVAPSZ256rm_NOVLX:
7066   case X86::VMOVUPSZ256rm_NOVLX:
7067   case X86::VMOVAPDZ256rm:
7068   case X86::VMOVUPDZ256rm:
7069   case X86::VMOVDQU8Z256rm:
7070   case X86::VMOVDQU16Z256rm:
7071   case X86::VMOVDQA32Z256rm:
7072   case X86::VMOVDQU32Z256rm:
7073   case X86::VMOVDQA64Z256rm:
7074   case X86::VMOVDQU64Z256rm:
7075   case X86::VMOVAPSZrm:
7076   case X86::VMOVUPSZrm:
7077   case X86::VMOVAPDZrm:
7078   case X86::VMOVUPDZrm:
7079   case X86::VMOVDQU8Zrm:
7080   case X86::VMOVDQU16Zrm:
7081   case X86::VMOVDQA32Zrm:
7082   case X86::VMOVDQU32Zrm:
7083   case X86::VMOVDQA64Zrm:
7084   case X86::VMOVDQU64Zrm:
7085   case X86::KMOVBkm:
7086   case X86::KMOVWkm:
7087   case X86::KMOVDkm:
7088   case X86::KMOVQkm:
7089     break;
7090   }
7091 
7092   // Lambda to check if both the loads have the same value for an operand index.
7093   auto HasSameOp = [&](int I) {
7094     return Load1->getOperand(I) == Load2->getOperand(I);
7095   };
7096 
7097   // All operands except the displacement should match.
7098   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
7099       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
7100     return false;
7101 
7102   // Chain Operand must be the same.
7103   if (!HasSameOp(5))
7104     return false;
7105 
7106   // Now let's examine if the displacements are constants.
7107   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
7108   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
7109   if (!Disp1 || !Disp2)
7110     return false;
7111 
7112   Offset1 = Disp1->getSExtValue();
7113   Offset2 = Disp2->getSExtValue();
7114   return true;
7115 }
7116 
7117 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
7118                                            int64_t Offset1, int64_t Offset2,
7119                                            unsigned NumLoads) const {
7120   assert(Offset2 > Offset1);
7121   if ((Offset2 - Offset1) / 8 > 64)
7122     return false;
7123 
7124   unsigned Opc1 = Load1->getMachineOpcode();
7125   unsigned Opc2 = Load2->getMachineOpcode();
7126   if (Opc1 != Opc2)
7127     return false;  // FIXME: overly conservative?
7128 
7129   switch (Opc1) {
7130   default: break;
7131   case X86::LD_Fp32m:
7132   case X86::LD_Fp64m:
7133   case X86::LD_Fp80m:
7134   case X86::MMX_MOVD64rm:
7135   case X86::MMX_MOVQ64rm:
7136     return false;
7137   }
7138 
7139   EVT VT = Load1->getValueType(0);
7140   switch (VT.getSimpleVT().SimpleTy) {
7141   default:
7142     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
7143     // have 16 of them to play with.
7144     if (Subtarget.is64Bit()) {
7145       if (NumLoads >= 3)
7146         return false;
7147     } else if (NumLoads) {
7148       return false;
7149     }
7150     break;
7151   case MVT::i8:
7152   case MVT::i16:
7153   case MVT::i32:
7154   case MVT::i64:
7155   case MVT::f32:
7156   case MVT::f64:
7157     if (NumLoads)
7158       return false;
7159     break;
7160   }
7161 
7162   return true;
7163 }
7164 
7165 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
7166                                         const MachineBasicBlock *MBB,
7167                                         const MachineFunction &MF) const {
7168 
7169   // ENDBR instructions should not be scheduled around.
7170   unsigned Opcode = MI.getOpcode();
7171   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
7172       Opcode == X86::LDTILECFG)
7173     return true;
7174 
7175   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
7176 }
7177 
7178 bool X86InstrInfo::
7179 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
7180   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
7181   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7182   Cond[0].setImm(GetOppositeBranchCondition(CC));
7183   return false;
7184 }
7185 
7186 bool X86InstrInfo::
7187 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7188   // FIXME: Return false for x87 stack register classes for now. We can't
7189   // allow any loads of these registers before FpGet_ST0_80.
7190   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
7191            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
7192            RC == &X86::RFP80RegClass);
7193 }
7194 
7195 /// Return a virtual register initialized with the
7196 /// the global base register value. Output instructions required to
7197 /// initialize the register in the function entry block, if necessary.
7198 ///
7199 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7200 ///
7201 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
7202   assert((!Subtarget.is64Bit() ||
7203           MF->getTarget().getCodeModel() == CodeModel::Medium ||
7204           MF->getTarget().getCodeModel() == CodeModel::Large) &&
7205          "X86-64 PIC uses RIP relative addressing");
7206 
7207   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7208   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
7209   if (GlobalBaseReg != 0)
7210     return GlobalBaseReg;
7211 
7212   // Create the register. The code to initialize it is inserted
7213   // later, by the CGBR pass (below).
7214   MachineRegisterInfo &RegInfo = MF->getRegInfo();
7215   GlobalBaseReg = RegInfo.createVirtualRegister(
7216       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
7217   X86FI->setGlobalBaseReg(GlobalBaseReg);
7218   return GlobalBaseReg;
7219 }
7220 
7221 // These are the replaceable SSE instructions. Some of these have Int variants
7222 // that we don't include here. We don't want to replace instructions selected
7223 // by intrinsics.
7224 static const uint16_t ReplaceableInstrs[][3] = {
7225   //PackedSingle     PackedDouble    PackedInt
7226   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
7227   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7228   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7229   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7230   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7231   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
7232   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
7233   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
7234   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
7235   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
7236   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
7237   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
7238   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7239   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7240   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7241   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7242   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7243   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7244   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7245   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7246   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7247   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
7248   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
7249   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
7250   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
7251   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
7252   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
7253   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
7254   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
7255   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
7256   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
7257   // AVX 128-bit support
7258   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7259   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7260   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7261   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7262   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7263   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
7264   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
7265   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
7266   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
7267   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
7268   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
7269   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
7270   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7271   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7272   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7273   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7274   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7275   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7276   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7277   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7278   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7279   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
7280   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
7281   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
7282   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
7283   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
7284   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
7285   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
7286   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
7287   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
7288   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
7289   // AVX 256-bit support
7290   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7291   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7292   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7293   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7294   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7295   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
7296   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
7297   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
7298   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
7299   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
7300   // AVX512 support
7301   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
7302   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7303   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
7304   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
7305   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
7306   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
7307   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
7308   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
7309   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
7310   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
7311   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
7312   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
7313   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
7314   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
7315   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
7316   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
7317   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
7318   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
7319   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
7320   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
7321   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
7322   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
7323   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
7324   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
7325   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
7326   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
7327   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
7328   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
7329   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
7330   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
7331   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
7332   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
7333   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
7334   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
7335   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
7336   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
7337   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
7338   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
7339   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
7340   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
7341   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
7342   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
7343   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
7344   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
7345   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
7346   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
7347   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
7348   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
7349   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
7350   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
7351   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
7352   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
7353   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
7354   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
7355   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
7356   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
7357   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
7358   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
7359   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
7360   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
7361   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
7362   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
7363   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
7364   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
7365   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
7366   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
7367   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
7368   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
7369   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
7370   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
7371   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
7372   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
7373   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
7374   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
7375   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
7376   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
7377   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
7378   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
7379   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
7380   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
7381   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
7382   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
7383   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
7384   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
7385   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
7386   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
7387   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
7388   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
7389   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
7390   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
7391   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
7392   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
7393 };
7394 
7395 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7396   //PackedSingle       PackedDouble       PackedInt
7397   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7398   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7399   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7400   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7401   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7402   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7403   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7404   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7405   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7406   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7407   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7408   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7409   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
7410   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
7411   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7412   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7413   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7414   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
7415   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
7416   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
7417   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7418   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7419   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7420   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7421   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7422   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7423   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7424   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7425   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7426   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7427   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7428 };
7429 
7430 static const uint16_t ReplaceableInstrsFP[][3] = {
7431   //PackedSingle         PackedDouble
7432   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7433   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7434   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7435   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7436   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7437   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7438   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7439   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7440   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7441 };
7442 
7443 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7444   //PackedSingle       PackedDouble       PackedInt
7445   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7446   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7447   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7448   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7449 };
7450 
7451 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7452   // Two integer columns for 64-bit and 32-bit elements.
7453   //PackedSingle        PackedDouble        PackedInt             PackedInt
7454   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7455   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7456   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7457   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7458   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7459   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7460   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7461   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7462   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7463   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7464   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7465   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7466   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7467   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7468   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7469 };
7470 
7471 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7472   // Two integer columns for 64-bit and 32-bit elements.
7473   //PackedSingle        PackedDouble        PackedInt           PackedInt
7474   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7475   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7476   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7477   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7478   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7479   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7480   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7481   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7482   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7483   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7484   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7485   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7486   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7487   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7488   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7489   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7490   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7491   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7492   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7493   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7494   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7495   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7496   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7497   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7498 };
7499 
7500 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7501   // Two integer columns for 64-bit and 32-bit elements.
7502   //PackedSingle          PackedDouble
7503   //PackedInt             PackedInt
7504   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7505     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7506   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7507     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7508   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7509     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7510   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7511     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7512   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7513     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7514   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7515     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7516   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7517     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7518   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7519     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7520   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7521     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7522   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7523     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7524   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7525     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7526   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7527     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7528   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7529     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7530   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7531     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7532   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7533     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7534   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7535     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7536   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7537     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7538   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7539     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7540   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7541     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7542   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7543     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7544   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7545     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7546   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7547     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7548   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7549     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7550   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7551     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7552   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7553     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7554   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7555     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7556   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7557     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7558   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7559     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7560   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7561     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7562   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7563     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7564   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7565     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7566   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7567     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7568   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7569     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7570   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7571     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7572   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7573     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7574   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7575     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7576   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7577     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7578   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7579     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7580   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7581     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7582   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7583     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7584   { X86::VORPSZrmk,       X86::VORPDZrmk,
7585     X86::VPORQZrmk,       X86::VPORDZrmk       },
7586   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7587     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7588   { X86::VORPSZrrk,       X86::VORPDZrrk,
7589     X86::VPORQZrrk,       X86::VPORDZrrk       },
7590   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7591     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7592   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7593     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7594   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7595     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7596   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7597     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7598   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7599     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7600   // Broadcast loads can be handled the same as masked operations to avoid
7601   // changing element size.
7602   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7603     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7604   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7605     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7606   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7607     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7608   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7609     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7610   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7611     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7612   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7613     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7614   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7615     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7616   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7617     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7618   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7619     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7620   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7621     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7622   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7623     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7624   { X86::VORPSZrmb,       X86::VORPDZrmb,
7625     X86::VPORQZrmb,       X86::VPORDZrmb       },
7626   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7627     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7628   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7629     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7630   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7631     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7632   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7633     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7634   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7635     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7636   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7637     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7638   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7639     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7640   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7641     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7642   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7643     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7644   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7645     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7646   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7647     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7648   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7649     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7650   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7651     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7652   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7653     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7654   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7655     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7656   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7657     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7658   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7659     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7660   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7661     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7662   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7663     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7664   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7665     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7666   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7667     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7668   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7669     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7670   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7671     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7672   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7673     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7674   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7675     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7676   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7677     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7678   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7679     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7680 };
7681 
7682 // NOTE: These should only be used by the custom domain methods.
7683 static const uint16_t ReplaceableBlendInstrs[][3] = {
7684   //PackedSingle             PackedDouble             PackedInt
7685   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7686   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7687   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7688   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7689   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7690   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7691 };
7692 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7693   //PackedSingle             PackedDouble             PackedInt
7694   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7695   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7696   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7697   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7698 };
7699 
7700 // Special table for changing EVEX logic instructions to VEX.
7701 // TODO: Should we run EVEX->VEX earlier?
7702 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7703   // Two integer columns for 64-bit and 32-bit elements.
7704   //PackedSingle     PackedDouble     PackedInt           PackedInt
7705   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7706   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7707   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7708   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7709   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7710   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7711   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7712   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7713   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7714   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7715   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7716   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7717   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7718   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7719   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7720   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7721 };
7722 
7723 // FIXME: Some shuffle and unpack instructions have equivalents in different
7724 // domains, but they require a bit more work than just switching opcodes.
7725 
7726 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7727                               ArrayRef<uint16_t[3]> Table) {
7728   for (const uint16_t (&Row)[3] : Table)
7729     if (Row[domain-1] == opcode)
7730       return Row;
7731   return nullptr;
7732 }
7733 
7734 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7735                                     ArrayRef<uint16_t[4]> Table) {
7736   // If this is the integer domain make sure to check both integer columns.
7737   for (const uint16_t (&Row)[4] : Table)
7738     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7739       return Row;
7740   return nullptr;
7741 }
7742 
7743 // Helper to attempt to widen/narrow blend masks.
7744 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7745                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7746   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7747          "Illegal blend mask scale");
7748   unsigned NewMask = 0;
7749 
7750   if ((OldWidth % NewWidth) == 0) {
7751     unsigned Scale = OldWidth / NewWidth;
7752     unsigned SubMask = (1u << Scale) - 1;
7753     for (unsigned i = 0; i != NewWidth; ++i) {
7754       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7755       if (Sub == SubMask)
7756         NewMask |= (1u << i);
7757       else if (Sub != 0x0)
7758         return false;
7759     }
7760   } else {
7761     unsigned Scale = NewWidth / OldWidth;
7762     unsigned SubMask = (1u << Scale) - 1;
7763     for (unsigned i = 0; i != OldWidth; ++i) {
7764       if (OldMask & (1 << i)) {
7765         NewMask |= (SubMask << (i * Scale));
7766       }
7767     }
7768   }
7769 
7770   if (pNewMask)
7771     *pNewMask = NewMask;
7772   return true;
7773 }
7774 
7775 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7776   unsigned Opcode = MI.getOpcode();
7777   unsigned NumOperands = MI.getDesc().getNumOperands();
7778 
7779   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7780     uint16_t validDomains = 0;
7781     if (MI.getOperand(NumOperands - 1).isImm()) {
7782       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7783       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7784         validDomains |= 0x2; // PackedSingle
7785       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7786         validDomains |= 0x4; // PackedDouble
7787       if (!Is256 || Subtarget.hasAVX2())
7788         validDomains |= 0x8; // PackedInt
7789     }
7790     return validDomains;
7791   };
7792 
7793   switch (Opcode) {
7794   case X86::BLENDPDrmi:
7795   case X86::BLENDPDrri:
7796   case X86::VBLENDPDrmi:
7797   case X86::VBLENDPDrri:
7798     return GetBlendDomains(2, false);
7799   case X86::VBLENDPDYrmi:
7800   case X86::VBLENDPDYrri:
7801     return GetBlendDomains(4, true);
7802   case X86::BLENDPSrmi:
7803   case X86::BLENDPSrri:
7804   case X86::VBLENDPSrmi:
7805   case X86::VBLENDPSrri:
7806   case X86::VPBLENDDrmi:
7807   case X86::VPBLENDDrri:
7808     return GetBlendDomains(4, false);
7809   case X86::VBLENDPSYrmi:
7810   case X86::VBLENDPSYrri:
7811   case X86::VPBLENDDYrmi:
7812   case X86::VPBLENDDYrri:
7813     return GetBlendDomains(8, true);
7814   case X86::PBLENDWrmi:
7815   case X86::PBLENDWrri:
7816   case X86::VPBLENDWrmi:
7817   case X86::VPBLENDWrri:
7818   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7819   case X86::VPBLENDWYrmi:
7820   case X86::VPBLENDWYrri:
7821     return GetBlendDomains(8, false);
7822   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7823   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7824   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7825   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7826   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7827   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7828   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7829   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7830   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7831   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7832   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7833   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7834   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7835   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7836   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7837   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7838     // If we don't have DQI see if we can still switch from an EVEX integer
7839     // instruction to a VEX floating point instruction.
7840     if (Subtarget.hasDQI())
7841       return 0;
7842 
7843     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7844       return 0;
7845     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7846       return 0;
7847     // Register forms will have 3 operands. Memory form will have more.
7848     if (NumOperands == 3 &&
7849         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7850       return 0;
7851 
7852     // All domains are valid.
7853     return 0xe;
7854   case X86::MOVHLPSrr:
7855     // We can swap domains when both inputs are the same register.
7856     // FIXME: This doesn't catch all the cases we would like. If the input
7857     // register isn't KILLed by the instruction, the two address instruction
7858     // pass puts a COPY on one input. The other input uses the original
7859     // register. This prevents the same physical register from being used by
7860     // both inputs.
7861     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7862         MI.getOperand(0).getSubReg() == 0 &&
7863         MI.getOperand(1).getSubReg() == 0 &&
7864         MI.getOperand(2).getSubReg() == 0)
7865       return 0x6;
7866     return 0;
7867   case X86::SHUFPDrri:
7868     return 0x6;
7869   }
7870   return 0;
7871 }
7872 
7873 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7874                                             unsigned Domain) const {
7875   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7876   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7877   assert(dom && "Not an SSE instruction");
7878 
7879   unsigned Opcode = MI.getOpcode();
7880   unsigned NumOperands = MI.getDesc().getNumOperands();
7881 
7882   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7883     if (MI.getOperand(NumOperands - 1).isImm()) {
7884       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7885       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7886       unsigned NewImm = Imm;
7887 
7888       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7889       if (!table)
7890         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7891 
7892       if (Domain == 1) { // PackedSingle
7893         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7894       } else if (Domain == 2) { // PackedDouble
7895         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7896       } else if (Domain == 3) { // PackedInt
7897         if (Subtarget.hasAVX2()) {
7898           // If we are already VPBLENDW use that, else use VPBLENDD.
7899           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7900             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7901             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7902           }
7903         } else {
7904           assert(!Is256 && "128-bit vector expected");
7905           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7906         }
7907       }
7908 
7909       assert(table && table[Domain - 1] && "Unknown domain op");
7910       MI.setDesc(get(table[Domain - 1]));
7911       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7912     }
7913     return true;
7914   };
7915 
7916   switch (Opcode) {
7917   case X86::BLENDPDrmi:
7918   case X86::BLENDPDrri:
7919   case X86::VBLENDPDrmi:
7920   case X86::VBLENDPDrri:
7921     return SetBlendDomain(2, false);
7922   case X86::VBLENDPDYrmi:
7923   case X86::VBLENDPDYrri:
7924     return SetBlendDomain(4, true);
7925   case X86::BLENDPSrmi:
7926   case X86::BLENDPSrri:
7927   case X86::VBLENDPSrmi:
7928   case X86::VBLENDPSrri:
7929   case X86::VPBLENDDrmi:
7930   case X86::VPBLENDDrri:
7931     return SetBlendDomain(4, false);
7932   case X86::VBLENDPSYrmi:
7933   case X86::VBLENDPSYrri:
7934   case X86::VPBLENDDYrmi:
7935   case X86::VPBLENDDYrri:
7936     return SetBlendDomain(8, true);
7937   case X86::PBLENDWrmi:
7938   case X86::PBLENDWrri:
7939   case X86::VPBLENDWrmi:
7940   case X86::VPBLENDWrri:
7941     return SetBlendDomain(8, false);
7942   case X86::VPBLENDWYrmi:
7943   case X86::VPBLENDWYrri:
7944     return SetBlendDomain(16, true);
7945   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7946   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7947   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7948   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7949   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7950   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7951   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7952   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7953   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7954   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7955   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7956   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7957   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7958   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7959   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7960   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7961     // Without DQI, convert EVEX instructions to VEX instructions.
7962     if (Subtarget.hasDQI())
7963       return false;
7964 
7965     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7966                                          ReplaceableCustomAVX512LogicInstrs);
7967     assert(table && "Instruction not found in table?");
7968     // Don't change integer Q instructions to D instructions and
7969     // use D intructions if we started with a PS instruction.
7970     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7971       Domain = 4;
7972     MI.setDesc(get(table[Domain - 1]));
7973     return true;
7974   }
7975   case X86::UNPCKHPDrr:
7976   case X86::MOVHLPSrr:
7977     // We just need to commute the instruction which will switch the domains.
7978     if (Domain != dom && Domain != 3 &&
7979         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7980         MI.getOperand(0).getSubReg() == 0 &&
7981         MI.getOperand(1).getSubReg() == 0 &&
7982         MI.getOperand(2).getSubReg() == 0) {
7983       commuteInstruction(MI, false);
7984       return true;
7985     }
7986     // We must always return true for MOVHLPSrr.
7987     if (Opcode == X86::MOVHLPSrr)
7988       return true;
7989     break;
7990   case X86::SHUFPDrri: {
7991     if (Domain == 1) {
7992       unsigned Imm = MI.getOperand(3).getImm();
7993       unsigned NewImm = 0x44;
7994       if (Imm & 1) NewImm |= 0x0a;
7995       if (Imm & 2) NewImm |= 0xa0;
7996       MI.getOperand(3).setImm(NewImm);
7997       MI.setDesc(get(X86::SHUFPSrri));
7998     }
7999     return true;
8000   }
8001   }
8002   return false;
8003 }
8004 
8005 std::pair<uint16_t, uint16_t>
8006 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
8007   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8008   unsigned opcode = MI.getOpcode();
8009   uint16_t validDomains = 0;
8010   if (domain) {
8011     // Attempt to match for custom instructions.
8012     validDomains = getExecutionDomainCustom(MI);
8013     if (validDomains)
8014       return std::make_pair(domain, validDomains);
8015 
8016     if (lookup(opcode, domain, ReplaceableInstrs)) {
8017       validDomains = 0xe;
8018     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
8019       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
8020     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
8021       validDomains = 0x6;
8022     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
8023       // Insert/extract instructions should only effect domain if AVX2
8024       // is enabled.
8025       if (!Subtarget.hasAVX2())
8026         return std::make_pair(0, 0);
8027       validDomains = 0xe;
8028     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
8029       validDomains = 0xe;
8030     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
8031                                                   ReplaceableInstrsAVX512DQ)) {
8032       validDomains = 0xe;
8033     } else if (Subtarget.hasDQI()) {
8034       if (const uint16_t *table = lookupAVX512(opcode, domain,
8035                                              ReplaceableInstrsAVX512DQMasked)) {
8036         if (domain == 1 || (domain == 3 && table[3] == opcode))
8037           validDomains = 0xa;
8038         else
8039           validDomains = 0xc;
8040       }
8041     }
8042   }
8043   return std::make_pair(domain, validDomains);
8044 }
8045 
8046 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
8047   assert(Domain>0 && Domain<4 && "Invalid execution domain");
8048   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8049   assert(dom && "Not an SSE instruction");
8050 
8051   // Attempt to match for custom instructions.
8052   if (setExecutionDomainCustom(MI, Domain))
8053     return;
8054 
8055   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
8056   if (!table) { // try the other table
8057     assert((Subtarget.hasAVX2() || Domain < 3) &&
8058            "256-bit vector operations only available in AVX2");
8059     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
8060   }
8061   if (!table) { // try the FP table
8062     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
8063     assert((!table || Domain < 3) &&
8064            "Can only select PackedSingle or PackedDouble");
8065   }
8066   if (!table) { // try the other table
8067     assert(Subtarget.hasAVX2() &&
8068            "256-bit insert/extract only available in AVX2");
8069     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
8070   }
8071   if (!table) { // try the AVX512 table
8072     assert(Subtarget.hasAVX512() && "Requires AVX-512");
8073     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
8074     // Don't change integer Q instructions to D instructions.
8075     if (table && Domain == 3 && table[3] == MI.getOpcode())
8076       Domain = 4;
8077   }
8078   if (!table) { // try the AVX512DQ table
8079     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8080     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
8081     // Don't change integer Q instructions to D instructions and
8082     // use D instructions if we started with a PS instruction.
8083     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8084       Domain = 4;
8085   }
8086   if (!table) { // try the AVX512DQMasked table
8087     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8088     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
8089     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8090       Domain = 4;
8091   }
8092   assert(table && "Cannot change domain");
8093   MI.setDesc(get(table[Domain - 1]));
8094 }
8095 
8096 /// Return the noop instruction to use for a noop.
8097 MCInst X86InstrInfo::getNop() const {
8098   MCInst Nop;
8099   Nop.setOpcode(X86::NOOP);
8100   return Nop;
8101 }
8102 
8103 bool X86InstrInfo::isHighLatencyDef(int opc) const {
8104   switch (opc) {
8105   default: return false;
8106   case X86::DIVPDrm:
8107   case X86::DIVPDrr:
8108   case X86::DIVPSrm:
8109   case X86::DIVPSrr:
8110   case X86::DIVSDrm:
8111   case X86::DIVSDrm_Int:
8112   case X86::DIVSDrr:
8113   case X86::DIVSDrr_Int:
8114   case X86::DIVSSrm:
8115   case X86::DIVSSrm_Int:
8116   case X86::DIVSSrr:
8117   case X86::DIVSSrr_Int:
8118   case X86::SQRTPDm:
8119   case X86::SQRTPDr:
8120   case X86::SQRTPSm:
8121   case X86::SQRTPSr:
8122   case X86::SQRTSDm:
8123   case X86::SQRTSDm_Int:
8124   case X86::SQRTSDr:
8125   case X86::SQRTSDr_Int:
8126   case X86::SQRTSSm:
8127   case X86::SQRTSSm_Int:
8128   case X86::SQRTSSr:
8129   case X86::SQRTSSr_Int:
8130   // AVX instructions with high latency
8131   case X86::VDIVPDrm:
8132   case X86::VDIVPDrr:
8133   case X86::VDIVPDYrm:
8134   case X86::VDIVPDYrr:
8135   case X86::VDIVPSrm:
8136   case X86::VDIVPSrr:
8137   case X86::VDIVPSYrm:
8138   case X86::VDIVPSYrr:
8139   case X86::VDIVSDrm:
8140   case X86::VDIVSDrm_Int:
8141   case X86::VDIVSDrr:
8142   case X86::VDIVSDrr_Int:
8143   case X86::VDIVSSrm:
8144   case X86::VDIVSSrm_Int:
8145   case X86::VDIVSSrr:
8146   case X86::VDIVSSrr_Int:
8147   case X86::VSQRTPDm:
8148   case X86::VSQRTPDr:
8149   case X86::VSQRTPDYm:
8150   case X86::VSQRTPDYr:
8151   case X86::VSQRTPSm:
8152   case X86::VSQRTPSr:
8153   case X86::VSQRTPSYm:
8154   case X86::VSQRTPSYr:
8155   case X86::VSQRTSDm:
8156   case X86::VSQRTSDm_Int:
8157   case X86::VSQRTSDr:
8158   case X86::VSQRTSDr_Int:
8159   case X86::VSQRTSSm:
8160   case X86::VSQRTSSm_Int:
8161   case X86::VSQRTSSr:
8162   case X86::VSQRTSSr_Int:
8163   // AVX512 instructions with high latency
8164   case X86::VDIVPDZ128rm:
8165   case X86::VDIVPDZ128rmb:
8166   case X86::VDIVPDZ128rmbk:
8167   case X86::VDIVPDZ128rmbkz:
8168   case X86::VDIVPDZ128rmk:
8169   case X86::VDIVPDZ128rmkz:
8170   case X86::VDIVPDZ128rr:
8171   case X86::VDIVPDZ128rrk:
8172   case X86::VDIVPDZ128rrkz:
8173   case X86::VDIVPDZ256rm:
8174   case X86::VDIVPDZ256rmb:
8175   case X86::VDIVPDZ256rmbk:
8176   case X86::VDIVPDZ256rmbkz:
8177   case X86::VDIVPDZ256rmk:
8178   case X86::VDIVPDZ256rmkz:
8179   case X86::VDIVPDZ256rr:
8180   case X86::VDIVPDZ256rrk:
8181   case X86::VDIVPDZ256rrkz:
8182   case X86::VDIVPDZrrb:
8183   case X86::VDIVPDZrrbk:
8184   case X86::VDIVPDZrrbkz:
8185   case X86::VDIVPDZrm:
8186   case X86::VDIVPDZrmb:
8187   case X86::VDIVPDZrmbk:
8188   case X86::VDIVPDZrmbkz:
8189   case X86::VDIVPDZrmk:
8190   case X86::VDIVPDZrmkz:
8191   case X86::VDIVPDZrr:
8192   case X86::VDIVPDZrrk:
8193   case X86::VDIVPDZrrkz:
8194   case X86::VDIVPSZ128rm:
8195   case X86::VDIVPSZ128rmb:
8196   case X86::VDIVPSZ128rmbk:
8197   case X86::VDIVPSZ128rmbkz:
8198   case X86::VDIVPSZ128rmk:
8199   case X86::VDIVPSZ128rmkz:
8200   case X86::VDIVPSZ128rr:
8201   case X86::VDIVPSZ128rrk:
8202   case X86::VDIVPSZ128rrkz:
8203   case X86::VDIVPSZ256rm:
8204   case X86::VDIVPSZ256rmb:
8205   case X86::VDIVPSZ256rmbk:
8206   case X86::VDIVPSZ256rmbkz:
8207   case X86::VDIVPSZ256rmk:
8208   case X86::VDIVPSZ256rmkz:
8209   case X86::VDIVPSZ256rr:
8210   case X86::VDIVPSZ256rrk:
8211   case X86::VDIVPSZ256rrkz:
8212   case X86::VDIVPSZrrb:
8213   case X86::VDIVPSZrrbk:
8214   case X86::VDIVPSZrrbkz:
8215   case X86::VDIVPSZrm:
8216   case X86::VDIVPSZrmb:
8217   case X86::VDIVPSZrmbk:
8218   case X86::VDIVPSZrmbkz:
8219   case X86::VDIVPSZrmk:
8220   case X86::VDIVPSZrmkz:
8221   case X86::VDIVPSZrr:
8222   case X86::VDIVPSZrrk:
8223   case X86::VDIVPSZrrkz:
8224   case X86::VDIVSDZrm:
8225   case X86::VDIVSDZrr:
8226   case X86::VDIVSDZrm_Int:
8227   case X86::VDIVSDZrm_Intk:
8228   case X86::VDIVSDZrm_Intkz:
8229   case X86::VDIVSDZrr_Int:
8230   case X86::VDIVSDZrr_Intk:
8231   case X86::VDIVSDZrr_Intkz:
8232   case X86::VDIVSDZrrb_Int:
8233   case X86::VDIVSDZrrb_Intk:
8234   case X86::VDIVSDZrrb_Intkz:
8235   case X86::VDIVSSZrm:
8236   case X86::VDIVSSZrr:
8237   case X86::VDIVSSZrm_Int:
8238   case X86::VDIVSSZrm_Intk:
8239   case X86::VDIVSSZrm_Intkz:
8240   case X86::VDIVSSZrr_Int:
8241   case X86::VDIVSSZrr_Intk:
8242   case X86::VDIVSSZrr_Intkz:
8243   case X86::VDIVSSZrrb_Int:
8244   case X86::VDIVSSZrrb_Intk:
8245   case X86::VDIVSSZrrb_Intkz:
8246   case X86::VSQRTPDZ128m:
8247   case X86::VSQRTPDZ128mb:
8248   case X86::VSQRTPDZ128mbk:
8249   case X86::VSQRTPDZ128mbkz:
8250   case X86::VSQRTPDZ128mk:
8251   case X86::VSQRTPDZ128mkz:
8252   case X86::VSQRTPDZ128r:
8253   case X86::VSQRTPDZ128rk:
8254   case X86::VSQRTPDZ128rkz:
8255   case X86::VSQRTPDZ256m:
8256   case X86::VSQRTPDZ256mb:
8257   case X86::VSQRTPDZ256mbk:
8258   case X86::VSQRTPDZ256mbkz:
8259   case X86::VSQRTPDZ256mk:
8260   case X86::VSQRTPDZ256mkz:
8261   case X86::VSQRTPDZ256r:
8262   case X86::VSQRTPDZ256rk:
8263   case X86::VSQRTPDZ256rkz:
8264   case X86::VSQRTPDZm:
8265   case X86::VSQRTPDZmb:
8266   case X86::VSQRTPDZmbk:
8267   case X86::VSQRTPDZmbkz:
8268   case X86::VSQRTPDZmk:
8269   case X86::VSQRTPDZmkz:
8270   case X86::VSQRTPDZr:
8271   case X86::VSQRTPDZrb:
8272   case X86::VSQRTPDZrbk:
8273   case X86::VSQRTPDZrbkz:
8274   case X86::VSQRTPDZrk:
8275   case X86::VSQRTPDZrkz:
8276   case X86::VSQRTPSZ128m:
8277   case X86::VSQRTPSZ128mb:
8278   case X86::VSQRTPSZ128mbk:
8279   case X86::VSQRTPSZ128mbkz:
8280   case X86::VSQRTPSZ128mk:
8281   case X86::VSQRTPSZ128mkz:
8282   case X86::VSQRTPSZ128r:
8283   case X86::VSQRTPSZ128rk:
8284   case X86::VSQRTPSZ128rkz:
8285   case X86::VSQRTPSZ256m:
8286   case X86::VSQRTPSZ256mb:
8287   case X86::VSQRTPSZ256mbk:
8288   case X86::VSQRTPSZ256mbkz:
8289   case X86::VSQRTPSZ256mk:
8290   case X86::VSQRTPSZ256mkz:
8291   case X86::VSQRTPSZ256r:
8292   case X86::VSQRTPSZ256rk:
8293   case X86::VSQRTPSZ256rkz:
8294   case X86::VSQRTPSZm:
8295   case X86::VSQRTPSZmb:
8296   case X86::VSQRTPSZmbk:
8297   case X86::VSQRTPSZmbkz:
8298   case X86::VSQRTPSZmk:
8299   case X86::VSQRTPSZmkz:
8300   case X86::VSQRTPSZr:
8301   case X86::VSQRTPSZrb:
8302   case X86::VSQRTPSZrbk:
8303   case X86::VSQRTPSZrbkz:
8304   case X86::VSQRTPSZrk:
8305   case X86::VSQRTPSZrkz:
8306   case X86::VSQRTSDZm:
8307   case X86::VSQRTSDZm_Int:
8308   case X86::VSQRTSDZm_Intk:
8309   case X86::VSQRTSDZm_Intkz:
8310   case X86::VSQRTSDZr:
8311   case X86::VSQRTSDZr_Int:
8312   case X86::VSQRTSDZr_Intk:
8313   case X86::VSQRTSDZr_Intkz:
8314   case X86::VSQRTSDZrb_Int:
8315   case X86::VSQRTSDZrb_Intk:
8316   case X86::VSQRTSDZrb_Intkz:
8317   case X86::VSQRTSSZm:
8318   case X86::VSQRTSSZm_Int:
8319   case X86::VSQRTSSZm_Intk:
8320   case X86::VSQRTSSZm_Intkz:
8321   case X86::VSQRTSSZr:
8322   case X86::VSQRTSSZr_Int:
8323   case X86::VSQRTSSZr_Intk:
8324   case X86::VSQRTSSZr_Intkz:
8325   case X86::VSQRTSSZrb_Int:
8326   case X86::VSQRTSSZrb_Intk:
8327   case X86::VSQRTSSZrb_Intkz:
8328 
8329   case X86::VGATHERDPDYrm:
8330   case X86::VGATHERDPDZ128rm:
8331   case X86::VGATHERDPDZ256rm:
8332   case X86::VGATHERDPDZrm:
8333   case X86::VGATHERDPDrm:
8334   case X86::VGATHERDPSYrm:
8335   case X86::VGATHERDPSZ128rm:
8336   case X86::VGATHERDPSZ256rm:
8337   case X86::VGATHERDPSZrm:
8338   case X86::VGATHERDPSrm:
8339   case X86::VGATHERPF0DPDm:
8340   case X86::VGATHERPF0DPSm:
8341   case X86::VGATHERPF0QPDm:
8342   case X86::VGATHERPF0QPSm:
8343   case X86::VGATHERPF1DPDm:
8344   case X86::VGATHERPF1DPSm:
8345   case X86::VGATHERPF1QPDm:
8346   case X86::VGATHERPF1QPSm:
8347   case X86::VGATHERQPDYrm:
8348   case X86::VGATHERQPDZ128rm:
8349   case X86::VGATHERQPDZ256rm:
8350   case X86::VGATHERQPDZrm:
8351   case X86::VGATHERQPDrm:
8352   case X86::VGATHERQPSYrm:
8353   case X86::VGATHERQPSZ128rm:
8354   case X86::VGATHERQPSZ256rm:
8355   case X86::VGATHERQPSZrm:
8356   case X86::VGATHERQPSrm:
8357   case X86::VPGATHERDDYrm:
8358   case X86::VPGATHERDDZ128rm:
8359   case X86::VPGATHERDDZ256rm:
8360   case X86::VPGATHERDDZrm:
8361   case X86::VPGATHERDDrm:
8362   case X86::VPGATHERDQYrm:
8363   case X86::VPGATHERDQZ128rm:
8364   case X86::VPGATHERDQZ256rm:
8365   case X86::VPGATHERDQZrm:
8366   case X86::VPGATHERDQrm:
8367   case X86::VPGATHERQDYrm:
8368   case X86::VPGATHERQDZ128rm:
8369   case X86::VPGATHERQDZ256rm:
8370   case X86::VPGATHERQDZrm:
8371   case X86::VPGATHERQDrm:
8372   case X86::VPGATHERQQYrm:
8373   case X86::VPGATHERQQZ128rm:
8374   case X86::VPGATHERQQZ256rm:
8375   case X86::VPGATHERQQZrm:
8376   case X86::VPGATHERQQrm:
8377   case X86::VSCATTERDPDZ128mr:
8378   case X86::VSCATTERDPDZ256mr:
8379   case X86::VSCATTERDPDZmr:
8380   case X86::VSCATTERDPSZ128mr:
8381   case X86::VSCATTERDPSZ256mr:
8382   case X86::VSCATTERDPSZmr:
8383   case X86::VSCATTERPF0DPDm:
8384   case X86::VSCATTERPF0DPSm:
8385   case X86::VSCATTERPF0QPDm:
8386   case X86::VSCATTERPF0QPSm:
8387   case X86::VSCATTERPF1DPDm:
8388   case X86::VSCATTERPF1DPSm:
8389   case X86::VSCATTERPF1QPDm:
8390   case X86::VSCATTERPF1QPSm:
8391   case X86::VSCATTERQPDZ128mr:
8392   case X86::VSCATTERQPDZ256mr:
8393   case X86::VSCATTERQPDZmr:
8394   case X86::VSCATTERQPSZ128mr:
8395   case X86::VSCATTERQPSZ256mr:
8396   case X86::VSCATTERQPSZmr:
8397   case X86::VPSCATTERDDZ128mr:
8398   case X86::VPSCATTERDDZ256mr:
8399   case X86::VPSCATTERDDZmr:
8400   case X86::VPSCATTERDQZ128mr:
8401   case X86::VPSCATTERDQZ256mr:
8402   case X86::VPSCATTERDQZmr:
8403   case X86::VPSCATTERQDZ128mr:
8404   case X86::VPSCATTERQDZ256mr:
8405   case X86::VPSCATTERQDZmr:
8406   case X86::VPSCATTERQQZ128mr:
8407   case X86::VPSCATTERQQZ256mr:
8408   case X86::VPSCATTERQQZmr:
8409     return true;
8410   }
8411 }
8412 
8413 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8414                                          const MachineRegisterInfo *MRI,
8415                                          const MachineInstr &DefMI,
8416                                          unsigned DefIdx,
8417                                          const MachineInstr &UseMI,
8418                                          unsigned UseIdx) const {
8419   return isHighLatencyDef(DefMI.getOpcode());
8420 }
8421 
8422 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8423                                            const MachineBasicBlock *MBB) const {
8424   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8425          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8426 
8427   // Integer binary math/logic instructions have a third source operand:
8428   // the EFLAGS register. That operand must be both defined here and never
8429   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8430   // not change anything because rearranging the operands could affect other
8431   // instructions that depend on the exact status flags (zero, sign, etc.)
8432   // that are set by using these particular operands with this operation.
8433   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8434   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8435          "Implicit def isn't flags?");
8436   if (FlagDef && !FlagDef->isDead())
8437     return false;
8438 
8439   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8440 }
8441 
8442 // TODO: There are many more machine instruction opcodes to match:
8443 //       1. Other data types (integer, vectors)
8444 //       2. Other math / logic operations (xor, or)
8445 //       3. Other forms of the same operation (intrinsics and other variants)
8446 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8447   switch (Inst.getOpcode()) {
8448   case X86::AND8rr:
8449   case X86::AND16rr:
8450   case X86::AND32rr:
8451   case X86::AND64rr:
8452   case X86::OR8rr:
8453   case X86::OR16rr:
8454   case X86::OR32rr:
8455   case X86::OR64rr:
8456   case X86::XOR8rr:
8457   case X86::XOR16rr:
8458   case X86::XOR32rr:
8459   case X86::XOR64rr:
8460   case X86::IMUL16rr:
8461   case X86::IMUL32rr:
8462   case X86::IMUL64rr:
8463   case X86::PANDrr:
8464   case X86::PORrr:
8465   case X86::PXORrr:
8466   case X86::ANDPDrr:
8467   case X86::ANDPSrr:
8468   case X86::ORPDrr:
8469   case X86::ORPSrr:
8470   case X86::XORPDrr:
8471   case X86::XORPSrr:
8472   case X86::PADDBrr:
8473   case X86::PADDWrr:
8474   case X86::PADDDrr:
8475   case X86::PADDQrr:
8476   case X86::PMULLWrr:
8477   case X86::PMULLDrr:
8478   case X86::PMAXSBrr:
8479   case X86::PMAXSDrr:
8480   case X86::PMAXSWrr:
8481   case X86::PMAXUBrr:
8482   case X86::PMAXUDrr:
8483   case X86::PMAXUWrr:
8484   case X86::PMINSBrr:
8485   case X86::PMINSDrr:
8486   case X86::PMINSWrr:
8487   case X86::PMINUBrr:
8488   case X86::PMINUDrr:
8489   case X86::PMINUWrr:
8490   case X86::VPANDrr:
8491   case X86::VPANDYrr:
8492   case X86::VPANDDZ128rr:
8493   case X86::VPANDDZ256rr:
8494   case X86::VPANDDZrr:
8495   case X86::VPANDQZ128rr:
8496   case X86::VPANDQZ256rr:
8497   case X86::VPANDQZrr:
8498   case X86::VPORrr:
8499   case X86::VPORYrr:
8500   case X86::VPORDZ128rr:
8501   case X86::VPORDZ256rr:
8502   case X86::VPORDZrr:
8503   case X86::VPORQZ128rr:
8504   case X86::VPORQZ256rr:
8505   case X86::VPORQZrr:
8506   case X86::VPXORrr:
8507   case X86::VPXORYrr:
8508   case X86::VPXORDZ128rr:
8509   case X86::VPXORDZ256rr:
8510   case X86::VPXORDZrr:
8511   case X86::VPXORQZ128rr:
8512   case X86::VPXORQZ256rr:
8513   case X86::VPXORQZrr:
8514   case X86::VANDPDrr:
8515   case X86::VANDPSrr:
8516   case X86::VANDPDYrr:
8517   case X86::VANDPSYrr:
8518   case X86::VANDPDZ128rr:
8519   case X86::VANDPSZ128rr:
8520   case X86::VANDPDZ256rr:
8521   case X86::VANDPSZ256rr:
8522   case X86::VANDPDZrr:
8523   case X86::VANDPSZrr:
8524   case X86::VORPDrr:
8525   case X86::VORPSrr:
8526   case X86::VORPDYrr:
8527   case X86::VORPSYrr:
8528   case X86::VORPDZ128rr:
8529   case X86::VORPSZ128rr:
8530   case X86::VORPDZ256rr:
8531   case X86::VORPSZ256rr:
8532   case X86::VORPDZrr:
8533   case X86::VORPSZrr:
8534   case X86::VXORPDrr:
8535   case X86::VXORPSrr:
8536   case X86::VXORPDYrr:
8537   case X86::VXORPSYrr:
8538   case X86::VXORPDZ128rr:
8539   case X86::VXORPSZ128rr:
8540   case X86::VXORPDZ256rr:
8541   case X86::VXORPSZ256rr:
8542   case X86::VXORPDZrr:
8543   case X86::VXORPSZrr:
8544   case X86::KADDBrr:
8545   case X86::KADDWrr:
8546   case X86::KADDDrr:
8547   case X86::KADDQrr:
8548   case X86::KANDBrr:
8549   case X86::KANDWrr:
8550   case X86::KANDDrr:
8551   case X86::KANDQrr:
8552   case X86::KORBrr:
8553   case X86::KORWrr:
8554   case X86::KORDrr:
8555   case X86::KORQrr:
8556   case X86::KXORBrr:
8557   case X86::KXORWrr:
8558   case X86::KXORDrr:
8559   case X86::KXORQrr:
8560   case X86::VPADDBrr:
8561   case X86::VPADDWrr:
8562   case X86::VPADDDrr:
8563   case X86::VPADDQrr:
8564   case X86::VPADDBYrr:
8565   case X86::VPADDWYrr:
8566   case X86::VPADDDYrr:
8567   case X86::VPADDQYrr:
8568   case X86::VPADDBZ128rr:
8569   case X86::VPADDWZ128rr:
8570   case X86::VPADDDZ128rr:
8571   case X86::VPADDQZ128rr:
8572   case X86::VPADDBZ256rr:
8573   case X86::VPADDWZ256rr:
8574   case X86::VPADDDZ256rr:
8575   case X86::VPADDQZ256rr:
8576   case X86::VPADDBZrr:
8577   case X86::VPADDWZrr:
8578   case X86::VPADDDZrr:
8579   case X86::VPADDQZrr:
8580   case X86::VPMULLWrr:
8581   case X86::VPMULLWYrr:
8582   case X86::VPMULLWZ128rr:
8583   case X86::VPMULLWZ256rr:
8584   case X86::VPMULLWZrr:
8585   case X86::VPMULLDrr:
8586   case X86::VPMULLDYrr:
8587   case X86::VPMULLDZ128rr:
8588   case X86::VPMULLDZ256rr:
8589   case X86::VPMULLDZrr:
8590   case X86::VPMULLQZ128rr:
8591   case X86::VPMULLQZ256rr:
8592   case X86::VPMULLQZrr:
8593   case X86::VPMAXSBrr:
8594   case X86::VPMAXSBYrr:
8595   case X86::VPMAXSBZ128rr:
8596   case X86::VPMAXSBZ256rr:
8597   case X86::VPMAXSBZrr:
8598   case X86::VPMAXSDrr:
8599   case X86::VPMAXSDYrr:
8600   case X86::VPMAXSDZ128rr:
8601   case X86::VPMAXSDZ256rr:
8602   case X86::VPMAXSDZrr:
8603   case X86::VPMAXSQZ128rr:
8604   case X86::VPMAXSQZ256rr:
8605   case X86::VPMAXSQZrr:
8606   case X86::VPMAXSWrr:
8607   case X86::VPMAXSWYrr:
8608   case X86::VPMAXSWZ128rr:
8609   case X86::VPMAXSWZ256rr:
8610   case X86::VPMAXSWZrr:
8611   case X86::VPMAXUBrr:
8612   case X86::VPMAXUBYrr:
8613   case X86::VPMAXUBZ128rr:
8614   case X86::VPMAXUBZ256rr:
8615   case X86::VPMAXUBZrr:
8616   case X86::VPMAXUDrr:
8617   case X86::VPMAXUDYrr:
8618   case X86::VPMAXUDZ128rr:
8619   case X86::VPMAXUDZ256rr:
8620   case X86::VPMAXUDZrr:
8621   case X86::VPMAXUQZ128rr:
8622   case X86::VPMAXUQZ256rr:
8623   case X86::VPMAXUQZrr:
8624   case X86::VPMAXUWrr:
8625   case X86::VPMAXUWYrr:
8626   case X86::VPMAXUWZ128rr:
8627   case X86::VPMAXUWZ256rr:
8628   case X86::VPMAXUWZrr:
8629   case X86::VPMINSBrr:
8630   case X86::VPMINSBYrr:
8631   case X86::VPMINSBZ128rr:
8632   case X86::VPMINSBZ256rr:
8633   case X86::VPMINSBZrr:
8634   case X86::VPMINSDrr:
8635   case X86::VPMINSDYrr:
8636   case X86::VPMINSDZ128rr:
8637   case X86::VPMINSDZ256rr:
8638   case X86::VPMINSDZrr:
8639   case X86::VPMINSQZ128rr:
8640   case X86::VPMINSQZ256rr:
8641   case X86::VPMINSQZrr:
8642   case X86::VPMINSWrr:
8643   case X86::VPMINSWYrr:
8644   case X86::VPMINSWZ128rr:
8645   case X86::VPMINSWZ256rr:
8646   case X86::VPMINSWZrr:
8647   case X86::VPMINUBrr:
8648   case X86::VPMINUBYrr:
8649   case X86::VPMINUBZ128rr:
8650   case X86::VPMINUBZ256rr:
8651   case X86::VPMINUBZrr:
8652   case X86::VPMINUDrr:
8653   case X86::VPMINUDYrr:
8654   case X86::VPMINUDZ128rr:
8655   case X86::VPMINUDZ256rr:
8656   case X86::VPMINUDZrr:
8657   case X86::VPMINUQZ128rr:
8658   case X86::VPMINUQZ256rr:
8659   case X86::VPMINUQZrr:
8660   case X86::VPMINUWrr:
8661   case X86::VPMINUWYrr:
8662   case X86::VPMINUWZ128rr:
8663   case X86::VPMINUWZ256rr:
8664   case X86::VPMINUWZrr:
8665   // Normal min/max instructions are not commutative because of NaN and signed
8666   // zero semantics, but these are. Thus, there's no need to check for global
8667   // relaxed math; the instructions themselves have the properties we need.
8668   case X86::MAXCPDrr:
8669   case X86::MAXCPSrr:
8670   case X86::MAXCSDrr:
8671   case X86::MAXCSSrr:
8672   case X86::MINCPDrr:
8673   case X86::MINCPSrr:
8674   case X86::MINCSDrr:
8675   case X86::MINCSSrr:
8676   case X86::VMAXCPDrr:
8677   case X86::VMAXCPSrr:
8678   case X86::VMAXCPDYrr:
8679   case X86::VMAXCPSYrr:
8680   case X86::VMAXCPDZ128rr:
8681   case X86::VMAXCPSZ128rr:
8682   case X86::VMAXCPDZ256rr:
8683   case X86::VMAXCPSZ256rr:
8684   case X86::VMAXCPDZrr:
8685   case X86::VMAXCPSZrr:
8686   case X86::VMAXCSDrr:
8687   case X86::VMAXCSSrr:
8688   case X86::VMAXCSDZrr:
8689   case X86::VMAXCSSZrr:
8690   case X86::VMINCPDrr:
8691   case X86::VMINCPSrr:
8692   case X86::VMINCPDYrr:
8693   case X86::VMINCPSYrr:
8694   case X86::VMINCPDZ128rr:
8695   case X86::VMINCPSZ128rr:
8696   case X86::VMINCPDZ256rr:
8697   case X86::VMINCPSZ256rr:
8698   case X86::VMINCPDZrr:
8699   case X86::VMINCPSZrr:
8700   case X86::VMINCSDrr:
8701   case X86::VMINCSSrr:
8702   case X86::VMINCSDZrr:
8703   case X86::VMINCSSZrr:
8704   case X86::VMAXCPHZ128rr:
8705   case X86::VMAXCPHZ256rr:
8706   case X86::VMAXCPHZrr:
8707   case X86::VMAXCSHZrr:
8708   case X86::VMINCPHZ128rr:
8709   case X86::VMINCPHZ256rr:
8710   case X86::VMINCPHZrr:
8711   case X86::VMINCSHZrr:
8712     return true;
8713   case X86::ADDPDrr:
8714   case X86::ADDPSrr:
8715   case X86::ADDSDrr:
8716   case X86::ADDSSrr:
8717   case X86::MULPDrr:
8718   case X86::MULPSrr:
8719   case X86::MULSDrr:
8720   case X86::MULSSrr:
8721   case X86::VADDPDrr:
8722   case X86::VADDPSrr:
8723   case X86::VADDPDYrr:
8724   case X86::VADDPSYrr:
8725   case X86::VADDPDZ128rr:
8726   case X86::VADDPSZ128rr:
8727   case X86::VADDPDZ256rr:
8728   case X86::VADDPSZ256rr:
8729   case X86::VADDPDZrr:
8730   case X86::VADDPSZrr:
8731   case X86::VADDSDrr:
8732   case X86::VADDSSrr:
8733   case X86::VADDSDZrr:
8734   case X86::VADDSSZrr:
8735   case X86::VMULPDrr:
8736   case X86::VMULPSrr:
8737   case X86::VMULPDYrr:
8738   case X86::VMULPSYrr:
8739   case X86::VMULPDZ128rr:
8740   case X86::VMULPSZ128rr:
8741   case X86::VMULPDZ256rr:
8742   case X86::VMULPSZ256rr:
8743   case X86::VMULPDZrr:
8744   case X86::VMULPSZrr:
8745   case X86::VMULSDrr:
8746   case X86::VMULSSrr:
8747   case X86::VMULSDZrr:
8748   case X86::VMULSSZrr:
8749   case X86::VADDPHZ128rr:
8750   case X86::VADDPHZ256rr:
8751   case X86::VADDPHZrr:
8752   case X86::VADDSHZrr:
8753   case X86::VMULPHZ128rr:
8754   case X86::VMULPHZ256rr:
8755   case X86::VMULPHZrr:
8756   case X86::VMULSHZrr:
8757     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8758            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8759   default:
8760     return false;
8761   }
8762 }
8763 
8764 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8765 /// register then, if possible, describe the value in terms of the source
8766 /// register.
8767 static Optional<ParamLoadedValue>
8768 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8769                          const TargetRegisterInfo *TRI) {
8770   Register DestReg = MI.getOperand(0).getReg();
8771   Register SrcReg = MI.getOperand(1).getReg();
8772 
8773   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8774 
8775   // If the described register is the destination, just return the source.
8776   if (DestReg == DescribedReg)
8777     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8778 
8779   // If the described register is a sub-register of the destination register,
8780   // then pick out the source register's corresponding sub-register.
8781   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8782     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8783     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8784   }
8785 
8786   // The remaining case to consider is when the described register is a
8787   // super-register of the destination register. MOV8rr and MOV16rr does not
8788   // write to any of the other bytes in the register, meaning that we'd have to
8789   // describe the value using a combination of the source register and the
8790   // non-overlapping bits in the described register, which is not currently
8791   // possible.
8792   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8793       !TRI->isSuperRegister(DestReg, DescribedReg))
8794     return None;
8795 
8796   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8797   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8798 }
8799 
8800 Optional<ParamLoadedValue>
8801 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8802   const MachineOperand *Op = nullptr;
8803   DIExpression *Expr = nullptr;
8804 
8805   const TargetRegisterInfo *TRI = &getRegisterInfo();
8806 
8807   switch (MI.getOpcode()) {
8808   case X86::LEA32r:
8809   case X86::LEA64r:
8810   case X86::LEA64_32r: {
8811     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8812     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8813       return None;
8814 
8815     // Operand 4 could be global address. For now we do not support
8816     // such situation.
8817     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8818       return None;
8819 
8820     const MachineOperand &Op1 = MI.getOperand(1);
8821     const MachineOperand &Op2 = MI.getOperand(3);
8822     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8823                            Register::isPhysicalRegister(Op2.getReg())));
8824 
8825     // Omit situations like:
8826     // %rsi = lea %rsi, 4, ...
8827     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8828         Op2.getReg() == MI.getOperand(0).getReg())
8829       return None;
8830     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8831               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8832              (Op2.getReg() != X86::NoRegister &&
8833               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8834       return None;
8835 
8836     int64_t Coef = MI.getOperand(2).getImm();
8837     int64_t Offset = MI.getOperand(4).getImm();
8838     SmallVector<uint64_t, 8> Ops;
8839 
8840     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8841       Op = &Op1;
8842     } else if (Op1.isFI())
8843       Op = &Op1;
8844 
8845     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8846       Ops.push_back(dwarf::DW_OP_constu);
8847       Ops.push_back(Coef + 1);
8848       Ops.push_back(dwarf::DW_OP_mul);
8849     } else {
8850       if (Op && Op2.getReg() != X86::NoRegister) {
8851         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8852         if (dwarfReg < 0)
8853           return None;
8854         else if (dwarfReg < 32) {
8855           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8856           Ops.push_back(0);
8857         } else {
8858           Ops.push_back(dwarf::DW_OP_bregx);
8859           Ops.push_back(dwarfReg);
8860           Ops.push_back(0);
8861         }
8862       } else if (!Op) {
8863         assert(Op2.getReg() != X86::NoRegister);
8864         Op = &Op2;
8865       }
8866 
8867       if (Coef > 1) {
8868         assert(Op2.getReg() != X86::NoRegister);
8869         Ops.push_back(dwarf::DW_OP_constu);
8870         Ops.push_back(Coef);
8871         Ops.push_back(dwarf::DW_OP_mul);
8872       }
8873 
8874       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8875           Op2.getReg() != X86::NoRegister) {
8876         Ops.push_back(dwarf::DW_OP_plus);
8877       }
8878     }
8879 
8880     DIExpression::appendOffset(Ops, Offset);
8881     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8882 
8883     return ParamLoadedValue(*Op, Expr);;
8884   }
8885   case X86::MOV8ri:
8886   case X86::MOV16ri:
8887     // TODO: Handle MOV8ri and MOV16ri.
8888     return None;
8889   case X86::MOV32ri:
8890   case X86::MOV64ri:
8891   case X86::MOV64ri32:
8892     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8893     // 64-bit parameters, so we need to consider super-registers.
8894     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8895       return None;
8896     return ParamLoadedValue(MI.getOperand(1), Expr);
8897   case X86::MOV8rr:
8898   case X86::MOV16rr:
8899   case X86::MOV32rr:
8900   case X86::MOV64rr:
8901     return describeMOVrrLoadedValue(MI, Reg, TRI);
8902   case X86::XOR32rr: {
8903     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8904     // super-registers.
8905     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8906       return None;
8907     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8908       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8909     return None;
8910   }
8911   case X86::MOVSX64rr32: {
8912     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8913     // cases like this:
8914     //
8915     //  $ebx = [...]
8916     //  $rdi = MOVSX64rr32 $ebx
8917     //  $esi = MOV32rr $edi
8918     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8919       return None;
8920 
8921     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8922 
8923     // If the described register is the destination register we need to
8924     // sign-extend the source register from 32 bits. The other case we handle
8925     // is when the described register is the 32-bit sub-register of the
8926     // destination register, in case we just need to return the source
8927     // register.
8928     if (Reg == MI.getOperand(0).getReg())
8929       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8930     else
8931       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8932              "Unhandled sub-register case for MOVSX64rr32");
8933 
8934     return ParamLoadedValue(MI.getOperand(1), Expr);
8935   }
8936   default:
8937     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8938     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8939   }
8940 }
8941 
8942 /// This is an architecture-specific helper function of reassociateOps.
8943 /// Set special operand attributes for new instructions after reassociation.
8944 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8945                                          MachineInstr &OldMI2,
8946                                          MachineInstr &NewMI1,
8947                                          MachineInstr &NewMI2) const {
8948   // Propagate FP flags from the original instructions.
8949   // But clear poison-generating flags because those may not be valid now.
8950   // TODO: There should be a helper function for copying only fast-math-flags.
8951   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8952   NewMI1.setFlags(IntersectedFlags);
8953   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8954   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8955   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8956 
8957   NewMI2.setFlags(IntersectedFlags);
8958   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8959   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8960   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8961 
8962   // Integer instructions may define an implicit EFLAGS dest register operand.
8963   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8964   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8965 
8966   assert(!OldFlagDef1 == !OldFlagDef2 &&
8967          "Unexpected instruction type for reassociation");
8968 
8969   if (!OldFlagDef1 || !OldFlagDef2)
8970     return;
8971 
8972   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8973          "Must have dead EFLAGS operand in reassociable instruction");
8974 
8975   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8976   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8977 
8978   assert(NewFlagDef1 && NewFlagDef2 &&
8979          "Unexpected operand in reassociable instruction");
8980 
8981   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8982   // of this pass or other passes. The EFLAGS operands must be dead in these new
8983   // instructions because the EFLAGS operands in the original instructions must
8984   // be dead in order for reassociation to occur.
8985   NewFlagDef1->setIsDead();
8986   NewFlagDef2->setIsDead();
8987 }
8988 
8989 std::pair<unsigned, unsigned>
8990 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8991   return std::make_pair(TF, 0u);
8992 }
8993 
8994 ArrayRef<std::pair<unsigned, const char *>>
8995 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8996   using namespace X86II;
8997   static const std::pair<unsigned, const char *> TargetFlags[] = {
8998       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8999       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
9000       {MO_GOT, "x86-got"},
9001       {MO_GOTOFF, "x86-gotoff"},
9002       {MO_GOTPCREL, "x86-gotpcrel"},
9003       {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"},
9004       {MO_PLT, "x86-plt"},
9005       {MO_TLSGD, "x86-tlsgd"},
9006       {MO_TLSLD, "x86-tlsld"},
9007       {MO_TLSLDM, "x86-tlsldm"},
9008       {MO_GOTTPOFF, "x86-gottpoff"},
9009       {MO_INDNTPOFF, "x86-indntpoff"},
9010       {MO_TPOFF, "x86-tpoff"},
9011       {MO_DTPOFF, "x86-dtpoff"},
9012       {MO_NTPOFF, "x86-ntpoff"},
9013       {MO_GOTNTPOFF, "x86-gotntpoff"},
9014       {MO_DLLIMPORT, "x86-dllimport"},
9015       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
9016       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
9017       {MO_TLVP, "x86-tlvp"},
9018       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
9019       {MO_SECREL, "x86-secrel"},
9020       {MO_COFFSTUB, "x86-coffstub"}};
9021   return makeArrayRef(TargetFlags);
9022 }
9023 
9024 namespace {
9025   /// Create Global Base Reg pass. This initializes the PIC
9026   /// global base register for x86-32.
9027   struct CGBR : public MachineFunctionPass {
9028     static char ID;
9029     CGBR() : MachineFunctionPass(ID) {}
9030 
9031     bool runOnMachineFunction(MachineFunction &MF) override {
9032       const X86TargetMachine *TM =
9033         static_cast<const X86TargetMachine *>(&MF.getTarget());
9034       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
9035 
9036       // Don't do anything in the 64-bit small and kernel code models. They use
9037       // RIP-relative addressing for everything.
9038       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
9039                             TM->getCodeModel() == CodeModel::Kernel))
9040         return false;
9041 
9042       // Only emit a global base reg in PIC mode.
9043       if (!TM->isPositionIndependent())
9044         return false;
9045 
9046       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9047       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
9048 
9049       // If we didn't need a GlobalBaseReg, don't insert code.
9050       if (GlobalBaseReg == 0)
9051         return false;
9052 
9053       // Insert the set of GlobalBaseReg into the first MBB of the function
9054       MachineBasicBlock &FirstMBB = MF.front();
9055       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
9056       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
9057       MachineRegisterInfo &RegInfo = MF.getRegInfo();
9058       const X86InstrInfo *TII = STI.getInstrInfo();
9059 
9060       Register PC;
9061       if (STI.isPICStyleGOT())
9062         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
9063       else
9064         PC = GlobalBaseReg;
9065 
9066       if (STI.is64Bit()) {
9067         if (TM->getCodeModel() == CodeModel::Medium) {
9068           // In the medium code model, use a RIP-relative LEA to materialize the
9069           // GOT.
9070           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
9071               .addReg(X86::RIP)
9072               .addImm(0)
9073               .addReg(0)
9074               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
9075               .addReg(0);
9076         } else if (TM->getCodeModel() == CodeModel::Large) {
9077           // In the large code model, we are aiming for this code, though the
9078           // register allocation may vary:
9079           //   leaq .LN$pb(%rip), %rax
9080           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
9081           //   addq %rcx, %rax
9082           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
9083           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
9084           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
9085           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
9086               .addReg(X86::RIP)
9087               .addImm(0)
9088               .addReg(0)
9089               .addSym(MF.getPICBaseSymbol())
9090               .addReg(0);
9091           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
9092           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
9093               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
9094                                  X86II::MO_PIC_BASE_OFFSET);
9095           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
9096               .addReg(PBReg, RegState::Kill)
9097               .addReg(GOTReg, RegState::Kill);
9098         } else {
9099           llvm_unreachable("unexpected code model");
9100         }
9101       } else {
9102         // Operand of MovePCtoStack is completely ignored by asm printer. It's
9103         // only used in JIT code emission as displacement to pc.
9104         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
9105 
9106         // If we're using vanilla 'GOT' PIC style, we should use relative
9107         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
9108         if (STI.isPICStyleGOT()) {
9109           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
9110           // %some_register
9111           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
9112               .addReg(PC)
9113               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
9114                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
9115         }
9116       }
9117 
9118       return true;
9119     }
9120 
9121     StringRef getPassName() const override {
9122       return "X86 PIC Global Base Reg Initialization";
9123     }
9124 
9125     void getAnalysisUsage(AnalysisUsage &AU) const override {
9126       AU.setPreservesCFG();
9127       MachineFunctionPass::getAnalysisUsage(AU);
9128     }
9129   };
9130 } // namespace
9131 
9132 char CGBR::ID = 0;
9133 FunctionPass*
9134 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
9135 
9136 namespace {
9137   struct LDTLSCleanup : public MachineFunctionPass {
9138     static char ID;
9139     LDTLSCleanup() : MachineFunctionPass(ID) {}
9140 
9141     bool runOnMachineFunction(MachineFunction &MF) override {
9142       if (skipFunction(MF.getFunction()))
9143         return false;
9144 
9145       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
9146       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
9147         // No point folding accesses if there isn't at least two.
9148         return false;
9149       }
9150 
9151       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
9152       return VisitNode(DT->getRootNode(), 0);
9153     }
9154 
9155     // Visit the dominator subtree rooted at Node in pre-order.
9156     // If TLSBaseAddrReg is non-null, then use that to replace any
9157     // TLS_base_addr instructions. Otherwise, create the register
9158     // when the first such instruction is seen, and then use it
9159     // as we encounter more instructions.
9160     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
9161       MachineBasicBlock *BB = Node->getBlock();
9162       bool Changed = false;
9163 
9164       // Traverse the current block.
9165       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
9166            ++I) {
9167         switch (I->getOpcode()) {
9168           case X86::TLS_base_addr32:
9169           case X86::TLS_base_addr64:
9170             if (TLSBaseAddrReg)
9171               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
9172             else
9173               I = SetRegister(*I, &TLSBaseAddrReg);
9174             Changed = true;
9175             break;
9176           default:
9177             break;
9178         }
9179       }
9180 
9181       // Visit the children of this block in the dominator tree.
9182       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
9183         Changed |= VisitNode(*I, TLSBaseAddrReg);
9184       }
9185 
9186       return Changed;
9187     }
9188 
9189     // Replace the TLS_base_addr instruction I with a copy from
9190     // TLSBaseAddrReg, returning the new instruction.
9191     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
9192                                          unsigned TLSBaseAddrReg) {
9193       MachineFunction *MF = I.getParent()->getParent();
9194       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9195       const bool is64Bit = STI.is64Bit();
9196       const X86InstrInfo *TII = STI.getInstrInfo();
9197 
9198       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
9199       MachineInstr *Copy =
9200           BuildMI(*I.getParent(), I, I.getDebugLoc(),
9201                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
9202               .addReg(TLSBaseAddrReg);
9203 
9204       // Erase the TLS_base_addr instruction.
9205       I.eraseFromParent();
9206 
9207       return Copy;
9208     }
9209 
9210     // Create a virtual register in *TLSBaseAddrReg, and populate it by
9211     // inserting a copy instruction after I. Returns the new instruction.
9212     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
9213       MachineFunction *MF = I.getParent()->getParent();
9214       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9215       const bool is64Bit = STI.is64Bit();
9216       const X86InstrInfo *TII = STI.getInstrInfo();
9217 
9218       // Create a virtual register for the TLS base address.
9219       MachineRegisterInfo &RegInfo = MF->getRegInfo();
9220       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
9221                                                       ? &X86::GR64RegClass
9222                                                       : &X86::GR32RegClass);
9223 
9224       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
9225       MachineInstr *Next = I.getNextNode();
9226       MachineInstr *Copy =
9227           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
9228                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
9229               .addReg(is64Bit ? X86::RAX : X86::EAX);
9230 
9231       return Copy;
9232     }
9233 
9234     StringRef getPassName() const override {
9235       return "Local Dynamic TLS Access Clean-up";
9236     }
9237 
9238     void getAnalysisUsage(AnalysisUsage &AU) const override {
9239       AU.setPreservesCFG();
9240       AU.addRequired<MachineDominatorTree>();
9241       MachineFunctionPass::getAnalysisUsage(AU);
9242     }
9243   };
9244 }
9245 
9246 char LDTLSCleanup::ID = 0;
9247 FunctionPass*
9248 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
9249 
9250 /// Constants defining how certain sequences should be outlined.
9251 ///
9252 /// \p MachineOutlinerDefault implies that the function is called with a call
9253 /// instruction, and a return must be emitted for the outlined function frame.
9254 ///
9255 /// That is,
9256 ///
9257 /// I1                                 OUTLINED_FUNCTION:
9258 /// I2 --> call OUTLINED_FUNCTION       I1
9259 /// I3                                  I2
9260 ///                                     I3
9261 ///                                     ret
9262 ///
9263 /// * Call construction overhead: 1 (call instruction)
9264 /// * Frame construction overhead: 1 (return instruction)
9265 ///
9266 /// \p MachineOutlinerTailCall implies that the function is being tail called.
9267 /// A jump is emitted instead of a call, and the return is already present in
9268 /// the outlined sequence. That is,
9269 ///
9270 /// I1                                 OUTLINED_FUNCTION:
9271 /// I2 --> jmp OUTLINED_FUNCTION       I1
9272 /// ret                                I2
9273 ///                                    ret
9274 ///
9275 /// * Call construction overhead: 1 (jump instruction)
9276 /// * Frame construction overhead: 0 (don't need to return)
9277 ///
9278 enum MachineOutlinerClass {
9279   MachineOutlinerDefault,
9280   MachineOutlinerTailCall
9281 };
9282 
9283 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
9284     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
9285   unsigned SequenceSize =
9286       std::accumulate(RepeatedSequenceLocs[0].front(),
9287                       std::next(RepeatedSequenceLocs[0].back()), 0,
9288                       [](unsigned Sum, const MachineInstr &MI) {
9289                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
9290                         // we can't tell the cost.  Just assume each instruction
9291                         // is one byte.
9292                         if (MI.isDebugInstr() || MI.isKill())
9293                           return Sum;
9294                         return Sum + 1;
9295                       });
9296 
9297   // We check to see if CFI Instructions are present, and if they are
9298   // we find the number of CFI Instructions in the candidates.
9299   unsigned CFICount = 0;
9300   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
9301   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
9302        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
9303     if (MBBI->isCFIInstruction())
9304       CFICount++;
9305     MBBI++;
9306   }
9307 
9308   // We compare the number of found CFI Instructions to  the number of CFI
9309   // instructions in the parent function for each candidate.  We must check this
9310   // since if we outline one of the CFI instructions in a function, we have to
9311   // outline them all for correctness. If we do not, the address offsets will be
9312   // incorrect between the two sections of the program.
9313   for (outliner::Candidate &C : RepeatedSequenceLocs) {
9314     std::vector<MCCFIInstruction> CFIInstructions =
9315         C.getMF()->getFrameInstructions();
9316 
9317     if (CFICount > 0 && CFICount != CFIInstructions.size())
9318       return outliner::OutlinedFunction();
9319   }
9320 
9321   // FIXME: Use real size in bytes for call and ret instructions.
9322   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
9323     for (outliner::Candidate &C : RepeatedSequenceLocs)
9324       C.setCallInfo(MachineOutlinerTailCall, 1);
9325 
9326     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
9327                                       0, // Number of bytes to emit frame.
9328                                       MachineOutlinerTailCall // Type of frame.
9329     );
9330   }
9331 
9332   if (CFICount > 0)
9333     return outliner::OutlinedFunction();
9334 
9335   for (outliner::Candidate &C : RepeatedSequenceLocs)
9336     C.setCallInfo(MachineOutlinerDefault, 1);
9337 
9338   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
9339                                     MachineOutlinerDefault);
9340 }
9341 
9342 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
9343                                            bool OutlineFromLinkOnceODRs) const {
9344   const Function &F = MF.getFunction();
9345 
9346   // Does the function use a red zone? If it does, then we can't risk messing
9347   // with the stack.
9348   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
9349     // It could have a red zone. If it does, then we don't want to touch it.
9350     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9351     if (!X86FI || X86FI->getUsesRedZone())
9352       return false;
9353   }
9354 
9355   // If we *don't* want to outline from things that could potentially be deduped
9356   // then return false.
9357   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
9358       return false;
9359 
9360   // This function is viable for outlining, so return true.
9361   return true;
9362 }
9363 
9364 outliner::InstrType
9365 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
9366   MachineInstr &MI = *MIT;
9367   // Don't allow debug values to impact outlining type.
9368   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
9369     return outliner::InstrType::Invisible;
9370 
9371   // At this point, KILL instructions don't really tell us much so we can go
9372   // ahead and skip over them.
9373   if (MI.isKill())
9374     return outliner::InstrType::Invisible;
9375 
9376   // Is this a tail call? If yes, we can outline as a tail call.
9377   if (isTailCall(MI))
9378     return outliner::InstrType::Legal;
9379 
9380   // Is this the terminator of a basic block?
9381   if (MI.isTerminator() || MI.isReturn()) {
9382 
9383     // Does its parent have any successors in its MachineFunction?
9384     if (MI.getParent()->succ_empty())
9385       return outliner::InstrType::Legal;
9386 
9387     // It does, so we can't tail call it.
9388     return outliner::InstrType::Illegal;
9389   }
9390 
9391   // Don't outline anything that modifies or reads from the stack pointer.
9392   //
9393   // FIXME: There are instructions which are being manually built without
9394   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
9395   // able to remove the extra checks once those are fixed up. For example,
9396   // sometimes we might get something like %rax = POP64r 1. This won't be
9397   // caught by modifiesRegister or readsRegister even though the instruction
9398   // really ought to be formed so that modifiesRegister/readsRegister would
9399   // catch it.
9400   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
9401       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
9402       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
9403     return outliner::InstrType::Illegal;
9404 
9405   // Outlined calls change the instruction pointer, so don't read from it.
9406   if (MI.readsRegister(X86::RIP, &RI) ||
9407       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
9408       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
9409     return outliner::InstrType::Illegal;
9410 
9411   // Positions can't safely be outlined.
9412   if (MI.isPosition())
9413     return outliner::InstrType::Illegal;
9414 
9415   // Make sure none of the operands of this instruction do anything tricky.
9416   for (const MachineOperand &MOP : MI.operands())
9417     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
9418         MOP.isTargetIndex())
9419       return outliner::InstrType::Illegal;
9420 
9421   return outliner::InstrType::Legal;
9422 }
9423 
9424 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
9425                                           MachineFunction &MF,
9426                                           const outliner::OutlinedFunction &OF)
9427                                           const {
9428   // If we're a tail call, we already have a return, so don't do anything.
9429   if (OF.FrameConstructionID == MachineOutlinerTailCall)
9430     return;
9431 
9432   // We're a normal call, so our sequence doesn't have a return instruction.
9433   // Add it in.
9434   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RET64));
9435   MBB.insert(MBB.end(), retq);
9436 }
9437 
9438 MachineBasicBlock::iterator
9439 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9440                                  MachineBasicBlock::iterator &It,
9441                                  MachineFunction &MF,
9442                                  outliner::Candidate &C) const {
9443   // Is it a tail call?
9444   if (C.CallConstructionID == MachineOutlinerTailCall) {
9445     // Yes, just insert a JMP.
9446     It = MBB.insert(It,
9447                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9448                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9449   } else {
9450     // No, insert a call.
9451     It = MBB.insert(It,
9452                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9453                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9454   }
9455 
9456   return It;
9457 }
9458 
9459 #define GET_INSTRINFO_HELPERS
9460 #include "X86GenInstrInfo.inc"
9461