1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 x87 FPU instruction set, defining the 10// instructions, and properties of the instructions which are needed for code 11// generation, machine code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// FPStack specific DAG Nodes. 17//===----------------------------------------------------------------------===// 18 19def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 20 SDTCisPtrTy<1>]>; 21def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 22 SDTCisPtrTy<1>]>; 23def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 24def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 25def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 26 27def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 28 29def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 30 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 31def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 32 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 33 SDNPMemOperand]>; 34def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 35 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 36def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 37 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 38 SDNPMemOperand]>; 39def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 40 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 41 SDNPMemOperand]>; 42def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 43def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 44 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 45def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 46 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 47 SDNPMemOperand]>; 48 49def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 50 (X86fst node:$val, node:$ptr), [{ 51 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 52}]>; 53def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 54 (X86fst node:$val, node:$ptr), [{ 55 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 56}]>; 57def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 58 (X86fst node:$val, node:$ptr), [{ 59 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 60}]>; 61 62def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 63 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 64}]>; 65def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 66 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 67}]>; 68def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 69 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 70}]>; 71 72def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 73 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 74}]>; 75def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 76 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 77}]>; 78def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 79 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 80}]>; 81 82def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{ 83 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 84}]>; 85 86def X86fist64 : PatFrag<(ops node:$val, node:$ptr), 87 (X86fist node:$val, node:$ptr), [{ 88 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 89}]>; 90 91def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 92 (X86fp_to_mem node:$val, node:$ptr), [{ 93 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 94}]>; 95def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 96 (X86fp_to_mem node:$val, node:$ptr), [{ 97 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 98}]>; 99def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 100 (X86fp_to_mem node:$val, node:$ptr), [{ 101 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 102}]>; 103 104//===----------------------------------------------------------------------===// 105// FPStack pattern fragments 106//===----------------------------------------------------------------------===// 107 108def fpimm0 : FPImmLeaf<fAny, [{ 109 return Imm.isExactlyValue(+0.0); 110}]>; 111 112def fpimmneg0 : FPImmLeaf<fAny, [{ 113 return Imm.isExactlyValue(-0.0); 114}]>; 115 116def fpimm1 : FPImmLeaf<fAny, [{ 117 return Imm.isExactlyValue(+1.0); 118}]>; 119 120def fpimmneg1 : FPImmLeaf<fAny, [{ 121 return Imm.isExactlyValue(-1.0); 122}]>; 123 124// Some 'special' instructions - expanded after instruction selection. 125// Clobbers EFLAGS due to OR instruction used internally. 126// FIXME: Can we model this in SelectionDAG? 127let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 128 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 129 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 130 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 131 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 132 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 133 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 134 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 135 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 136 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 137 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 138 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 139 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 140 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 141 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 142 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 143 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 144 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 145 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 146} 147 148// All FP Stack operations are represented with four instructions here. The 149// first three instructions, generated by the instruction selector, use "RFP32" 150// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 151// 64-bit or 80-bit floating point values. These sizes apply to the values, 152// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 153// copied to each other without losing information. These instructions are all 154// pseudo instructions and use the "_Fp" suffix. 155// In some cases there are additional variants with a mixture of different 156// register sizes. 157// The second instruction is defined with FPI, which is the actual instruction 158// emitted by the assembler. These use "RST" registers, although frequently 159// the actual register(s) used are implicit. These are always 80 bits. 160// The FP stackifier pass converts one to the other after register allocation 161// occurs. 162// 163// Note that the FpI instruction should have instruction selection info (e.g. 164// a pattern) and the FPI instruction should have emission info (e.g. opcode 165// encoding and asm printing info). 166 167// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 168// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 169// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 170// f80 instructions cannot use SSE and use neither of these. 171class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 172 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 173class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 174 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 175 176// Factoring for arithmetic. 177multiclass FPBinary_rr<SDNode OpNode> { 178// Register op register -> register 179// These are separated out because they have no reversed form. 180def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 181 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 182def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 183 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 184def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 185 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 186} 187// The FopST0 series are not included here because of the irregularities 188// in where the 'r' goes in assembly output. 189// These instructions cannot address 80-bit memory. 190multiclass FPBinary<SDNode OpNode, Format fp, string asmstring, 191 bit Forward = 1> { 192// ST(0) = ST(0) + [mem] 193def _Fp32m : FpIf32<(outs RFP32:$dst), 194 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 195 [!if(Forward, 196 (set RFP32:$dst, 197 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 198 (set RFP32:$dst, 199 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 200def _Fp64m : FpIf64<(outs RFP64:$dst), 201 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 202 [!if(Forward, 203 (set RFP64:$dst, 204 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 205 (set RFP64:$dst, 206 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 207def _Fp64m32: FpIf64<(outs RFP64:$dst), 208 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 209 [!if(Forward, 210 (set RFP64:$dst, 211 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 212 (set RFP64:$dst, 213 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 214def _Fp80m32: FpI_<(outs RFP80:$dst), 215 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 216 [!if(Forward, 217 (set RFP80:$dst, 218 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 219 (set RFP80:$dst, 220 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 221def _Fp80m64: FpI_<(outs RFP80:$dst), 222 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 223 [!if(Forward, 224 (set RFP80:$dst, 225 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 226 (set RFP80:$dst, 227 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 228let mayLoad = 1 in 229def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 230 !strconcat("f", asmstring, "{s}\t$src")>; 231let mayLoad = 1 in 232def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 233 !strconcat("f", asmstring, "{l}\t$src")>; 234// ST(0) = ST(0) + [memint] 235def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 236 OneArgFPRW, 237 [!if(Forward, 238 (set RFP32:$dst, 239 (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 240 (set RFP32:$dst, 241 (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 242def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 243 OneArgFPRW, 244 [!if(Forward, 245 (set RFP32:$dst, 246 (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 247 (set RFP32:$dst, 248 (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 249def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 250 OneArgFPRW, 251 [!if(Forward, 252 (set RFP64:$dst, 253 (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 254 (set RFP64:$dst, 255 (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 256def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 257 OneArgFPRW, 258 [!if(Forward, 259 (set RFP64:$dst, 260 (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 261 (set RFP64:$dst, 262 (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 263def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 264 OneArgFPRW, 265 [!if(Forward, 266 (set RFP80:$dst, 267 (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 268 (set RFP80:$dst, 269 (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 270def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 271 OneArgFPRW, 272 [!if(Forward, 273 (set RFP80:$dst, 274 (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 275 (set RFP80:$dst, 276 (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 277let mayLoad = 1 in 278def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 279 !strconcat("fi", asmstring, "{s}\t$src")>; 280let mayLoad = 1 in 281def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 282 !strconcat("fi", asmstring, "{l}\t$src")>; 283} 284 285let Defs = [FPSW], Uses = [FPCW] in { 286// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 287// resources. 288let hasNoSchedulingInfo = 1 in { 289defm ADD : FPBinary_rr<fadd>; 290defm SUB : FPBinary_rr<fsub>; 291defm MUL : FPBinary_rr<fmul>; 292defm DIV : FPBinary_rr<fdiv>; 293} 294 295// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 296let SchedRW = [WriteFAddLd] in { 297defm ADD : FPBinary<fadd, MRM0m, "add">; 298defm SUB : FPBinary<fsub, MRM4m, "sub">; 299defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>; 300} 301 302let SchedRW = [WriteFMulLd] in { 303defm MUL : FPBinary<fmul, MRM1m, "mul">; 304} 305 306let SchedRW = [WriteFDivLd] in { 307defm DIV : FPBinary<fdiv, MRM6m, "div">; 308defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>; 309} 310} // Defs = [FPSW] 311 312class FPST0rInst<Format fp, string asm> 313 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 314class FPrST0Inst<Format fp, string asm> 315 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 316class FPrST0PInst<Format fp, string asm> 317 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 318 319// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 320// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 321// we have to put some 'r's in and take them out of weird places. 322let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in { 323def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 324def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 325def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 326def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 327def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 328def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 329def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 330def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 331def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 332} // SchedRW 333let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in { 334def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 335def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 336} // SchedRW 337let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in { 338def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 339def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 340def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 341} // SchedRW 342let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in { 343def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 344def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 345def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 346def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 347def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 348def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 349} // SchedRW 350 351// Unary operations. 352multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 353def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 354 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 355def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 356 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 357def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 358 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 359def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 360} 361 362let Defs = [FPSW], Uses = [FPCW] in { 363 364let SchedRW = [WriteFSign] in { 365defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 366defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 367} 368 369let SchedRW = [WriteFSqrt80] in 370defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; 371 372let SchedRW = [WriteFCom] in { 373let hasSideEffects = 0 in { 374def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 375def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 376def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 377} // hasSideEffects 378 379def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 380} // SchedRW 381} // Defs = [FPSW] 382 383// Versions of FP instructions that take a single memory operand. Added for the 384// disassembler; remove as they are included with patterns elsewhere. 385let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in { 386def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 387def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 388 389def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 390def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 391 392def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 393def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 394 395def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 396def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 397} // SchedRW 398 399let SchedRW = [WriteMicrocoded] in { 400def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 401def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; 402 403def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; 404def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; 405def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 406 407def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 408def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 409} // SchedRW 410 411// Floating point cmovs. 412class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 413 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 414class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 415 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 416 417multiclass FPCMov<PatLeaf cc> { 418 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 419 CondMovFP, 420 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 421 cc, EFLAGS))]>; 422 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 423 CondMovFP, 424 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 425 cc, EFLAGS))]>; 426 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 427 CondMovFP, 428 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 429 cc, EFLAGS))]>, 430 Requires<[HasCMov]>; 431} 432 433let Defs = [FPSW] in { 434let SchedRW = [WriteFCMOV] in { 435let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 436defm CMOVB : FPCMov<X86_COND_B>; 437defm CMOVBE : FPCMov<X86_COND_BE>; 438defm CMOVE : FPCMov<X86_COND_E>; 439defm CMOVP : FPCMov<X86_COND_P>; 440defm CMOVNB : FPCMov<X86_COND_AE>; 441defm CMOVNBE: FPCMov<X86_COND_A>; 442defm CMOVNE : FPCMov<X86_COND_NE>; 443defm CMOVNP : FPCMov<X86_COND_NP>; 444} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 445 446let Predicates = [HasCMov] in { 447// These are not factored because there's no clean way to pass DA/DB. 448def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 449 "fcmovb\t{$op, %st|st, $op}">; 450def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 451 "fcmovbe\t{$op, %st|st, $op}">; 452def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 453 "fcmove\t{$op, %st|st, $op}">; 454def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 455 "fcmovu\t{$op, %st|st, $op}">; 456def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 457 "fcmovnb\t{$op, %st|st, $op}">; 458def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 459 "fcmovnbe\t{$op, %st|st, $op}">; 460def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 461 "fcmovne\t{$op, %st|st, $op}">; 462def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 463 "fcmovnu\t{$op, %st|st, $op}">; 464} // Predicates = [HasCMov] 465} // SchedRW 466 467// Floating point loads & stores. 468let SchedRW = [WriteLoad], Uses = [FPCW] in { 469let canFoldAsLoad = 1 in { 470def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 471 [(set RFP32:$dst, (loadf32 addr:$src))]>; 472def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 473 [(set RFP64:$dst, (loadf64 addr:$src))]>; 474def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 475 [(set RFP80:$dst, (loadf80 addr:$src))]>; 476} // canFoldAsLoad 477def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 478 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 479def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 480 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 481def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 482 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 483def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 484 [(set RFP32:$dst, (X86fild16 addr:$src))]>; 485def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 486 [(set RFP32:$dst, (X86fild32 addr:$src))]>; 487def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 488 [(set RFP32:$dst, (X86fild64 addr:$src))]>; 489def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 490 [(set RFP64:$dst, (X86fild16 addr:$src))]>; 491def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 492 [(set RFP64:$dst, (X86fild32 addr:$src))]>; 493def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 494 [(set RFP64:$dst, (X86fild64 addr:$src))]>; 495def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 496 [(set RFP80:$dst, (X86fild16 addr:$src))]>; 497def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 498 [(set RFP80:$dst, (X86fild32 addr:$src))]>; 499def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 500 [(set RFP80:$dst, (X86fild64 addr:$src))]>; 501} // SchedRW 502 503let SchedRW = [WriteStore], Uses = [FPCW] in { 504def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 505 [(store RFP32:$src, addr:$op)]>; 506def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 507 [(truncstoref32 RFP64:$src, addr:$op)]>; 508def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 509 [(store RFP64:$src, addr:$op)]>; 510def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 511 [(truncstoref32 RFP80:$src, addr:$op)]>; 512def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 513 [(truncstoref64 RFP80:$src, addr:$op)]>; 514// FST does not support 80-bit memory target; FSTP must be used. 515 516let mayStore = 1, hasSideEffects = 0 in { 517def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 518def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 519def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 520def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 521def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 522} // mayStore 523 524def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 525 [(store RFP80:$src, addr:$op)]>; 526 527let mayStore = 1, hasSideEffects = 0 in { 528def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 529def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 530def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 531def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 532def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 533def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 534def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 535def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 536def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 537} // mayStore 538} // SchedRW, Uses = [FPCW] 539 540let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 541def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 542def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 543def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 544def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 545def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 546def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 547} 548let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 549def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 550def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 551def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 552def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 553def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 554def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 555def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 556def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 557def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 558def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 559} 560 561// FISTTP requires SSE3 even though it's a FPStack op. 562let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 563def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 564 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 565def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 566 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 567def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 568 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 569def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 570 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 571def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 572 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 573def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 574 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 575def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 576 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 577def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 578 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 579def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 580 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 581} // Predicates = [HasSSE3] 582 583let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 584def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 585def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 586def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 587} 588 589// FP Stack manipulation instructions. 590let SchedRW = [WriteMove], Uses = [FPCW] in { 591def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 592def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 593def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 594def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 595} 596 597// Floating point constant loads. 598let SchedRW = [WriteZero], Uses = [FPCW] in { 599def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 600 [(set RFP32:$dst, fpimm0)]>; 601def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 602 [(set RFP32:$dst, fpimm1)]>; 603def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 604 [(set RFP64:$dst, fpimm0)]>; 605def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 606 [(set RFP64:$dst, fpimm1)]>; 607def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 608 [(set RFP80:$dst, fpimm0)]>; 609def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 610 [(set RFP80:$dst, fpimm1)]>; 611} 612 613let SchedRW = [WriteFLD0], Uses = [FPCW] in 614def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 615 616let SchedRW = [WriteFLD1], Uses = [FPCW] in 617def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 618 619let SchedRW = [WriteFLDC], Uses = [FPCW] in { 620def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 621def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 622def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 623def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 624def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 625} // SchedRW 626 627// Floating point compares. 628let SchedRW = [WriteFCom], Uses = [FPCW] in { 629def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 630 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 631def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 632 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 633def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 634 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 635} // SchedRW 636} // Defs = [FPSW] 637 638let SchedRW = [WriteFCom] in { 639// CC = ST(0) cmp ST(i) 640let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 641def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 642 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>, 643 Requires<[FPStackf32, HasCMov]>; 644def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 645 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>, 646 Requires<[FPStackf64, HasCMov]>; 647def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 648 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>, 649 Requires<[HasCMov]>; 650} 651 652let Defs = [FPSW], Uses = [ST0, FPCW] in { 653def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 654 (outs), (ins RSTi:$reg), "fucom\t$reg">; 655def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 656 (outs), (ins RSTi:$reg), "fucomp\t$reg">; 657def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 658 (outs), (ins), "fucompp">; 659} 660 661let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 662def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 663 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 664def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 665 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 666 667def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 668 "fcomi\t{$reg, %st|st, $reg}">; 669def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 670 "fcompi\t{$reg, %st|st, $reg}">; 671} 672} // SchedRW 673 674// Floating point flag ops. 675let SchedRW = [WriteALU] in { 676let Defs = [AX], Uses = [FPSW] in 677def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 678 (outs), (ins), "fnstsw\t{%ax|ax}", 679 [(set AX, (X86fp_stsw FPSW))]>; 680let Defs = [FPSW], Uses = [FPCW] in 681def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 682 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 683 [(X86fp_cwd_get16 addr:$dst)]>; 684} // SchedRW 685let Defs = [FPSW,FPCW], mayLoad = 1 in 686def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 687 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, 688 Sched<[WriteLoad]>; 689 690// FPU control instructions 691let SchedRW = [WriteMicrocoded] in { 692let Defs = [FPSW] in { 693def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 694def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 695def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 696 697// Clear exceptions 698def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 699} // Defs = [FPSW] 700} // SchedRW 701 702// Operand-less floating-point instructions for the disassembler. 703def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 704 705let SchedRW = [WriteMicrocoded] in { 706let Defs = [FPSW] in { 707def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 708def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 709def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 710def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 711def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 712def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 713def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 714def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 715def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 716def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 717def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 718def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 719def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>; 720def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>; 721def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 722def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 723def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 724def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 725} // Defs = [FPSW] 726 727def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 728 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, 729 Requires<[HasFXSR]>; 730def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 731 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 732 TB, Requires<[HasFXSR, In64BitMode]>; 733def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 734 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 735 TB, Requires<[HasFXSR]>; 736def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 737 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 738 TB, Requires<[HasFXSR, In64BitMode]>; 739} // SchedRW 740 741//===----------------------------------------------------------------------===// 742// Non-Instruction Patterns 743//===----------------------------------------------------------------------===// 744 745// Required for RET of f32 / f64 / f80 values. 746def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 747def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 748def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 749 750// Required for CALL which return f32 / f64 / f80 values. 751def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 752def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 753def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 754def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 755def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 756def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 757 758// Floating point constant -0.0 and -1.0 759def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 760def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 761def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 762def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 763def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 764def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 765 766// Used to conv. i64 to f64 since there isn't a SSE version. 767def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>; 768 769// Used to conv. between f80 and i64 for i64 atomic loads. 770def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>; 771def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>; 772 773// FP extensions map onto simple pseudo-value conversions if they are to/from 774// the FP stack. 775def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 776 Requires<[FPStackf32]>; 777def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 778 Requires<[FPStackf32]>; 779def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 780 Requires<[FPStackf64]>; 781 782// FP truncations map onto simple pseudo-value conversions if they are to/from 783// the FP stack. We have validated that only value-preserving truncations make 784// it through isel. 785def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 786 Requires<[FPStackf32]>; 787def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 788 Requires<[FPStackf32]>; 789def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 790 Requires<[FPStackf64]>; 791