1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 x87 FPU instruction set, defining the 10// instructions, and properties of the instructions which are needed for code 11// generation, machine code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// FPStack specific DAG Nodes. 17//===----------------------------------------------------------------------===// 18 19def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 20 SDTCisPtrTy<1>]>; 21def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 22 SDTCisPtrTy<1>]>; 23def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 24def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 25def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 26 27def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 28 29def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 30 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 31def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 32 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 33def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 34 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 35def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 36 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 37def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 38def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 39 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 40def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 41 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 42 SDNPMemOperand]>; 43 44def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 45 (X86fst node:$val, node:$ptr), [{ 46 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 47}]>; 48def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 49 (X86fst node:$val, node:$ptr), [{ 50 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 51}]>; 52def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 53 (X86fst node:$val, node:$ptr), [{ 54 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 55}]>; 56 57def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 58 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 59}]>; 60def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 61 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 62}]>; 63def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 64 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 65}]>; 66 67def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 68 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 69}]>; 70def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 71 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 72}]>; 73def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 74 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 75}]>; 76 77def X86fist64 : PatFrag<(ops node:$val, node:$ptr), 78 (X86fist node:$val, node:$ptr), [{ 79 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 80}]>; 81 82def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 83 (X86fp_to_mem node:$val, node:$ptr), [{ 84 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 85}]>; 86def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 87 (X86fp_to_mem node:$val, node:$ptr), [{ 88 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 89}]>; 90def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 91 (X86fp_to_mem node:$val, node:$ptr), [{ 92 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 93}]>; 94 95//===----------------------------------------------------------------------===// 96// FPStack pattern fragments 97//===----------------------------------------------------------------------===// 98 99def fpimm0 : FPImmLeaf<fAny, [{ 100 return Imm.isExactlyValue(+0.0); 101}]>; 102 103def fpimmneg0 : FPImmLeaf<fAny, [{ 104 return Imm.isExactlyValue(-0.0); 105}]>; 106 107def fpimm1 : FPImmLeaf<fAny, [{ 108 return Imm.isExactlyValue(+1.0); 109}]>; 110 111def fpimmneg1 : FPImmLeaf<fAny, [{ 112 return Imm.isExactlyValue(-1.0); 113}]>; 114 115// Some 'special' instructions - expanded after instruction selection. 116// Clobbers EFLAGS due to OR instruction used internally. 117// FIXME: Can we model this in SelectionDAG? 118let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 119 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 120 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 121 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 122 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 123 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 124 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 125 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 126 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 127 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 128 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 129 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 130 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 131 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 132 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 133 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 134 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 135 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 136 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 137} 138 139// All FP Stack operations are represented with four instructions here. The 140// first three instructions, generated by the instruction selector, use "RFP32" 141// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 142// 64-bit or 80-bit floating point values. These sizes apply to the values, 143// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 144// copied to each other without losing information. These instructions are all 145// pseudo instructions and use the "_Fp" suffix. 146// In some cases there are additional variants with a mixture of different 147// register sizes. 148// The second instruction is defined with FPI, which is the actual instruction 149// emitted by the assembler. These use "RST" registers, although frequently 150// the actual register(s) used are implicit. These are always 80 bits. 151// The FP stackifier pass converts one to the other after register allocation 152// occurs. 153// 154// Note that the FpI instruction should have instruction selection info (e.g. 155// a pattern) and the FPI instruction should have emission info (e.g. opcode 156// encoding and asm printing info). 157 158// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 159// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 160// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 161// f80 instructions cannot use SSE and use neither of these. 162class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 163 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 164class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 165 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 166 167// Factoring for arithmetic. 168multiclass FPBinary_rr<SDNode OpNode> { 169// Register op register -> register 170// These are separated out because they have no reversed form. 171def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 172 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 173def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 174 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 175def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 176 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 177} 178// The FopST0 series are not included here because of the irregularities 179// in where the 'r' goes in assembly output. 180// These instructions cannot address 80-bit memory. 181multiclass FPBinary<SDNode OpNode, Format fp, string asmstring, 182 bit Forward = 1> { 183// ST(0) = ST(0) + [mem] 184def _Fp32m : FpIf32<(outs RFP32:$dst), 185 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 186 [!if(Forward, 187 (set RFP32:$dst, 188 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 189 (set RFP32:$dst, 190 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 191def _Fp64m : FpIf64<(outs RFP64:$dst), 192 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 193 [!if(Forward, 194 (set RFP64:$dst, 195 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 196 (set RFP64:$dst, 197 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 198def _Fp64m32: FpIf64<(outs RFP64:$dst), 199 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 200 [!if(Forward, 201 (set RFP64:$dst, 202 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 203 (set RFP64:$dst, 204 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 205def _Fp80m32: FpI_<(outs RFP80:$dst), 206 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 207 [!if(Forward, 208 (set RFP80:$dst, 209 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 210 (set RFP80:$dst, 211 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 212def _Fp80m64: FpI_<(outs RFP80:$dst), 213 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 214 [!if(Forward, 215 (set RFP80:$dst, 216 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 217 (set RFP80:$dst, 218 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 219let mayLoad = 1 in 220def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 221 !strconcat("f", asmstring, "{s}\t$src")>; 222let mayLoad = 1 in 223def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 224 !strconcat("f", asmstring, "{l}\t$src")>; 225// ST(0) = ST(0) + [memint] 226def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 227 OneArgFPRW, 228 [!if(Forward, 229 (set RFP32:$dst, 230 (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 231 (set RFP32:$dst, 232 (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 233def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 234 OneArgFPRW, 235 [!if(Forward, 236 (set RFP32:$dst, 237 (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 238 (set RFP32:$dst, 239 (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 240def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 241 OneArgFPRW, 242 [!if(Forward, 243 (set RFP64:$dst, 244 (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 245 (set RFP64:$dst, 246 (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 247def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 248 OneArgFPRW, 249 [!if(Forward, 250 (set RFP64:$dst, 251 (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 252 (set RFP64:$dst, 253 (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 254def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 255 OneArgFPRW, 256 [!if(Forward, 257 (set RFP80:$dst, 258 (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 259 (set RFP80:$dst, 260 (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 261def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 262 OneArgFPRW, 263 [!if(Forward, 264 (set RFP80:$dst, 265 (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 266 (set RFP80:$dst, 267 (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 268let mayLoad = 1 in 269def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 270 !strconcat("fi", asmstring, "{s}\t$src")>; 271let mayLoad = 1 in 272def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 273 !strconcat("fi", asmstring, "{l}\t$src")>; 274} 275 276let Uses = [FPCW], mayRaiseFPException = 1 in { 277// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 278// resources. 279let hasNoSchedulingInfo = 1 in { 280defm ADD : FPBinary_rr<any_fadd>; 281defm SUB : FPBinary_rr<any_fsub>; 282defm MUL : FPBinary_rr<any_fmul>; 283defm DIV : FPBinary_rr<any_fdiv>; 284} 285 286// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 287let SchedRW = [WriteFAddLd] in { 288defm ADD : FPBinary<any_fadd, MRM0m, "add">; 289defm SUB : FPBinary<any_fsub, MRM4m, "sub">; 290defm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>; 291} 292 293let SchedRW = [WriteFMulLd] in { 294defm MUL : FPBinary<any_fmul, MRM1m, "mul">; 295} 296 297let SchedRW = [WriteFDivLd] in { 298defm DIV : FPBinary<any_fdiv, MRM6m, "div">; 299defm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>; 300} 301} // Uses = [FPCW], mayRaiseFPException = 1 302 303class FPST0rInst<Format fp, string asm> 304 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 305class FPrST0Inst<Format fp, string asm> 306 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 307class FPrST0PInst<Format fp, string asm> 308 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 309 310// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 311// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 312// we have to put some 'r's in and take them out of weird places. 313let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in { 314def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 315def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 316def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 317def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 318def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 319def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 320def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 321def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 322def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 323} // SchedRW 324let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in { 325def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 326def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 327} // SchedRW 328let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in { 329def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 330def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 331def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 332} // SchedRW 333let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in { 334def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 335def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 336def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 337def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 338def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 339def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 340} // SchedRW 341 342// Unary operations. 343multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 344def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 345 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 346def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 347 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 348def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 349 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 350def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 351} 352 353let SchedRW = [WriteFSign] in { 354defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 355defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 356} 357 358let Uses = [FPCW], mayRaiseFPException = 1 in { 359let SchedRW = [WriteFSqrt80] in 360defm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">; 361 362let SchedRW = [WriteFCom] in { 363let hasSideEffects = 0 in { 364def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 365def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 366def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 367} // hasSideEffects 368 369def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 370} // SchedRW 371} // Uses = [FPCW], mayRaiseFPException = 1 372 373// Versions of FP instructions that take a single memory operand. Added for the 374// disassembler; remove as they are included with patterns elsewhere. 375let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1 in { 376def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 377def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 378 379def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 380def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 381 382def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 383def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 384 385def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 386def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 387} // SchedRW 388 389let SchedRW = [WriteMicrocoded] in { 390let Defs = [FPSW, FPCW] in { 391def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 392def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; 393} 394 395let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW] in { 396def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; 397def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; 398} 399 400let Uses = [FPSW] in 401def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 402 403def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 404let Uses = [FPCW] ,mayRaiseFPException = 1 in 405def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 406} // SchedRW 407 408// Floating point cmovs. 409class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 410 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 411class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 412 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 413 414multiclass FPCMov<PatLeaf cc> { 415 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 416 CondMovFP, 417 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 418 cc, EFLAGS))]>; 419 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 420 CondMovFP, 421 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 422 cc, EFLAGS))]>; 423 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 424 CondMovFP, 425 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 426 cc, EFLAGS))]>, 427 Requires<[HasCMov]>; 428} 429 430let SchedRW = [WriteFCMOV] in { 431let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 432defm CMOVB : FPCMov<X86_COND_B>; 433defm CMOVBE : FPCMov<X86_COND_BE>; 434defm CMOVE : FPCMov<X86_COND_E>; 435defm CMOVP : FPCMov<X86_COND_P>; 436defm CMOVNB : FPCMov<X86_COND_AE>; 437defm CMOVNBE: FPCMov<X86_COND_A>; 438defm CMOVNE : FPCMov<X86_COND_NE>; 439defm CMOVNP : FPCMov<X86_COND_NP>; 440} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 441 442let Predicates = [HasCMov] in { 443// These are not factored because there's no clean way to pass DA/DB. 444def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 445 "fcmovb\t{$op, %st|st, $op}">; 446def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 447 "fcmovbe\t{$op, %st|st, $op}">; 448def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 449 "fcmove\t{$op, %st|st, $op}">; 450def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 451 "fcmovu\t{$op, %st|st, $op}">; 452def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 453 "fcmovnb\t{$op, %st|st, $op}">; 454def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 455 "fcmovnbe\t{$op, %st|st, $op}">; 456def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 457 "fcmovne\t{$op, %st|st, $op}">; 458def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 459 "fcmovnu\t{$op, %st|st, $op}">; 460} // Predicates = [HasCMov] 461} // SchedRW 462 463let mayRaiseFPException = 1 in { 464// Floating point loads & stores. 465let SchedRW = [WriteLoad], Uses = [FPCW] in { 466let canFoldAsLoad = 1 in { 467def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 468 [(set RFP32:$dst, (loadf32 addr:$src))]>; 469def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 470 [(set RFP64:$dst, (loadf64 addr:$src))]>; 471def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 472 [(set RFP80:$dst, (loadf80 addr:$src))]>; 473} // canFoldAsLoad 474def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 475 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 476def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 477 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 478def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 479 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 480let mayRaiseFPException = 0 in { 481def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 482 [(set RFP32:$dst, (X86fild16 addr:$src))]>; 483def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 484 [(set RFP32:$dst, (X86fild32 addr:$src))]>; 485def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 486 [(set RFP32:$dst, (X86fild64 addr:$src))]>; 487def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 488 [(set RFP64:$dst, (X86fild16 addr:$src))]>; 489def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 490 [(set RFP64:$dst, (X86fild32 addr:$src))]>; 491def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 492 [(set RFP64:$dst, (X86fild64 addr:$src))]>; 493def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 494 [(set RFP80:$dst, (X86fild16 addr:$src))]>; 495def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 496 [(set RFP80:$dst, (X86fild32 addr:$src))]>; 497def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 498 [(set RFP80:$dst, (X86fild64 addr:$src))]>; 499} // mayRaiseFPException = 0 500} // SchedRW 501 502let SchedRW = [WriteStore], Uses = [FPCW] in { 503def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 504 [(store RFP32:$src, addr:$op)]>; 505def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 506 [(truncstoref32 RFP64:$src, addr:$op)]>; 507def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 508 [(store RFP64:$src, addr:$op)]>; 509def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 510 [(truncstoref32 RFP80:$src, addr:$op)]>; 511def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 512 [(truncstoref64 RFP80:$src, addr:$op)]>; 513// FST does not support 80-bit memory target; FSTP must be used. 514 515let mayStore = 1, hasSideEffects = 0 in { 516def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 517def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 518def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 519def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 520def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 521} // mayStore 522 523def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 524 [(store RFP80:$src, addr:$op)]>; 525 526let mayStore = 1, hasSideEffects = 0 in { 527def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 528def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 529def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 530def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 531def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 532def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 533def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 534def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 535def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 536} // mayStore 537} // SchedRW, Uses = [FPCW] 538 539let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 540def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 541def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 542def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 543let mayRaiseFPException = 0 in { 544def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 545def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 546def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 547} 548} 549let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 550def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 551def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 552def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 553def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 554def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 555def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 556def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 557def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 558def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 559def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 560} 561 562// FISTTP requires SSE3 even though it's a FPStack op. 563let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 564def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 565 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 566def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 567 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 568def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 569 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 570def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 571 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 572def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 573 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 574def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 575 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 576def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 577 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 578def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 579 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 580def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 581 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 582} // Predicates = [HasSSE3] 583 584let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 585def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 586def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 587def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 588} 589 590// FP Stack manipulation instructions. 591let SchedRW = [WriteMove], Uses = [FPCW] in { 592def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 593def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 594def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 595let mayRaiseFPException = 0 in 596def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 597} 598 599// Floating point constant loads. 600let SchedRW = [WriteZero], Uses = [FPCW] in { 601def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 602 [(set RFP32:$dst, fpimm0)]>; 603def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 604 [(set RFP32:$dst, fpimm1)]>; 605def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 606 [(set RFP64:$dst, fpimm0)]>; 607def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 608 [(set RFP64:$dst, fpimm1)]>; 609def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 610 [(set RFP80:$dst, fpimm0)]>; 611def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 612 [(set RFP80:$dst, fpimm1)]>; 613} 614 615let SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in 616def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 617 618let SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in 619def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 620 621let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in { 622def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 623def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 624def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 625def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 626def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 627} // SchedRW 628 629// Floating point compares. 630let SchedRW = [WriteFCom], Uses = [FPCW] in { 631def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 632 [(set FPSW, (trunc (X86any_fcmp RFP32:$lhs, RFP32:$rhs)))]>; 633def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 634 [(set FPSW, (trunc (X86any_fcmp RFP64:$lhs, RFP64:$rhs)))]>; 635def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 636 [(set FPSW, (trunc (X86any_fcmp RFP80:$lhs, RFP80:$rhs)))]>; 637def COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 638 [(set FPSW, (trunc (X86strict_fcmps RFP32:$lhs, RFP32:$rhs)))]>; 639def COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 640 [(set FPSW, (trunc (X86strict_fcmps RFP64:$lhs, RFP64:$rhs)))]>; 641def COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 642 [(set FPSW, (trunc (X86strict_fcmps RFP80:$lhs, RFP80:$rhs)))]>; 643} // SchedRW 644} // mayRaiseFPException = 1 645 646let SchedRW = [WriteFCom], mayRaiseFPException = 1 in { 647// CC = ST(0) cmp ST(i) 648let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 649def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 650 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>, 651 Requires<[FPStackf32, HasCMov]>; 652def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 653 [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>, 654 Requires<[FPStackf64, HasCMov]>; 655def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 656 [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>, 657 Requires<[HasCMov]>; 658def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 659 [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>, 660 Requires<[FPStackf32, HasCMov]>; 661def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 662 [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>, 663 Requires<[FPStackf64, HasCMov]>; 664def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 665 [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>, 666 Requires<[HasCMov]>; 667} 668 669let Uses = [ST0, FPCW] in { 670def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 671 (outs), (ins RSTi:$reg), "fucom\t$reg">; 672def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 673 (outs), (ins RSTi:$reg), "fucomp\t$reg">; 674def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 675 (outs), (ins), "fucompp">; 676} 677 678let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 679def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 680 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 681def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 682 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 683 684def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 685 "fcomi\t{$reg, %st|st, $reg}">; 686def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 687 "fcompi\t{$reg, %st|st, $reg}">; 688} 689} // SchedRW 690 691// Floating point flag ops. 692let SchedRW = [WriteALU] in { 693let Defs = [AX, FPSW], Uses = [FPSW] in 694def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 695 (outs), (ins), "fnstsw\t{%ax|ax}", 696 [(set AX, (X86fp_stsw FPSW))]>; 697let Defs = [FPSW], Uses = [FPCW] in 698def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 699 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 700 [(X86fp_cwd_get16 addr:$dst)]>; 701} // SchedRW 702let Defs = [FPSW,FPCW], mayLoad = 1 in 703def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 704 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, 705 Sched<[WriteLoad]>; 706 707// FPU control instructions 708let SchedRW = [WriteMicrocoded] in { 709def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 710def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 711 712let Defs = [FPSW, FPCW] in 713def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 714// Clear exceptions 715let Defs = [FPSW] in 716def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 717} // SchedRW 718 719// Operand-less floating-point instructions for the disassembler. 720let Defs = [FPSW] in 721def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 722 723let SchedRW = [WriteMicrocoded] in { 724let Defs = [FPSW] in { 725def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 726def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 727def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 728def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 729let Uses = [FPCW], mayRaiseFPException = 1 in { 730def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 731def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 732def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 733def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 734def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 735def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 736def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 737def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 738def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>; 739def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>; 740def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 741def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 742def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 743def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 744} // Uses = [FPCW], mayRaiseFPException = 1 745} // Defs = [FPSW] 746 747let Uses = [FPSW, FPCW] in { 748def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 749 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, 750 Requires<[HasFXSR]>; 751def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 752 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 753 TB, Requires<[HasFXSR, In64BitMode]>; 754} // Uses = [FPSW, FPCW] 755 756let Defs = [FPSW, FPCW] in { 757def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 758 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 759 TB, Requires<[HasFXSR]>; 760def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 761 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 762 TB, Requires<[HasFXSR, In64BitMode]>; 763} // Defs = [FPSW, FPCW] 764} // SchedRW 765 766//===----------------------------------------------------------------------===// 767// Non-Instruction Patterns 768//===----------------------------------------------------------------------===// 769 770// Required for RET of f32 / f64 / f80 values. 771def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 772def : Pat<(X86fldf32 addr:$src), (LD_Fp32m64 addr:$src)>; 773def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 774def : Pat<(X86fldf32 addr:$src), (LD_Fp32m80 addr:$src)>; 775def : Pat<(X86fldf64 addr:$src), (LD_Fp64m80 addr:$src)>; 776def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 777 778// Required for CALL which return f32 / f64 / f80 values. 779def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 780def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 781def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 782def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 783def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 784def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 785 786// Floating point constant -0.0 and -1.0 787def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 788def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 789def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 790def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 791def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 792def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 793 794// Used to conv. between f80 and i64 for i64 atomic loads. 795def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>; 796 797// FP extensions map onto simple pseudo-value conversions if they are to/from 798// the FP stack. 799def : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 800 Requires<[FPStackf32]>; 801def : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 802 Requires<[FPStackf32]>; 803def : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 804 Requires<[FPStackf64]>; 805 806// FP truncations map onto simple pseudo-value conversions if they are to/from 807// the FP stack. We have validated that only value-preserving truncations make 808// it through isel. 809def : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 810 Requires<[FPStackf32]>; 811def : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 812 Requires<[FPStackf32]>; 813def : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 814 Requires<[FPStackf64]>; 815