1//==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 x87 FPU instruction set, defining the 11// instructions, and properties of the instructions which are needed for code 12// generation, machine code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// FPStack specific DAG Nodes. 18//===----------------------------------------------------------------------===// 19 20def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, 21 SDTCisVT<1, f80>]>; 22def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, 23 SDTCisPtrTy<1>, 24 SDTCisVT<2, OtherVT>]>; 25def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, 26 SDTCisPtrTy<1>, 27 SDTCisVT<2, OtherVT>]>; 28def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, 29 SDTCisVT<2, OtherVT>]>; 30def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 31 32def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 33 34def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 35 [SDNPHasChain, SDNPMayLoad]>; 36def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 37 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>; 38def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 39 [SDNPHasChain, SDNPMayLoad]>; 40def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 41 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>; 42def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, 43 [SDNPHasChain, SDNPMayStore]>; 44def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, 45 [SDNPHasChain, SDNPMayStore]>; 46def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, 47 [SDNPHasChain, SDNPMayStore]>; 48def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 49 [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>; 50 51//===----------------------------------------------------------------------===// 52// FPStack pattern fragments 53//===----------------------------------------------------------------------===// 54 55def fpimm0 : PatLeaf<(fpimm), [{ 56 return N->isExactlyValue(+0.0); 57}]>; 58 59def fpimmneg0 : PatLeaf<(fpimm), [{ 60 return N->isExactlyValue(-0.0); 61}]>; 62 63def fpimm1 : PatLeaf<(fpimm), [{ 64 return N->isExactlyValue(+1.0); 65}]>; 66 67def fpimmneg1 : PatLeaf<(fpimm), [{ 68 return N->isExactlyValue(-1.0); 69}]>; 70 71// Some 'special' instructions 72let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo, 74 (outs), (ins i16mem:$dst, RFP32:$src), 75 "##FP32_TO_INT16_IN_MEM PSEUDO!", 76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo, 78 (outs), (ins i32mem:$dst, RFP32:$src), 79 "##FP32_TO_INT32_IN_MEM PSEUDO!", 80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo, 82 (outs), (ins i64mem:$dst, RFP32:$src), 83 "##FP32_TO_INT64_IN_MEM PSEUDO!", 84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo, 86 (outs), (ins i16mem:$dst, RFP64:$src), 87 "##FP64_TO_INT16_IN_MEM PSEUDO!", 88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo, 90 (outs), (ins i32mem:$dst, RFP64:$src), 91 "##FP64_TO_INT32_IN_MEM PSEUDO!", 92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo, 94 (outs), (ins i64mem:$dst, RFP64:$src), 95 "##FP64_TO_INT64_IN_MEM PSEUDO!", 96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 97 def FP80_TO_INT16_IN_MEM : I<0, Pseudo, 98 (outs), (ins i16mem:$dst, RFP80:$src), 99 "##FP80_TO_INT16_IN_MEM PSEUDO!", 100 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 101 def FP80_TO_INT32_IN_MEM : I<0, Pseudo, 102 (outs), (ins i32mem:$dst, RFP80:$src), 103 "##FP80_TO_INT32_IN_MEM PSEUDO!", 104 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 105 def FP80_TO_INT64_IN_MEM : I<0, Pseudo, 106 (outs), (ins i64mem:$dst, RFP80:$src), 107 "##FP80_TO_INT64_IN_MEM PSEUDO!", 108 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 109} 110 111let isTerminator = 1 in 112 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in 113 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>; 114 115// All FP Stack operations are represented with four instructions here. The 116// first three instructions, generated by the instruction selector, use "RFP32" 117// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 118// 64-bit or 80-bit floating point values. These sizes apply to the values, 119// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 120// copied to each other without losing information. These instructions are all 121// pseudo instructions and use the "_Fp" suffix. 122// In some cases there are additional variants with a mixture of different 123// register sizes. 124// The second instruction is defined with FPI, which is the actual instruction 125// emitted by the assembler. These use "RST" registers, although frequently 126// the actual register(s) used are implicit. These are always 80 bits. 127// The FP stackifier pass converts one to the other after register allocation 128// occurs. 129// 130// Note that the FpI instruction should have instruction selection info (e.g. 131// a pattern) and the FPI instruction should have emission info (e.g. opcode 132// encoding and asm printing info). 133 134// Pseudo Instructions for FP stack return values. 135def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0) 136def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0) 137def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0) 138 139// FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when 140// there are two values live out on the stack from a call or inlineasm. This 141// magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and 142// then FpGET_ST0*. In addition, it is invalid for any FP-using operations to 143// occur between them. 144def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1) 145def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1) 146def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1) 147 148let Defs = [ST0] in { 149def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR 150def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR 151def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR 152} 153 154let Defs = [ST1] in { 155def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR 156def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR 157def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR 158} 159 160// FpIf32, FpIf64 - Floating Point Psuedo Instruction template. 161// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 162// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 163// f80 instructions cannot use SSE and use neither of these. 164class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 165 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 166class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 167 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 168 169// Register copies. Just copies, the shortening ones do not truncate. 170let neverHasSideEffects = 1 in { 171 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>; 172 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>; 173 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>; 174 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>; 175 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>; 176 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>; 177 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>; 178 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>; 179 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>; 180} 181 182// Factoring for arithmetic. 183multiclass FPBinary_rr<SDNode OpNode> { 184// Register op register -> register 185// These are separated out because they have no reversed form. 186def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 187 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 188def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 189 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 190def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 191 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 192} 193// The FopST0 series are not included here because of the irregularities 194// in where the 'r' goes in assembly output. 195// These instructions cannot address 80-bit memory. 196multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> { 197// ST(0) = ST(0) + [mem] 198def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 199 [(set RFP32:$dst, 200 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; 201def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 202 [(set RFP64:$dst, 203 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; 204def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 205 [(set RFP64:$dst, 206 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>; 207def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 208 [(set RFP80:$dst, 209 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>; 210def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 211 [(set RFP80:$dst, 212 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>; 213def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 214 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; } 215def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 216 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; } 217// ST(0) = ST(0) + [memint] 218def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW, 219 [(set RFP32:$dst, (OpNode RFP32:$src1, 220 (X86fild addr:$src2, i16)))]>; 221def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW, 222 [(set RFP32:$dst, (OpNode RFP32:$src1, 223 (X86fild addr:$src2, i32)))]>; 224def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW, 225 [(set RFP64:$dst, (OpNode RFP64:$src1, 226 (X86fild addr:$src2, i16)))]>; 227def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW, 228 [(set RFP64:$dst, (OpNode RFP64:$src1, 229 (X86fild addr:$src2, i32)))]>; 230def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW, 231 [(set RFP80:$dst, (OpNode RFP80:$src1, 232 (X86fild addr:$src2, i16)))]>; 233def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW, 234 [(set RFP80:$dst, (OpNode RFP80:$src1, 235 (X86fild addr:$src2, i32)))]>; 236def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 237 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; } 238def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 239 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; } 240} 241 242defm ADD : FPBinary_rr<fadd>; 243defm SUB : FPBinary_rr<fsub>; 244defm MUL : FPBinary_rr<fmul>; 245defm DIV : FPBinary_rr<fdiv>; 246defm ADD : FPBinary<fadd, MRM0m, "add">; 247defm SUB : FPBinary<fsub, MRM4m, "sub">; 248defm SUBR: FPBinary<fsub ,MRM5m, "subr">; 249defm MUL : FPBinary<fmul, MRM1m, "mul">; 250defm DIV : FPBinary<fdiv, MRM6m, "div">; 251defm DIVR: FPBinary<fdiv, MRM7m, "divr">; 252 253class FPST0rInst<bits<8> o, string asm> 254 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8; 255class FPrST0Inst<bits<8> o, string asm> 256 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC; 257class FPrST0PInst<bits<8> o, string asm> 258 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE; 259 260// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 261// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 262// we have to put some 'r's in and take them out of weird places. 263def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">; 264def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">; 265def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">; 266def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">; 267def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">; 268def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">; 269def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">; 270def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">; 271def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">; 272def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">; 273def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">; 274def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">; 275def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">; 276def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">; 277def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">; 278def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">; 279def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">; 280def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">; 281 282// Unary operations. 283multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> { 284def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 285 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 286def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 287 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 288def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 289 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 290def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9; 291} 292 293defm CHS : FPUnary<fneg, 0xE0, "fchs">; 294defm ABS : FPUnary<fabs, 0xE1, "fabs">; 295defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">; 296defm SIN : FPUnary<fsin, 0xFE, "fsin">; 297defm COS : FPUnary<fcos, 0xFF, "fcos">; 298 299let neverHasSideEffects = 1 in { 300def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 301def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 302def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 303} 304def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9; 305 306// Floating point cmovs. 307multiclass FPCMov<PatLeaf cc> { 308 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 309 CondMovFP, 310 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 311 cc, EFLAGS))]>; 312 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 313 CondMovFP, 314 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 315 cc, EFLAGS))]>; 316 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 317 CondMovFP, 318 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 319 cc, EFLAGS))]>; 320} 321let Uses = [EFLAGS], isTwoAddress = 1 in { 322defm CMOVB : FPCMov<X86_COND_B>; 323defm CMOVBE : FPCMov<X86_COND_BE>; 324defm CMOVE : FPCMov<X86_COND_E>; 325defm CMOVP : FPCMov<X86_COND_P>; 326defm CMOVNB : FPCMov<X86_COND_AE>; 327defm CMOVNBE: FPCMov<X86_COND_A>; 328defm CMOVNE : FPCMov<X86_COND_NE>; 329defm CMOVNP : FPCMov<X86_COND_NP>; 330} 331 332// These are not factored because there's no clean way to pass DA/DB. 333def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), 334 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA; 335def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), 336 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA; 337def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), 338 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA; 339def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), 340 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA; 341def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), 342 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB; 343def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), 344 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB; 345def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), 346 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB; 347def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), 348 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB; 349 350// Floating point loads & stores. 351let canFoldAsLoad = 1 in { 352def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 353 [(set RFP32:$dst, (loadf32 addr:$src))]>; 354let isReMaterializable = 1, mayHaveSideEffects = 1 in 355 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 356 [(set RFP64:$dst, (loadf64 addr:$src))]>; 357def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 358 [(set RFP80:$dst, (loadf80 addr:$src))]>; 359} 360def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 361 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 362def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 363 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 364def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 365 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 366def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 367 [(set RFP32:$dst, (X86fild addr:$src, i16))]>; 368def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 369 [(set RFP32:$dst, (X86fild addr:$src, i32))]>; 370def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 371 [(set RFP32:$dst, (X86fild addr:$src, i64))]>; 372def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 373 [(set RFP64:$dst, (X86fild addr:$src, i16))]>; 374def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 375 [(set RFP64:$dst, (X86fild addr:$src, i32))]>; 376def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 377 [(set RFP64:$dst, (X86fild addr:$src, i64))]>; 378def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 379 [(set RFP80:$dst, (X86fild addr:$src, i16))]>; 380def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 381 [(set RFP80:$dst, (X86fild addr:$src, i32))]>; 382def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 383 [(set RFP80:$dst, (X86fild addr:$src, i64))]>; 384 385def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 386 [(store RFP32:$src, addr:$op)]>; 387def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 388 [(truncstoref32 RFP64:$src, addr:$op)]>; 389def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 390 [(store RFP64:$src, addr:$op)]>; 391def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 392 [(truncstoref32 RFP80:$src, addr:$op)]>; 393def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 394 [(truncstoref64 RFP80:$src, addr:$op)]>; 395// FST does not support 80-bit memory target; FSTP must be used. 396 397let mayStore = 1, neverHasSideEffects = 1 in { 398def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 399def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 400def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 401def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 402def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 403} 404def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 405 [(store RFP80:$src, addr:$op)]>; 406let mayStore = 1, neverHasSideEffects = 1 in { 407def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 408def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 409def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 410def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 411def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 412def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 413def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 414def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 415def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 416} 417 418let mayLoad = 1 in { 419def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 420def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 421def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 422def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 423def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 424def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 425} 426let mayStore = 1 in { 427def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 428def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 429def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 430def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 431def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 432def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 433def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 434def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 435def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 436def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 437} 438 439// FISTTP requires SSE3 even though it's a FPStack op. 440def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 441 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>, 442 Requires<[HasSSE3]>; 443def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 444 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>, 445 Requires<[HasSSE3]>; 446def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 447 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>, 448 Requires<[HasSSE3]>; 449def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 450 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>, 451 Requires<[HasSSE3]>; 452def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 453 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>, 454 Requires<[HasSSE3]>; 455def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 456 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>, 457 Requires<[HasSSE3]>; 458def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 459 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>, 460 Requires<[HasSSE3]>; 461def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 462 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>, 463 Requires<[HasSSE3]>; 464def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 465 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>, 466 Requires<[HasSSE3]>; 467 468let mayStore = 1 in { 469def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 470def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 471def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 472} 473 474// FP Stack manipulation instructions. 475def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9; 476def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD; 477def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD; 478def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9; 479 480// Floating point constant loads. 481let isReMaterializable = 1 in { 482def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 483 [(set RFP32:$dst, fpimm0)]>; 484def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 485 [(set RFP32:$dst, fpimm1)]>; 486def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 487 [(set RFP64:$dst, fpimm0)]>; 488def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 489 [(set RFP64:$dst, fpimm1)]>; 490def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 491 [(set RFP80:$dst, fpimm0)]>; 492def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 493 [(set RFP80:$dst, fpimm1)]>; 494} 495 496def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9; 497def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9; 498 499 500// Floating point compares. 501let Defs = [EFLAGS] in { 502def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 503 []>; // FPSW = cmp ST(0) with ST(i) 504def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 505 []>; // FPSW = cmp ST(0) with ST(i) 506def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 507 []>; // FPSW = cmp ST(0) with ST(i) 508 509def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 510 [(X86cmp RFP32:$lhs, RFP32:$rhs), 511 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) 512def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 513 [(X86cmp RFP64:$lhs, RFP64:$rhs), 514 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) 515def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 516 [(X86cmp RFP80:$lhs, RFP80:$rhs), 517 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) 518} 519 520let Defs = [EFLAGS], Uses = [ST0] in { 521def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) 522 (outs), (ins RST:$reg), 523 "fucom\t$reg">, DD; 524def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop 525 (outs), (ins RST:$reg), 526 "fucomp\t$reg">, DD; 527def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop 528 (outs), (ins), 529 "fucompp">, DA; 530 531def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) 532 (outs), (ins RST:$reg), 533 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB; 534def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop 535 (outs), (ins RST:$reg), 536 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF; 537} 538 539// Floating point flag ops. 540let Defs = [AX] in 541def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags 542 (outs), (ins), "fnstsw", []>, DF; 543 544def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 545 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 546 [(X86fp_cwd_get16 addr:$dst)]>; 547 548let mayLoad = 1 in 549def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 550 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>; 551 552//===----------------------------------------------------------------------===// 553// Non-Instruction Patterns 554//===----------------------------------------------------------------------===// 555 556// Required for RET of f32 / f64 / f80 values. 557def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; 558def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; 559def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; 560 561// Required for CALL which return f32 / f64 / f80 values. 562def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; 563def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>; 564def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; 565def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>; 566def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>; 567def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>; 568 569// Floating point constant -0.0 and -1.0 570def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 571def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 572def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 573def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 574def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 575def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 576 577// Used to conv. i64 to f64 since there isn't a SSE version. 578def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; 579 580// FP extensions map onto simple pseudo-value conversions if they are to/from 581// the FP stack. 582def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, 583 Requires<[FPStackf32]>; 584def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, 585 Requires<[FPStackf32]>; 586def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, 587 Requires<[FPStackf64]>; 588 589// FP truncations map onto simple pseudo-value conversions if they are to/from 590// the FP stack. We have validated that only value-preserving truncations make 591// it through isel. 592def : Pat<(f32 (fround RFP64:$src)), (MOV_Fp6432 RFP64:$src)>, 593 Requires<[FPStackf32]>; 594def : Pat<(f32 (fround RFP80:$src)), (MOV_Fp8032 RFP80:$src)>, 595 Requires<[FPStackf32]>; 596def : Pat<(f64 (fround RFP80:$src)), (MOV_Fp8064 RFP80:$src)>, 597 Requires<[FPStackf64]>; 598