1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N)); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N)); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 47 "#ADJCALLSTACKDOWN", 48 []>, 49 Requires<[NotLP64]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[NotLP64]>; 54} 55def : Pat<(X86callseq_start timm:$amt1), 56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>; 57 58 59// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 60// a stack adjustment and the codegen must know that they may modify the stack 61// pointer before prolog-epilog rewriting occurs. 62// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 63// sub / add which can clobber EFLAGS. 64let Defs = [RSP, EFLAGS], Uses = [RSP] in { 65def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 66 "#ADJCALLSTACKDOWN", 67 []>, 68 Requires<[IsLP64]>; 69def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 70 "#ADJCALLSTACKUP", 71 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 72 Requires<[IsLP64]>; 73} 74def : Pat<(X86callseq_start timm:$amt1), 75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>; 76 77 78// x86-64 va_start lowering magic. 79let usesCustomInserter = 1, Defs = [EFLAGS] in { 80def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 81 (outs), 82 (ins GR8:$al, 83 i64imm:$regsavefi, i64imm:$offset, 84 variable_ops), 85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 86 [(X86vastart_save_xmm_regs GR8:$al, 87 imm:$regsavefi, 88 imm:$offset), 89 (implicit EFLAGS)]>; 90 91// The VAARG_64 pseudo-instruction takes the address of the va_list, 92// and places the address of the next argument into a register. 93let Defs = [EFLAGS] in 94def VAARG_64 : I<0, Pseudo, 95 (outs GR64:$dst), 96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 97 "#VAARG_64 $dst, $ap, $size, $mode, $align", 98 [(set GR64:$dst, 99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 100 (implicit EFLAGS)]>; 101 102// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 103// targets. These calls are needed to probe the stack when allocating more than 104// 4k bytes in one go. Touching the stack at 4K increments is necessary to 105// ensure that the guard pages used by the OS virtual memory manager are 106// allocated in correct sequence. 107// The main point of having separate instruction are extra unmodelled effects 108// (compared to ordinary calls) like stack pointer change. 109 110let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 112 "# dynamic stack allocation", 113 [(X86WinAlloca)]>; 114 115// When using segmented stacks these are lowered into instructions which first 116// check if the current stacklet has enough free memory. If it does, memory is 117// allocated by bumping the stack pointer. Otherwise memory is allocated from 118// the heap. 119 120let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 121def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 122 "# variable sized alloca for segmented stacks", 123 [(set GR32:$dst, 124 (X86SegAlloca GR32:$size))]>, 125 Requires<[NotLP64]>; 126 127let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 128def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 129 "# variable sized alloca for segmented stacks", 130 [(set GR64:$dst, 131 (X86SegAlloca GR64:$size))]>, 132 Requires<[In64BitMode]>; 133} 134 135//===----------------------------------------------------------------------===// 136// EH Pseudo Instructions 137// 138let SchedRW = [WriteSystem] in { 139let isTerminator = 1, isReturn = 1, isBarrier = 1, 140 hasCtrlDep = 1, isCodeGenOnly = 1 in { 141def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 142 "ret\t#eh_return, addr: $addr", 143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 144 145} 146 147let isTerminator = 1, isReturn = 1, isBarrier = 1, 148 hasCtrlDep = 1, isCodeGenOnly = 1 in { 149def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 150 "ret\t#eh_return, addr: $addr", 151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 152 153} 154 155let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 156 isCodeGenOnly = 1, isReturn = 1 in { 157 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 158 159 // CATCHRET needs a custom inserter for SEH. 160 let usesCustomInserter = 1 in 161 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 162 "# CATCHRET", 163 [(catchret bb:$dst, bb:$from)]>; 164} 165 166let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, 167 usesCustomInserter = 1 in 168def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>; 169 170// This instruction is responsible for re-establishing stack pointers after an 171// exception has been caught and we are rejoining normal control flow in the 172// parent function or funclet. It generally sets ESP and EBP, and optionally 173// ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us 174// elsewhere. 175let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in 176def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>; 177 178let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 179 usesCustomInserter = 1 in { 180 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 181 "#EH_SJLJ_SETJMP32", 182 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 183 Requires<[Not64BitMode]>; 184 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 185 "#EH_SJLJ_SETJMP64", 186 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 187 Requires<[In64BitMode]>; 188 let isTerminator = 1 in { 189 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 190 "#EH_SJLJ_LONGJMP32", 191 [(X86eh_sjlj_longjmp addr:$buf)]>, 192 Requires<[Not64BitMode]>; 193 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 194 "#EH_SJLJ_LONGJMP64", 195 [(X86eh_sjlj_longjmp addr:$buf)]>, 196 Requires<[In64BitMode]>; 197 } 198} 199} // SchedRW 200 201let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 202 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 203 "#EH_SjLj_Setup\t$dst", []>; 204} 205 206//===----------------------------------------------------------------------===// 207// Pseudo instructions used by unwind info. 208// 209let isPseudo = 1 in { 210 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 211 "#SEH_PushReg $reg", []>; 212 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 213 "#SEH_SaveReg $reg, $dst", []>; 214 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 215 "#SEH_SaveXMM $reg, $dst", []>; 216 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 217 "#SEH_StackAlloc $size", []>; 218 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 219 "#SEH_SetFrame $reg, $offset", []>; 220 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 221 "#SEH_PushFrame $mode", []>; 222 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 223 "#SEH_EndPrologue", []>; 224 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 225 "#SEH_Epilogue", []>; 226} 227 228//===----------------------------------------------------------------------===// 229// Pseudo instructions used by segmented stacks. 230// 231 232// This is lowered into a RET instruction by MCInstLower. We need 233// this so that we don't have to have a MachineBasicBlock which ends 234// with a RET and also has successors. 235let isPseudo = 1 in { 236def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 237 "", []>; 238 239// This instruction is lowered to a RET followed by a MOV. The two 240// instructions are not generated on a higher level since then the 241// verifier sees a MachineBasicBlock ending with a non-terminator. 242def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 243 "", []>; 244} 245 246//===----------------------------------------------------------------------===// 247// Alias Instructions 248//===----------------------------------------------------------------------===// 249 250// Alias instruction mapping movr0 to xor. 251// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 252let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 253 isPseudo = 1, AddedComplexity = 20 in 254def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 255 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>; 256 257// Other widths can also make use of the 32-bit xor, which may have a smaller 258// encoding and avoid partial register updates. 259def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 260def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 261def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> { 262 let AddedComplexity = 20; 263} 264 265let Predicates = [OptForSize, NotSlowIncDec, Not64BitMode], 266 AddedComplexity = 15 in { 267 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 268 // which only require 3 bytes compared to MOV32ri which requires 5. 269 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 270 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 271 [(set GR32:$dst, 1)]>; 272 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 273 [(set GR32:$dst, -1)]>; 274 } 275 276 // MOV16ri is 4 bytes, so the instructions above are smaller. 277 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 278 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 279} 280 281let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 10 in { 282// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 283// FIXME: Add itinerary class and Schedule. 284def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 285 [(set GR32:$dst, i32immSExt8:$src)]>, 286 Requires<[OptForMinSize, NotWin64WithoutFP]>; 287def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 288 [(set GR64:$dst, i64immSExt8:$src)]>, 289 Requires<[OptForMinSize, NotWin64WithoutFP]>; 290} 291 292// Materialize i64 constant where top 32-bits are zero. This could theoretically 293// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 294// that would make it more difficult to rematerialize. 295let isReMaterializable = 1, isAsCheapAsAMove = 1, 296 isPseudo = 1, hasSideEffects = 0 in 297def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>; 298 299// This 64-bit pseudo-move can be used for both a 64-bit constant that is 300// actually the zero-extension of a 32-bit constant and for labels in the 301// x86-64 small code model. 302def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>; 303 304let AddedComplexity = 1 in 305def : Pat<(i64 mov64imm32:$src), 306 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; 307 308// Use sbb to materialize carry bit. 309let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { 310// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 311// However, Pat<> can't replicate the destination reg into the inputs of the 312// result. 313def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 314 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 315def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 316 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 317def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 318 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 319def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 320 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 321} // isCodeGenOnly 322 323 324def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 325 (SETB_C16r)>; 326def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 327 (SETB_C32r)>; 328def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 329 (SETB_C64r)>; 330 331def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 332 (SETB_C16r)>; 333def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 334 (SETB_C32r)>; 335def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 336 (SETB_C64r)>; 337 338// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 339// will be eliminated and that the sbb can be extended up to a wider type. When 340// this happens, it is great. However, if we are left with an 8-bit sbb and an 341// and, we might as well just match it as a setb. 342def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 343 (SETBr)>; 344 345// (add OP, SETB) -> (adc OP, 0) 346def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 347 (ADC8ri GR8:$op, 0)>; 348def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 349 (ADC32ri8 GR32:$op, 0)>; 350def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 351 (ADC64ri8 GR64:$op, 0)>; 352 353// (sub OP, SETB) -> (sbb OP, 0) 354def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 355 (SBB8ri GR8:$op, 0)>; 356def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 357 (SBB32ri8 GR32:$op, 0)>; 358def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 359 (SBB64ri8 GR64:$op, 0)>; 360 361// (sub OP, SETCC_CARRY) -> (adc OP, 0) 362def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 363 (ADC8ri GR8:$op, 0)>; 364def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 365 (ADC32ri8 GR32:$op, 0)>; 366def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 367 (ADC64ri8 GR64:$op, 0)>; 368 369//===----------------------------------------------------------------------===// 370// String Pseudo Instructions 371// 372let SchedRW = [WriteMicrocoded] in { 373let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 374def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 375 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 376 Requires<[Not64BitMode]>; 377def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 378 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 379 Requires<[Not64BitMode]>; 380def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 381 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 382 Requires<[Not64BitMode]>; 383} 384 385let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 386def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 387 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 388 Requires<[In64BitMode]>; 389def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 390 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 391 Requires<[In64BitMode]>; 392def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 393 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 394 Requires<[In64BitMode]>; 395def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 396 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 397 Requires<[In64BitMode]>; 398} 399 400// FIXME: Should use "(X86rep_stos AL)" as the pattern. 401let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 402 let Uses = [AL,ECX,EDI] in 403 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 404 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 405 Requires<[Not64BitMode]>; 406 let Uses = [AX,ECX,EDI] in 407 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 408 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 409 Requires<[Not64BitMode]>; 410 let Uses = [EAX,ECX,EDI] in 411 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 412 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 413 Requires<[Not64BitMode]>; 414} 415 416let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 417 let Uses = [AL,RCX,RDI] in 418 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 419 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 420 Requires<[In64BitMode]>; 421 let Uses = [AX,RCX,RDI] in 422 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 423 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 424 Requires<[In64BitMode]>; 425 let Uses = [RAX,RCX,RDI] in 426 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 427 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 428 Requires<[In64BitMode]>; 429 430 let Uses = [RAX,RCX,RDI] in 431 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 432 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 433 Requires<[In64BitMode]>; 434} 435} // SchedRW 436 437//===----------------------------------------------------------------------===// 438// Thread Local Storage Instructions 439// 440 441// ELF TLS Support 442// All calls clobber the non-callee saved registers. ESP is marked as 443// a use to prevent stack-pointer assignments that appear immediately 444// before calls from potentially appearing dead. 445let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 446 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 447 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 448 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 449 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 450 usesCustomInserter = 1, Uses = [ESP] in { 451def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 452 "# TLS_addr32", 453 [(X86tlsaddr tls32addr:$sym)]>, 454 Requires<[Not64BitMode]>; 455def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 456 "# TLS_base_addr32", 457 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 458 Requires<[Not64BitMode]>; 459} 460 461// All calls clobber the non-callee saved registers. RSP is marked as 462// a use to prevent stack-pointer assignments that appear immediately 463// before calls from potentially appearing dead. 464let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 465 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 466 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 467 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 468 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 469 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 470 usesCustomInserter = 1, Uses = [RSP] in { 471def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 472 "# TLS_addr64", 473 [(X86tlsaddr tls64addr:$sym)]>, 474 Requires<[In64BitMode]>; 475def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 476 "# TLS_base_addr64", 477 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 478 Requires<[In64BitMode]>; 479} 480 481// Darwin TLS Support 482// For i386, the address of the thunk is passed on the stack, on return the 483// address of the variable is in %eax. %ecx is trashed during the function 484// call. All other registers are preserved. 485let Defs = [EAX, ECX, EFLAGS], 486 Uses = [ESP], 487 usesCustomInserter = 1 in 488def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 489 "# TLSCall_32", 490 [(X86TLSCall addr:$sym)]>, 491 Requires<[Not64BitMode]>; 492 493// For x86_64, the address of the thunk is passed in %rdi, on return 494// the address of the variable is in %rax. All other registers are preserved. 495let Defs = [RAX, EFLAGS], 496 Uses = [RSP, RDI], 497 usesCustomInserter = 1 in 498def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 499 "# TLSCall_64", 500 [(X86TLSCall addr:$sym)]>, 501 Requires<[In64BitMode]>; 502 503 504//===----------------------------------------------------------------------===// 505// Conditional Move Pseudo Instructions 506 507// CMOV* - Used to implement the SELECT DAG operation. Expanded after 508// instruction selection into a branch sequence. 509multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 510 def CMOV#NAME : I<0, Pseudo, 511 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 512 "#CMOV_"#NAME#" PSEUDO!", 513 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond, 514 EFLAGS)))]>; 515} 516 517let usesCustomInserter = 1, Uses = [EFLAGS] in { 518 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 519 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 520 // however that requires promoting the operands, and can induce additional 521 // i8 register pressure. 522 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 523 524 let Predicates = [NoCMov] in { 525 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 526 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 527 } // Predicates = [NoCMov] 528 529 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 530 // SSE1/SSE2. 531 let Predicates = [FPStackf32] in 532 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 533 534 let Predicates = [FPStackf64] in 535 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 536 537 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 538 539 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 540 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 541 defm _FR128 : CMOVrr_PSEUDO<FR128, f128>; 542 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>; 543 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>; 544 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>; 545 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>; 546 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>; 547 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>; 548 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>; 549 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>; 550 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>; 551 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>; 552 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>; 553 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>; 554 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>; 555} // usesCustomInserter = 1, Uses = [EFLAGS] 556 557//===----------------------------------------------------------------------===// 558// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 559//===----------------------------------------------------------------------===// 560 561// FIXME: Use normal instructions and add lock prefix dynamically. 562 563// Memory barriers 564 565// TODO: Get this to fold the constant into the instruction. 566let isCodeGenOnly = 1, Defs = [EFLAGS] in 567def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 568 "or{l}\t{$zero, $dst|$dst, $zero}", [], 569 IIC_ALU_MEM>, Requires<[Not64BitMode]>, OpSize32, LOCK, 570 Sched<[WriteALULd, WriteRMW]>; 571 572let hasSideEffects = 1 in 573def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 574 "#MEMBARRIER", 575 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 576 577// RegOpc corresponds to the mr version of the instruction 578// ImmOpc corresponds to the mi version of the instruction 579// ImmOpc8 corresponds to the mi8 version of the instruction 580// ImmMod corresponds to the instruction format of the mi and mi8 versions 581multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 582 Format ImmMod, SDPatternOperator Op, string mnemonic> { 583let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 584 SchedRW = [WriteALULd, WriteRMW] in { 585 586def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 587 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 588 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 589 !strconcat(mnemonic, "{b}\t", 590 "{$src2, $dst|$dst, $src2}"), 591 [(set EFLAGS, (Op addr:$dst, GR8:$src2))], 592 IIC_ALU_NONMEM>, LOCK; 593 594def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 595 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 596 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 597 !strconcat(mnemonic, "{w}\t", 598 "{$src2, $dst|$dst, $src2}"), 599 [(set EFLAGS, (Op addr:$dst, GR16:$src2))], 600 IIC_ALU_NONMEM>, OpSize16, LOCK; 601 602def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 603 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 604 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 605 !strconcat(mnemonic, "{l}\t", 606 "{$src2, $dst|$dst, $src2}"), 607 [(set EFLAGS, (Op addr:$dst, GR32:$src2))], 608 IIC_ALU_NONMEM>, OpSize32, LOCK; 609 610def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 611 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 612 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 613 !strconcat(mnemonic, "{q}\t", 614 "{$src2, $dst|$dst, $src2}"), 615 [(set EFLAGS, (Op addr:$dst, GR64:$src2))], 616 IIC_ALU_NONMEM>, LOCK; 617 618def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 619 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 620 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 621 !strconcat(mnemonic, "{b}\t", 622 "{$src2, $dst|$dst, $src2}"), 623 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))], 624 IIC_ALU_MEM>, LOCK; 625 626def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 627 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 628 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 629 !strconcat(mnemonic, "{w}\t", 630 "{$src2, $dst|$dst, $src2}"), 631 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))], 632 IIC_ALU_MEM>, OpSize16, LOCK; 633 634def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 635 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 636 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 637 !strconcat(mnemonic, "{l}\t", 638 "{$src2, $dst|$dst, $src2}"), 639 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))], 640 IIC_ALU_MEM>, OpSize32, LOCK; 641 642def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 643 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 644 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 645 !strconcat(mnemonic, "{q}\t", 646 "{$src2, $dst|$dst, $src2}"), 647 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))], 648 IIC_ALU_MEM>, LOCK; 649 650def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 651 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 652 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 653 !strconcat(mnemonic, "{w}\t", 654 "{$src2, $dst|$dst, $src2}"), 655 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))], 656 IIC_ALU_MEM>, OpSize16, LOCK; 657 658def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 659 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 660 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 661 !strconcat(mnemonic, "{l}\t", 662 "{$src2, $dst|$dst, $src2}"), 663 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))], 664 IIC_ALU_MEM>, OpSize32, LOCK; 665 666def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 667 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 668 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 669 !strconcat(mnemonic, "{q}\t", 670 "{$src2, $dst|$dst, $src2}"), 671 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))], 672 IIC_ALU_MEM>, LOCK; 673 674} 675 676} 677 678defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 679defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 680defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 681defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 682defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 683 684multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 685 int Increment, string mnemonic> { 686let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 687 SchedRW = [WriteALULd, WriteRMW], Predicates = [NotSlowIncDec] in { 688def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 689 !strconcat(mnemonic, "{b}\t$dst"), 690 [(set EFLAGS, (X86lock_add addr:$dst, (i8 Increment)))], 691 IIC_UNARY_MEM>, LOCK; 692def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 693 !strconcat(mnemonic, "{w}\t$dst"), 694 [(set EFLAGS, (X86lock_add addr:$dst, (i16 Increment)))], 695 IIC_UNARY_MEM>, OpSize16, LOCK; 696def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 697 !strconcat(mnemonic, "{l}\t$dst"), 698 [(set EFLAGS, (X86lock_add addr:$dst, (i32 Increment)))], 699 IIC_UNARY_MEM>, OpSize32, LOCK; 700def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 701 !strconcat(mnemonic, "{q}\t$dst"), 702 [(set EFLAGS, (X86lock_add addr:$dst, (i64 Increment)))], 703 IIC_UNARY_MEM>, LOCK; 704} 705} 706 707defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, 1, "inc">; 708defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, -1, "dec">; 709 710// Atomic compare and swap. 711multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 712 SDPatternOperator frag, X86MemOperand x86memop, 713 InstrItinClass itin> { 714let isCodeGenOnly = 1 in { 715 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 716 !strconcat(mnemonic, "\t$ptr"), 717 [(frag addr:$ptr)], itin>, TB, LOCK; 718} 719} 720 721multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 722 string mnemonic, SDPatternOperator frag, 723 InstrItinClass itin8, InstrItinClass itin> { 724let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { 725 let Defs = [AL, EFLAGS], Uses = [AL] in 726 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 727 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 728 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 729 let Defs = [AX, EFLAGS], Uses = [AX] in 730 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 731 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 732 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK; 733 let Defs = [EAX, EFLAGS], Uses = [EAX] in 734 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 735 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 736 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK; 737 let Defs = [RAX, EFLAGS], Uses = [RAX] in 738 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 739 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 740 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 741} 742} 743 744let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 745 SchedRW = [WriteALULd, WriteRMW] in { 746defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 747 X86cas8, i64mem, 748 IIC_CMPX_LOCK_8B>; 749} 750 751// This pseudo must be used when the frame uses RBX as 752// the base pointer. Indeed, in such situation RBX is a reserved 753// register and the register allocator will ignore any use/def of 754// it. In other words, the register will not fix the clobbering of 755// RBX that will happen when setting the arguments for the instrucion. 756// 757// Unlike the actual related instuction, we mark that this one 758// defines EBX (instead of using EBX). 759// The rationale is that we will define RBX during the expansion of 760// the pseudo. The argument feeding EBX is ebx_input. 761// 762// The additional argument, $ebx_save, is a temporary register used to 763// save the value of RBX accross the actual instruction. 764// 765// To make sure the register assigned to $ebx_save does not interfere with 766// the definition of the actual instruction, we use a definition $dst which 767// is tied to $rbx_save. That way, the live-range of $rbx_save spans accross 768// the instruction and we are sure we will have a valid register to restore 769// the value of RBX. 770let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX], 771 SchedRW = [WriteALULd, WriteRMW], isCodeGenOnly = 1, isPseudo = 1, 772 Constraints = "$ebx_save = $dst", usesCustomInserter = 1 in { 773def LCMPXCHG8B_SAVE_EBX : 774 I<0, Pseudo, (outs GR32:$dst), 775 (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save), 776 !strconcat("cmpxchg8b", "\t$ptr"), 777 [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input, 778 GR32:$ebx_save))], 779 IIC_CMPX_LOCK_8B>; 780} 781 782 783let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 784 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { 785defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 786 X86cas16, i128mem, 787 IIC_CMPX_LOCK_16B>, REX_W; 788} 789 790// Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant. 791let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 792 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW], 793 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst", 794 usesCustomInserter = 1 in { 795def LCMPXCHG16B_SAVE_RBX : 796 I<0, Pseudo, (outs GR64:$dst), 797 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), 798 !strconcat("cmpxchg16b", "\t$ptr"), 799 [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input, 800 GR64:$rbx_save))], 801 IIC_CMPX_LOCK_16B>; 802} 803 804defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 805 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 806 807// Atomic exchange and add 808multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 809 string frag, 810 InstrItinClass itin8, InstrItinClass itin> { 811 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, 812 SchedRW = [WriteALULd, WriteRMW] in { 813 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 814 (ins GR8:$val, i8mem:$ptr), 815 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 816 [(set GR8:$dst, 817 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 818 itin8>; 819 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 820 (ins GR16:$val, i16mem:$ptr), 821 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 822 [(set 823 GR16:$dst, 824 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 825 itin>, OpSize16; 826 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 827 (ins GR32:$val, i32mem:$ptr), 828 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 829 [(set 830 GR32:$dst, 831 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 832 itin>, OpSize32; 833 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 834 (ins GR64:$val, i64mem:$ptr), 835 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 836 [(set 837 GR64:$dst, 838 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 839 itin>; 840 } 841} 842 843defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 844 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 845 TB, LOCK; 846 847/* The following multiclass tries to make sure that in code like 848 * x.store (immediate op x.load(acquire), release) 849 * and 850 * x.store (register op x.load(acquire), release) 851 * an operation directly on memory is generated instead of wasting a register. 852 * It is not automatic as atomic_store/load are only lowered to MOV instructions 853 * extremely late to prevent them from being accidentally reordered in the backend 854 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 855 */ 856multiclass RELEASE_BINOP_MI<SDNode op> { 857 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 858 "#BINOP "#NAME#"8mi PSEUDO!", 859 [(atomic_store_8 addr:$dst, (op 860 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>; 861 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src), 862 "#BINOP "#NAME#"8mr PSEUDO!", 863 [(atomic_store_8 addr:$dst, (op 864 (atomic_load_8 addr:$dst), GR8:$src))]>; 865 // NAME#16 is not generated as 16-bit arithmetic instructions are considered 866 // costly and avoided as far as possible by this backend anyway 867 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 868 "#BINOP "#NAME#"32mi PSEUDO!", 869 [(atomic_store_32 addr:$dst, (op 870 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>; 871 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 872 "#BINOP "#NAME#"32mr PSEUDO!", 873 [(atomic_store_32 addr:$dst, (op 874 (atomic_load_32 addr:$dst), GR32:$src))]>; 875 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 876 "#BINOP "#NAME#"64mi32 PSEUDO!", 877 [(atomic_store_64 addr:$dst, (op 878 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>; 879 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 880 "#BINOP "#NAME#"64mr PSEUDO!", 881 [(atomic_store_64 addr:$dst, (op 882 (atomic_load_64 addr:$dst), GR64:$src))]>; 883} 884let Defs = [EFLAGS] in { 885 defm RELEASE_ADD : RELEASE_BINOP_MI<add>; 886 defm RELEASE_AND : RELEASE_BINOP_MI<and>; 887 defm RELEASE_OR : RELEASE_BINOP_MI<or>; 888 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>; 889 // Note: we don't deal with sub, because substractions of constants are 890 // optimized into additions before this code can run. 891} 892 893// Same as above, but for floating-point. 894// FIXME: imm version. 895// FIXME: Version that doesn't clobber $src, using AVX's VADDSS. 896// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 897let usesCustomInserter = 1 in { 898multiclass RELEASE_FP_BINOP_MI<SDNode op> { 899 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src), 900 "#BINOP "#NAME#"32mr PSEUDO!", 901 [(atomic_store_32 addr:$dst, 902 (i32 (bitconvert (op 903 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))), 904 FR32:$src))))]>, Requires<[HasSSE1]>; 905 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src), 906 "#BINOP "#NAME#"64mr PSEUDO!", 907 [(atomic_store_64 addr:$dst, 908 (i64 (bitconvert (op 909 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))), 910 FR64:$src))))]>, Requires<[HasSSE2]>; 911} 912defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>; 913// FIXME: Add fsub, fmul, fdiv, ... 914} 915 916multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> { 917 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst), 918 "#UNOP "#NAME#"8m PSEUDO!", 919 [(atomic_store_8 addr:$dst, dag8)]>; 920 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst), 921 "#UNOP "#NAME#"16m PSEUDO!", 922 [(atomic_store_16 addr:$dst, dag16)]>; 923 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst), 924 "#UNOP "#NAME#"32m PSEUDO!", 925 [(atomic_store_32 addr:$dst, dag32)]>; 926 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst), 927 "#UNOP "#NAME#"64m PSEUDO!", 928 [(atomic_store_64 addr:$dst, dag64)]>; 929} 930 931let Defs = [EFLAGS] in { 932 defm RELEASE_INC : RELEASE_UNOP< 933 (add (atomic_load_8 addr:$dst), (i8 1)), 934 (add (atomic_load_16 addr:$dst), (i16 1)), 935 (add (atomic_load_32 addr:$dst), (i32 1)), 936 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>; 937 defm RELEASE_DEC : RELEASE_UNOP< 938 (add (atomic_load_8 addr:$dst), (i8 -1)), 939 (add (atomic_load_16 addr:$dst), (i16 -1)), 940 (add (atomic_load_32 addr:$dst), (i32 -1)), 941 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>; 942} 943/* 944TODO: These don't work because the type inference of TableGen fails. 945TODO: find a way to fix it. 946let Defs = [EFLAGS] in { 947 defm RELEASE_NEG : RELEASE_UNOP< 948 (ineg (atomic_load_8 addr:$dst)), 949 (ineg (atomic_load_16 addr:$dst)), 950 (ineg (atomic_load_32 addr:$dst)), 951 (ineg (atomic_load_64 addr:$dst))>; 952} 953// NOT doesn't set flags. 954defm RELEASE_NOT : RELEASE_UNOP< 955 (not (atomic_load_8 addr:$dst)), 956 (not (atomic_load_16 addr:$dst)), 957 (not (atomic_load_32 addr:$dst)), 958 (not (atomic_load_64 addr:$dst))>; 959*/ 960 961def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 962 "#RELEASE_MOV8mi PSEUDO!", 963 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>; 964def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src), 965 "#RELEASE_MOV16mi PSEUDO!", 966 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>; 967def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 968 "#RELEASE_MOV32mi PSEUDO!", 969 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>; 970def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 971 "#RELEASE_MOV64mi32 PSEUDO!", 972 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>; 973 974def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 975 "#RELEASE_MOV8mr PSEUDO!", 976 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 977def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 978 "#RELEASE_MOV16mr PSEUDO!", 979 [(atomic_store_16 addr:$dst, GR16:$src)]>; 980def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 981 "#RELEASE_MOV32mr PSEUDO!", 982 [(atomic_store_32 addr:$dst, GR32:$src)]>; 983def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 984 "#RELEASE_MOV64mr PSEUDO!", 985 [(atomic_store_64 addr:$dst, GR64:$src)]>; 986 987def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 988 "#ACQUIRE_MOV8rm PSEUDO!", 989 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 990def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 991 "#ACQUIRE_MOV16rm PSEUDO!", 992 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 993def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 994 "#ACQUIRE_MOV32rm PSEUDO!", 995 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 996def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 997 "#ACQUIRE_MOV64rm PSEUDO!", 998 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 999 1000//===----------------------------------------------------------------------===// 1001// DAG Pattern Matching Rules 1002//===----------------------------------------------------------------------===// 1003 1004// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1005// binary size compared to a regular MOV, but it introduces an unnecessary 1006// load, so is not suitable for regular or optsize functions. 1007let Predicates = [OptForMinSize] in { 1008def : Pat<(store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>; 1009def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>; 1010def : Pat<(store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>; 1011def : Pat<(store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>; 1012def : Pat<(store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>; 1013def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>; 1014} 1015 1016// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 1017def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 1018def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 1019def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 1020def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 1021def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 1022def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1023def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 1024 1025def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 1026 (ADD32ri GR32:$src1, tconstpool:$src2)>; 1027def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 1028 (ADD32ri GR32:$src1, tjumptable:$src2)>; 1029def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 1030 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 1031def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 1032 (ADD32ri GR32:$src1, texternalsym:$src2)>; 1033def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)), 1034 (ADD32ri GR32:$src1, mcsym:$src2)>; 1035def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 1036 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 1037 1038def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1039 (MOV32mi addr:$dst, tglobaladdr:$src)>; 1040def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 1041 (MOV32mi addr:$dst, texternalsym:$src)>; 1042def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst), 1043 (MOV32mi addr:$dst, mcsym:$src)>; 1044def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 1045 (MOV32mi addr:$dst, tblockaddress:$src)>; 1046 1047// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 1048// code model mode, should use 'movabs'. FIXME: This is really a hack, the 1049// 'movabs' predicate should handle this sort of thing. 1050def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1051 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 1052def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1053 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 1054def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1055 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 1056def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1057 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 1058def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1059 (MOV64ri mcsym:$dst)>, Requires<[FarData]>; 1060def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1061 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 1062 1063// In kernel code model, we can get the address of a label 1064// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1065// the MOV64ri32 should accept these. 1066def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1067 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1068def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1069 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1070def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1071 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1072def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1073 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1074def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1075 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1076def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1077 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1078 1079// If we have small model and -static mode, it is safe to store global addresses 1080// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1081// for MOV64mi32 should handle this sort of thing. 1082def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1083 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1084 Requires<[NearData, IsStatic]>; 1085def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1086 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1087 Requires<[NearData, IsStatic]>; 1088def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1089 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1090 Requires<[NearData, IsStatic]>; 1091def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1092 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1093 Requires<[NearData, IsStatic]>; 1094def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1095 (MOV64mi32 addr:$dst, mcsym:$src)>, 1096 Requires<[NearData, IsStatic]>; 1097def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1098 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1099 Requires<[NearData, IsStatic]>; 1100 1101def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1102def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1103 1104// Calls 1105 1106// tls has some funny stuff here... 1107// This corresponds to movabs $foo@tpoff, %rax 1108def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1109 (MOV64ri32 tglobaltlsaddr :$dst)>; 1110// This corresponds to add $foo@tpoff, %rax 1111def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1112 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1113 1114 1115// Direct PC relative function call for small code model. 32-bit displacement 1116// sign extended to 64-bit. 1117def : Pat<(X86call (i64 tglobaladdr:$dst)), 1118 (CALL64pcrel32 tglobaladdr:$dst)>; 1119def : Pat<(X86call (i64 texternalsym:$dst)), 1120 (CALL64pcrel32 texternalsym:$dst)>; 1121 1122// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1123// can never use callee-saved registers. That is the purpose of the GR64_TC 1124// register classes. 1125// 1126// The only volatile register that is never used by the calling convention is 1127// %r11. This happens when calling a vararg function with 6 arguments. 1128// 1129// Match an X86tcret that uses less than 7 volatile registers. 1130def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1131 (X86tcret node:$ptr, node:$off), [{ 1132 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1133 unsigned NumRegs = 0; 1134 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1135 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1136 return false; 1137 return true; 1138}]>; 1139 1140def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1141 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1142 Requires<[Not64BitMode]>; 1143 1144// FIXME: This is disabled for 32-bit PIC mode because the global base 1145// register which is part of the address mode may be assigned a 1146// callee-saved register. 1147def : Pat<(X86tcret (load addr:$dst), imm:$off), 1148 (TCRETURNmi addr:$dst, imm:$off)>, 1149 Requires<[Not64BitMode, IsNotPIC]>; 1150 1151def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1152 (TCRETURNdi tglobaladdr:$dst, imm:$off)>, 1153 Requires<[NotLP64]>; 1154 1155def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1156 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1157 Requires<[NotLP64]>; 1158 1159def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1160 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1161 Requires<[In64BitMode]>; 1162 1163// Don't fold loads into X86tcret requiring more than 6 regs. 1164// There wouldn't be enough scratch registers for base+index. 1165def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1166 (TCRETURNmi64 addr:$dst, imm:$off)>, 1167 Requires<[In64BitMode]>; 1168 1169def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1170 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1171 Requires<[IsLP64]>; 1172 1173def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1174 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1175 Requires<[IsLP64]>; 1176 1177// Normal calls, with various flavors of addresses. 1178def : Pat<(X86call (i32 tglobaladdr:$dst)), 1179 (CALLpcrel32 tglobaladdr:$dst)>; 1180def : Pat<(X86call (i32 texternalsym:$dst)), 1181 (CALLpcrel32 texternalsym:$dst)>; 1182def : Pat<(X86call (i32 imm:$dst)), 1183 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1184 1185// Comparisons. 1186 1187// TEST R,R is smaller than CMP R,0 1188def : Pat<(X86cmp GR8:$src1, 0), 1189 (TEST8rr GR8:$src1, GR8:$src1)>; 1190def : Pat<(X86cmp GR16:$src1, 0), 1191 (TEST16rr GR16:$src1, GR16:$src1)>; 1192def : Pat<(X86cmp GR32:$src1, 0), 1193 (TEST32rr GR32:$src1, GR32:$src1)>; 1194def : Pat<(X86cmp GR64:$src1, 0), 1195 (TEST64rr GR64:$src1, GR64:$src1)>; 1196 1197// Conditional moves with folded loads with operands swapped and conditions 1198// inverted. 1199multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1200 Instruction Inst64> { 1201 let Predicates = [HasCMov] in { 1202 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1203 (Inst16 GR16:$src2, addr:$src1)>; 1204 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1205 (Inst32 GR32:$src2, addr:$src1)>; 1206 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1207 (Inst64 GR64:$src2, addr:$src1)>; 1208 } 1209} 1210 1211defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1212defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1213defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1214defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1215defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1216defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1217defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1218defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1219defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1220defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1221defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1222defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1223defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1224defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1225defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1226defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1227 1228// zextload bool -> zextload byte 1229// i1 stored in one byte in zero-extended form. 1230// Upper bits cleanup should be executed before Store. 1231def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1232def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1233def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1234def : Pat<(zextloadi64i1 addr:$src), 1235 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1236 1237// extload bool -> extload byte 1238// When extloading from 16-bit and smaller memory locations into 64-bit 1239// registers, use zero-extending loads so that the entire 64-bit register is 1240// defined, avoiding partial-register updates. 1241 1242def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1243def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1244def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1245def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1246def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1247def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1248 1249// For other extloads, use subregs, since the high contents of the register are 1250// defined after an extload. 1251def : Pat<(extloadi64i1 addr:$src), 1252 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1253def : Pat<(extloadi64i8 addr:$src), 1254 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1255def : Pat<(extloadi64i16 addr:$src), 1256 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1257def : Pat<(extloadi64i32 addr:$src), 1258 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1259 1260// anyext. Define these to do an explicit zero-extend to 1261// avoid partial-register updates. 1262def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1263 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1264def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1265 1266// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1267def : Pat<(i32 (anyext GR16:$src)), 1268 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1269 1270def : Pat<(i64 (anyext GR8 :$src)), 1271 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1272def : Pat<(i64 (anyext GR16:$src)), 1273 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1274def : Pat<(i64 (anyext GR32:$src)), 1275 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1276 1277 1278// Any instruction that defines a 32-bit result leaves the high half of the 1279// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1280// be copying from a truncate. And x86's cmov doesn't do anything if the 1281// condition is false. But any other 32-bit operation will zero-extend 1282// up to 64 bits. 1283def def32 : PatLeaf<(i32 GR32:$src), [{ 1284 return N->getOpcode() != ISD::TRUNCATE && 1285 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1286 N->getOpcode() != ISD::CopyFromReg && 1287 N->getOpcode() != ISD::AssertSext && 1288 N->getOpcode() != X86ISD::CMOV; 1289}]>; 1290 1291// In the case of a 32-bit def that is known to implicitly zero-extend, 1292// we can use a SUBREG_TO_REG. 1293def : Pat<(i64 (zext def32:$src)), 1294 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1295 1296//===----------------------------------------------------------------------===// 1297// Pattern match OR as ADD 1298//===----------------------------------------------------------------------===// 1299 1300// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1301// 3-addressified into an LEA instruction to avoid copies. However, we also 1302// want to finally emit these instructions as an or at the end of the code 1303// generator to make the generated code easier to read. To do this, we select 1304// into "disjoint bits" pseudo ops. 1305 1306// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1307def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1308 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1309 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1310 1311 APInt KnownZero0, KnownOne0; 1312 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1313 APInt KnownZero1, KnownOne1; 1314 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1315 return (~KnownZero0 & ~KnownZero1) == 0; 1316}]>; 1317 1318 1319// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1320// Try this before the selecting to OR. 1321let AddedComplexity = 5, SchedRW = [WriteALU] in { 1322 1323let isConvertibleToThreeAddress = 1, 1324 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1325let isCommutable = 1 in { 1326def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1327 "", // orw/addw REG, REG 1328 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1329def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1330 "", // orl/addl REG, REG 1331 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1332def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1333 "", // orq/addq REG, REG 1334 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1335} // isCommutable 1336 1337// NOTE: These are order specific, we want the ri8 forms to be listed 1338// first so that they are slightly preferred to the ri forms. 1339 1340def ADD16ri8_DB : I<0, Pseudo, 1341 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1342 "", // orw/addw REG, imm8 1343 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1344def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1345 "", // orw/addw REG, imm 1346 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1347 1348def ADD32ri8_DB : I<0, Pseudo, 1349 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1350 "", // orl/addl REG, imm8 1351 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1352def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1353 "", // orl/addl REG, imm 1354 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1355 1356 1357def ADD64ri8_DB : I<0, Pseudo, 1358 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1359 "", // orq/addq REG, imm8 1360 [(set GR64:$dst, (or_is_add GR64:$src1, 1361 i64immSExt8:$src2))]>; 1362def ADD64ri32_DB : I<0, Pseudo, 1363 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1364 "", // orq/addq REG, imm 1365 [(set GR64:$dst, (or_is_add GR64:$src1, 1366 i64immSExt32:$src2))]>; 1367} 1368} // AddedComplexity, SchedRW 1369 1370 1371//===----------------------------------------------------------------------===// 1372// Some peepholes 1373//===----------------------------------------------------------------------===// 1374 1375// Odd encoding trick: -128 fits into an 8-bit immediate field while 1376// +128 doesn't, so in this special case use a sub instead of an add. 1377def : Pat<(add GR16:$src1, 128), 1378 (SUB16ri8 GR16:$src1, -128)>; 1379def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1380 (SUB16mi8 addr:$dst, -128)>; 1381 1382def : Pat<(add GR32:$src1, 128), 1383 (SUB32ri8 GR32:$src1, -128)>; 1384def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1385 (SUB32mi8 addr:$dst, -128)>; 1386 1387def : Pat<(add GR64:$src1, 128), 1388 (SUB64ri8 GR64:$src1, -128)>; 1389def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1390 (SUB64mi8 addr:$dst, -128)>; 1391 1392// The same trick applies for 32-bit immediate fields in 64-bit 1393// instructions. 1394def : Pat<(add GR64:$src1, 0x0000000080000000), 1395 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1396def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1397 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1398 1399// To avoid needing to materialize an immediate in a register, use a 32-bit and 1400// with implicit zero-extension instead of a 64-bit and if the immediate has at 1401// least 32 bits of leading zeros. If in addition the last 32 bits can be 1402// represented with a sign extension of a 8 bit constant, use that. 1403// This can also reduce instruction size by eliminating the need for the REX 1404// prefix. 1405 1406// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1407let AddedComplexity = 1 in { 1408def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1409 (SUBREG_TO_REG 1410 (i64 0), 1411 (AND32ri8 1412 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1413 (i32 (GetLo8XForm imm:$imm))), 1414 sub_32bit)>; 1415 1416def : Pat<(and GR64:$src, i64immZExt32:$imm), 1417 (SUBREG_TO_REG 1418 (i64 0), 1419 (AND32ri 1420 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1421 (i32 (GetLo32XForm imm:$imm))), 1422 sub_32bit)>; 1423} // AddedComplexity = 1 1424 1425 1426// AddedComplexity is needed due to the increased complexity on the 1427// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1428// the MOVZX patterns keeps thems together in DAGIsel tables. 1429let AddedComplexity = 1 in { 1430// r & (2^16-1) ==> movz 1431def : Pat<(and GR32:$src1, 0xffff), 1432 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1433// r & (2^8-1) ==> movz 1434def : Pat<(and GR32:$src1, 0xff), 1435 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1436 GR32_ABCD)), 1437 sub_8bit))>, 1438 Requires<[Not64BitMode]>; 1439// r & (2^8-1) ==> movz 1440def : Pat<(and GR16:$src1, 0xff), 1441 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1442 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1443 sub_16bit)>, 1444 Requires<[Not64BitMode]>; 1445 1446// r & (2^32-1) ==> movz 1447def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1448 (SUBREG_TO_REG (i64 0), 1449 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1450 sub_32bit)>; 1451// r & (2^16-1) ==> movz 1452def : Pat<(and GR64:$src, 0xffff), 1453 (SUBREG_TO_REG (i64 0), 1454 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1455 sub_32bit)>; 1456// r & (2^8-1) ==> movz 1457def : Pat<(and GR64:$src, 0xff), 1458 (SUBREG_TO_REG (i64 0), 1459 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1460 sub_32bit)>; 1461// r & (2^8-1) ==> movz 1462def : Pat<(and GR32:$src1, 0xff), 1463 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1464 Requires<[In64BitMode]>; 1465// r & (2^8-1) ==> movz 1466def : Pat<(and GR16:$src1, 0xff), 1467 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1468 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1469 Requires<[In64BitMode]>; 1470} // AddedComplexity = 1 1471 1472 1473// sext_inreg patterns 1474def : Pat<(sext_inreg GR32:$src, i16), 1475 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1476def : Pat<(sext_inreg GR32:$src, i8), 1477 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1478 GR32_ABCD)), 1479 sub_8bit))>, 1480 Requires<[Not64BitMode]>; 1481 1482def : Pat<(sext_inreg GR16:$src, i8), 1483 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1484 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1485 sub_16bit)>, 1486 Requires<[Not64BitMode]>; 1487 1488def : Pat<(sext_inreg GR64:$src, i32), 1489 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1490def : Pat<(sext_inreg GR64:$src, i16), 1491 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1492def : Pat<(sext_inreg GR64:$src, i8), 1493 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1494def : Pat<(sext_inreg GR32:$src, i8), 1495 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1496 Requires<[In64BitMode]>; 1497def : Pat<(sext_inreg GR16:$src, i8), 1498 (EXTRACT_SUBREG (MOVSX32rr8 1499 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1500 Requires<[In64BitMode]>; 1501 1502// sext, sext_load, zext, zext_load 1503def: Pat<(i16 (sext GR8:$src)), 1504 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1505def: Pat<(sextloadi16i8 addr:$src), 1506 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1507def: Pat<(i16 (zext GR8:$src)), 1508 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1509def: Pat<(zextloadi16i8 addr:$src), 1510 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1511 1512// trunc patterns 1513def : Pat<(i16 (trunc GR32:$src)), 1514 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1515def : Pat<(i8 (trunc GR32:$src)), 1516 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1517 sub_8bit)>, 1518 Requires<[Not64BitMode]>; 1519def : Pat<(i8 (trunc GR16:$src)), 1520 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1521 sub_8bit)>, 1522 Requires<[Not64BitMode]>; 1523def : Pat<(i32 (trunc GR64:$src)), 1524 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1525def : Pat<(i16 (trunc GR64:$src)), 1526 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1527def : Pat<(i8 (trunc GR64:$src)), 1528 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1529def : Pat<(i8 (trunc GR32:$src)), 1530 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1531 Requires<[In64BitMode]>; 1532def : Pat<(i8 (trunc GR16:$src)), 1533 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1534 Requires<[In64BitMode]>; 1535 1536// h-register tricks 1537def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1538 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1539 sub_8bit_hi)>, 1540 Requires<[Not64BitMode]>; 1541def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1542 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1543 sub_8bit_hi)>, 1544 Requires<[Not64BitMode]>; 1545def : Pat<(srl GR16:$src, (i8 8)), 1546 (EXTRACT_SUBREG 1547 (MOVZX32rr8 1548 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1549 sub_8bit_hi)), 1550 sub_16bit)>, 1551 Requires<[Not64BitMode]>; 1552def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1553 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1554 GR16_ABCD)), 1555 sub_8bit_hi))>, 1556 Requires<[Not64BitMode]>; 1557def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1558 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1559 GR16_ABCD)), 1560 sub_8bit_hi))>, 1561 Requires<[Not64BitMode]>; 1562def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1563 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1564 GR32_ABCD)), 1565 sub_8bit_hi))>, 1566 Requires<[Not64BitMode]>; 1567def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1568 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1569 GR32_ABCD)), 1570 sub_8bit_hi))>, 1571 Requires<[Not64BitMode]>; 1572 1573// h-register tricks. 1574// For now, be conservative on x86-64 and use an h-register extract only if the 1575// value is immediately zero-extended or stored, which are somewhat common 1576// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1577// from being allocated in the same instruction as the h register, as there's 1578// currently no way to describe this requirement to the register allocator. 1579 1580// h-register extract and zero-extend. 1581def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1582 (SUBREG_TO_REG 1583 (i64 0), 1584 (MOVZX32_NOREXrr8 1585 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1586 sub_8bit_hi)), 1587 sub_32bit)>; 1588def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1589 (MOVZX32_NOREXrr8 1590 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1591 sub_8bit_hi))>, 1592 Requires<[In64BitMode]>; 1593def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1594 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1595 GR32_ABCD)), 1596 sub_8bit_hi))>, 1597 Requires<[In64BitMode]>; 1598def : Pat<(srl GR16:$src, (i8 8)), 1599 (EXTRACT_SUBREG 1600 (MOVZX32_NOREXrr8 1601 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1602 sub_8bit_hi)), 1603 sub_16bit)>, 1604 Requires<[In64BitMode]>; 1605def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1606 (MOVZX32_NOREXrr8 1607 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1608 sub_8bit_hi))>, 1609 Requires<[In64BitMode]>; 1610def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1611 (MOVZX32_NOREXrr8 1612 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1613 sub_8bit_hi))>, 1614 Requires<[In64BitMode]>; 1615def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1616 (SUBREG_TO_REG 1617 (i64 0), 1618 (MOVZX32_NOREXrr8 1619 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1620 sub_8bit_hi)), 1621 sub_32bit)>; 1622def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1623 (SUBREG_TO_REG 1624 (i64 0), 1625 (MOVZX32_NOREXrr8 1626 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1627 sub_8bit_hi)), 1628 sub_32bit)>; 1629 1630// h-register extract and store. 1631def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1632 (MOV8mr_NOREX 1633 addr:$dst, 1634 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1635 sub_8bit_hi))>; 1636def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1637 (MOV8mr_NOREX 1638 addr:$dst, 1639 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1640 sub_8bit_hi))>, 1641 Requires<[In64BitMode]>; 1642def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1643 (MOV8mr_NOREX 1644 addr:$dst, 1645 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1646 sub_8bit_hi))>, 1647 Requires<[In64BitMode]>; 1648 1649 1650// (shl x, 1) ==> (add x, x) 1651// Note that if x is undef (immediate or otherwise), we could theoretically 1652// end up with the two uses of x getting different values, producing a result 1653// where the least significant bit is not 0. However, the probability of this 1654// happening is considered low enough that this is officially not a 1655// "real problem". 1656def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1657def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1658def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1659def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1660 1661// Helper imms that check if a mask doesn't change significant shift bits. 1662def immShift32 : ImmLeaf<i8, [{ 1663 return countTrailingOnes<uint64_t>(Imm) >= 5; 1664}]>; 1665def immShift64 : ImmLeaf<i8, [{ 1666 return countTrailingOnes<uint64_t>(Imm) >= 6; 1667}]>; 1668 1669// Shift amount is implicitly masked. 1670multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1671 // (shift x (and y, 31)) ==> (shift x, y) 1672 def : Pat<(frag GR8:$src1, (and CL, immShift32)), 1673 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1674 def : Pat<(frag GR16:$src1, (and CL, immShift32)), 1675 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1676 def : Pat<(frag GR32:$src1, (and CL, immShift32)), 1677 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1678 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1679 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1680 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1681 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1682 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1683 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1684 1685 // (shift x (and y, 63)) ==> (shift x, y) 1686 def : Pat<(frag GR64:$src1, (and CL, immShift64)), 1687 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1688 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1689 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1690} 1691 1692defm : MaskedShiftAmountPats<shl, "SHL">; 1693defm : MaskedShiftAmountPats<srl, "SHR">; 1694defm : MaskedShiftAmountPats<sra, "SAR">; 1695defm : MaskedShiftAmountPats<rotl, "ROL">; 1696defm : MaskedShiftAmountPats<rotr, "ROR">; 1697 1698// (anyext (setcc_carry)) -> (setcc_carry) 1699def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1700 (SETB_C16r)>; 1701def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1702 (SETB_C32r)>; 1703def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1704 (SETB_C32r)>; 1705 1706 1707 1708 1709//===----------------------------------------------------------------------===// 1710// EFLAGS-defining Patterns 1711//===----------------------------------------------------------------------===// 1712 1713// add reg, reg 1714def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1715def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1716def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1717 1718// add reg, mem 1719def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1720 (ADD8rm GR8:$src1, addr:$src2)>; 1721def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1722 (ADD16rm GR16:$src1, addr:$src2)>; 1723def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1724 (ADD32rm GR32:$src1, addr:$src2)>; 1725 1726// add reg, imm 1727def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1728def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1729def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1730def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1731 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1732def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1733 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1734 1735// sub reg, reg 1736def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1737def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1738def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1739 1740// sub reg, mem 1741def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1742 (SUB8rm GR8:$src1, addr:$src2)>; 1743def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1744 (SUB16rm GR16:$src1, addr:$src2)>; 1745def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1746 (SUB32rm GR32:$src1, addr:$src2)>; 1747 1748// sub reg, imm 1749def : Pat<(sub GR8:$src1, imm:$src2), 1750 (SUB8ri GR8:$src1, imm:$src2)>; 1751def : Pat<(sub GR16:$src1, imm:$src2), 1752 (SUB16ri GR16:$src1, imm:$src2)>; 1753def : Pat<(sub GR32:$src1, imm:$src2), 1754 (SUB32ri GR32:$src1, imm:$src2)>; 1755def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1756 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1757def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1758 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1759 1760// sub 0, reg 1761def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1762def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1763def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1764def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1765 1766// mul reg, reg 1767def : Pat<(mul GR16:$src1, GR16:$src2), 1768 (IMUL16rr GR16:$src1, GR16:$src2)>; 1769def : Pat<(mul GR32:$src1, GR32:$src2), 1770 (IMUL32rr GR32:$src1, GR32:$src2)>; 1771 1772// mul reg, mem 1773def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1774 (IMUL16rm GR16:$src1, addr:$src2)>; 1775def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1776 (IMUL32rm GR32:$src1, addr:$src2)>; 1777 1778// mul reg, imm 1779def : Pat<(mul GR16:$src1, imm:$src2), 1780 (IMUL16rri GR16:$src1, imm:$src2)>; 1781def : Pat<(mul GR32:$src1, imm:$src2), 1782 (IMUL32rri GR32:$src1, imm:$src2)>; 1783def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1784 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1785def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1786 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1787 1788// reg = mul mem, imm 1789def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1790 (IMUL16rmi addr:$src1, imm:$src2)>; 1791def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1792 (IMUL32rmi addr:$src1, imm:$src2)>; 1793def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1794 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1795def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1796 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1797 1798// Patterns for nodes that do not produce flags, for instructions that do. 1799 1800// addition 1801def : Pat<(add GR64:$src1, GR64:$src2), 1802 (ADD64rr GR64:$src1, GR64:$src2)>; 1803def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1804 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1805def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1806 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1807def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1808 (ADD64rm GR64:$src1, addr:$src2)>; 1809 1810// subtraction 1811def : Pat<(sub GR64:$src1, GR64:$src2), 1812 (SUB64rr GR64:$src1, GR64:$src2)>; 1813def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1814 (SUB64rm GR64:$src1, addr:$src2)>; 1815def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1816 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1817def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1818 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1819 1820// Multiply 1821def : Pat<(mul GR64:$src1, GR64:$src2), 1822 (IMUL64rr GR64:$src1, GR64:$src2)>; 1823def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1824 (IMUL64rm GR64:$src1, addr:$src2)>; 1825def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1826 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1827def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1828 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1829def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1830 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1831def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1832 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1833 1834// Increment/Decrement reg. 1835// Do not make INC/DEC if it is slow 1836let Predicates = [NotSlowIncDec] in { 1837 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 1838 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 1839 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 1840 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1841 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 1842 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 1843 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 1844 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1845} 1846 1847// or reg/reg. 1848def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1849def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1850def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1851def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1852 1853// or reg/mem 1854def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1855 (OR8rm GR8:$src1, addr:$src2)>; 1856def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1857 (OR16rm GR16:$src1, addr:$src2)>; 1858def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1859 (OR32rm GR32:$src1, addr:$src2)>; 1860def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1861 (OR64rm GR64:$src1, addr:$src2)>; 1862 1863// or reg/imm 1864def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1865def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1866def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1867def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1868 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1869def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1870 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1871def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1872 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1873def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1874 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1875 1876// xor reg/reg 1877def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1878def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1879def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1880def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1881 1882// xor reg/mem 1883def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1884 (XOR8rm GR8:$src1, addr:$src2)>; 1885def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1886 (XOR16rm GR16:$src1, addr:$src2)>; 1887def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1888 (XOR32rm GR32:$src1, addr:$src2)>; 1889def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1890 (XOR64rm GR64:$src1, addr:$src2)>; 1891 1892// xor reg/imm 1893def : Pat<(xor GR8:$src1, imm:$src2), 1894 (XOR8ri GR8:$src1, imm:$src2)>; 1895def : Pat<(xor GR16:$src1, imm:$src2), 1896 (XOR16ri GR16:$src1, imm:$src2)>; 1897def : Pat<(xor GR32:$src1, imm:$src2), 1898 (XOR32ri GR32:$src1, imm:$src2)>; 1899def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1900 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1901def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1902 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1903def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1904 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1905def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1906 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1907 1908// and reg/reg 1909def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1910def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1911def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1912def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1913 1914// and reg/mem 1915def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1916 (AND8rm GR8:$src1, addr:$src2)>; 1917def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1918 (AND16rm GR16:$src1, addr:$src2)>; 1919def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1920 (AND32rm GR32:$src1, addr:$src2)>; 1921def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1922 (AND64rm GR64:$src1, addr:$src2)>; 1923 1924// and reg/imm 1925def : Pat<(and GR8:$src1, imm:$src2), 1926 (AND8ri GR8:$src1, imm:$src2)>; 1927def : Pat<(and GR16:$src1, imm:$src2), 1928 (AND16ri GR16:$src1, imm:$src2)>; 1929def : Pat<(and GR32:$src1, imm:$src2), 1930 (AND32ri GR32:$src1, imm:$src2)>; 1931def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1932 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1933def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1934 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1935def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1936 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1937def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1938 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1939 1940// Bit scan instruction patterns to match explicit zero-undef behavior. 1941def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1942def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1943def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1944def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1945def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1946def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1947 1948// When HasMOVBE is enabled it is possible to get a non-legalized 1949// register-register 16 bit bswap. This maps it to a ROL instruction. 1950let Predicates = [HasMOVBE] in { 1951 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 1952} 1953