1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N)); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N)); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 47 "#ADJCALLSTACKDOWN", 48 []>, 49 Requires<[NotLP64]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[NotLP64]>; 54} 55def : Pat<(X86callseq_start timm:$amt1), 56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>; 57 58 59// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 60// a stack adjustment and the codegen must know that they may modify the stack 61// pointer before prolog-epilog rewriting occurs. 62// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 63// sub / add which can clobber EFLAGS. 64let Defs = [RSP, EFLAGS], Uses = [RSP] in { 65def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 66 "#ADJCALLSTACKDOWN", 67 []>, 68 Requires<[IsLP64]>; 69def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 70 "#ADJCALLSTACKUP", 71 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 72 Requires<[IsLP64]>; 73} 74def : Pat<(X86callseq_start timm:$amt1), 75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>; 76 77 78// x86-64 va_start lowering magic. 79let usesCustomInserter = 1, Defs = [EFLAGS] in { 80def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 81 (outs), 82 (ins GR8:$al, 83 i64imm:$regsavefi, i64imm:$offset, 84 variable_ops), 85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 86 [(X86vastart_save_xmm_regs GR8:$al, 87 imm:$regsavefi, 88 imm:$offset), 89 (implicit EFLAGS)]>; 90 91// The VAARG_64 pseudo-instruction takes the address of the va_list, 92// and places the address of the next argument into a register. 93let Defs = [EFLAGS] in 94def VAARG_64 : I<0, Pseudo, 95 (outs GR64:$dst), 96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 97 "#VAARG_64 $dst, $ap, $size, $mode, $align", 98 [(set GR64:$dst, 99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 100 (implicit EFLAGS)]>; 101 102// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 103// targets. These calls are needed to probe the stack when allocating more than 104// 4k bytes in one go. Touching the stack at 4K increments is necessary to 105// ensure that the guard pages used by the OS virtual memory manager are 106// allocated in correct sequence. 107// The main point of having separate instruction are extra unmodelled effects 108// (compared to ordinary calls) like stack pointer change. 109 110let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 112 "# dynamic stack allocation", 113 [(X86WinAlloca)]>; 114 115// When using segmented stacks these are lowered into instructions which first 116// check if the current stacklet has enough free memory. If it does, memory is 117// allocated by bumping the stack pointer. Otherwise memory is allocated from 118// the heap. 119 120let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 121def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 122 "# variable sized alloca for segmented stacks", 123 [(set GR32:$dst, 124 (X86SegAlloca GR32:$size))]>, 125 Requires<[NotLP64]>; 126 127let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 128def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 129 "# variable sized alloca for segmented stacks", 130 [(set GR64:$dst, 131 (X86SegAlloca GR64:$size))]>, 132 Requires<[In64BitMode]>; 133} 134 135//===----------------------------------------------------------------------===// 136// EH Pseudo Instructions 137// 138let SchedRW = [WriteSystem] in { 139let isTerminator = 1, isReturn = 1, isBarrier = 1, 140 hasCtrlDep = 1, isCodeGenOnly = 1 in { 141def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 142 "ret\t#eh_return, addr: $addr", 143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 144 145} 146 147let isTerminator = 1, isReturn = 1, isBarrier = 1, 148 hasCtrlDep = 1, isCodeGenOnly = 1 in { 149def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 150 "ret\t#eh_return, addr: $addr", 151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 152 153} 154 155let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 156 isCodeGenOnly = 1, isReturn = 1 in { 157 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 158 159 // CATCHRET needs a custom inserter for SEH. 160 let usesCustomInserter = 1 in 161 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 162 "# CATCHRET", 163 [(catchret bb:$dst, bb:$from)]>; 164} 165 166let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, 167 usesCustomInserter = 1 in 168def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>; 169 170// This instruction is responsible for re-establishing stack pointers after an 171// exception has been caught and we are rejoining normal control flow in the 172// parent function or funclet. It generally sets ESP and EBP, and optionally 173// ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us 174// elsewhere. 175let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in 176def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>; 177 178let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 179 usesCustomInserter = 1 in { 180 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 181 "#EH_SJLJ_SETJMP32", 182 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 183 Requires<[Not64BitMode]>; 184 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 185 "#EH_SJLJ_SETJMP64", 186 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 187 Requires<[In64BitMode]>; 188 let isTerminator = 1 in { 189 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 190 "#EH_SJLJ_LONGJMP32", 191 [(X86eh_sjlj_longjmp addr:$buf)]>, 192 Requires<[Not64BitMode]>; 193 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 194 "#EH_SJLJ_LONGJMP64", 195 [(X86eh_sjlj_longjmp addr:$buf)]>, 196 Requires<[In64BitMode]>; 197 } 198} 199} // SchedRW 200 201let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 202 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 203 "#EH_SjLj_Setup\t$dst", []>; 204} 205 206//===----------------------------------------------------------------------===// 207// Pseudo instructions used by unwind info. 208// 209let isPseudo = 1 in { 210 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 211 "#SEH_PushReg $reg", []>; 212 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 213 "#SEH_SaveReg $reg, $dst", []>; 214 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 215 "#SEH_SaveXMM $reg, $dst", []>; 216 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 217 "#SEH_StackAlloc $size", []>; 218 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 219 "#SEH_SetFrame $reg, $offset", []>; 220 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 221 "#SEH_PushFrame $mode", []>; 222 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 223 "#SEH_EndPrologue", []>; 224 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 225 "#SEH_Epilogue", []>; 226} 227 228//===----------------------------------------------------------------------===// 229// Pseudo instructions used by segmented stacks. 230// 231 232// This is lowered into a RET instruction by MCInstLower. We need 233// this so that we don't have to have a MachineBasicBlock which ends 234// with a RET and also has successors. 235let isPseudo = 1 in { 236def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 237 "", []>; 238 239// This instruction is lowered to a RET followed by a MOV. The two 240// instructions are not generated on a higher level since then the 241// verifier sees a MachineBasicBlock ending with a non-terminator. 242def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 243 "", []>; 244} 245 246//===----------------------------------------------------------------------===// 247// Alias Instructions 248//===----------------------------------------------------------------------===// 249 250// Alias instruction mapping movr0 to xor. 251// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 252let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 253 isPseudo = 1 in 254def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 255 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>; 256 257// Other widths can also make use of the 32-bit xor, which may have a smaller 258// encoding and avoid partial register updates. 259def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 260def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 261def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> { 262 let AddedComplexity = 20; 263} 264 265let Predicates = [OptForSize, NotSlowIncDec, Not64BitMode], 266 AddedComplexity = 1 in { 267 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 268 // which only require 3 bytes compared to MOV32ri which requires 5. 269 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 270 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 271 [(set GR32:$dst, 1)]>; 272 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 273 [(set GR32:$dst, -1)]>; 274 } 275 276 // MOV16ri is 4 bytes, so the instructions above are smaller. 277 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 278 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 279} 280 281// Materialize i64 constant where top 32-bits are zero. This could theoretically 282// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 283// that would make it more difficult to rematerialize. 284let isReMaterializable = 1, isAsCheapAsAMove = 1, 285 isPseudo = 1, hasSideEffects = 0 in 286def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>; 287 288// This 64-bit pseudo-move can be used for both a 64-bit constant that is 289// actually the zero-extension of a 32-bit constant and for labels in the 290// x86-64 small code model. 291def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>; 292 293let AddedComplexity = 1 in 294def : Pat<(i64 mov64imm32:$src), 295 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; 296 297// Use sbb to materialize carry bit. 298let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { 299// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 300// However, Pat<> can't replicate the destination reg into the inputs of the 301// result. 302def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 303 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 304def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 305 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 306def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 307 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 308def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 309 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 310} // isCodeGenOnly 311 312 313def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 314 (SETB_C16r)>; 315def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 316 (SETB_C32r)>; 317def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 318 (SETB_C64r)>; 319 320def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 321 (SETB_C16r)>; 322def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 323 (SETB_C32r)>; 324def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 325 (SETB_C64r)>; 326 327// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 328// will be eliminated and that the sbb can be extended up to a wider type. When 329// this happens, it is great. However, if we are left with an 8-bit sbb and an 330// and, we might as well just match it as a setb. 331def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 332 (SETBr)>; 333 334// (add OP, SETB) -> (adc OP, 0) 335def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 336 (ADC8ri GR8:$op, 0)>; 337def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 338 (ADC32ri8 GR32:$op, 0)>; 339def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 340 (ADC64ri8 GR64:$op, 0)>; 341 342// (sub OP, SETB) -> (sbb OP, 0) 343def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 344 (SBB8ri GR8:$op, 0)>; 345def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 346 (SBB32ri8 GR32:$op, 0)>; 347def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 348 (SBB64ri8 GR64:$op, 0)>; 349 350// (sub OP, SETCC_CARRY) -> (adc OP, 0) 351def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 352 (ADC8ri GR8:$op, 0)>; 353def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 354 (ADC32ri8 GR32:$op, 0)>; 355def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 356 (ADC64ri8 GR64:$op, 0)>; 357 358//===----------------------------------------------------------------------===// 359// String Pseudo Instructions 360// 361let SchedRW = [WriteMicrocoded] in { 362let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 363def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 364 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 365 Requires<[Not64BitMode]>; 366def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 367 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 368 Requires<[Not64BitMode]>; 369def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 370 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 371 Requires<[Not64BitMode]>; 372} 373 374let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 375def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 376 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 377 Requires<[In64BitMode]>; 378def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 379 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 380 Requires<[In64BitMode]>; 381def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 382 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 383 Requires<[In64BitMode]>; 384def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 385 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 386 Requires<[In64BitMode]>; 387} 388 389// FIXME: Should use "(X86rep_stos AL)" as the pattern. 390let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 391 let Uses = [AL,ECX,EDI] in 392 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 393 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 394 Requires<[Not64BitMode]>; 395 let Uses = [AX,ECX,EDI] in 396 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 397 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 398 Requires<[Not64BitMode]>; 399 let Uses = [EAX,ECX,EDI] in 400 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 401 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 402 Requires<[Not64BitMode]>; 403} 404 405let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 406 let Uses = [AL,RCX,RDI] in 407 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 408 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 409 Requires<[In64BitMode]>; 410 let Uses = [AX,RCX,RDI] in 411 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 412 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 413 Requires<[In64BitMode]>; 414 let Uses = [RAX,RCX,RDI] in 415 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 416 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 417 Requires<[In64BitMode]>; 418 419 let Uses = [RAX,RCX,RDI] in 420 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 421 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 422 Requires<[In64BitMode]>; 423} 424} // SchedRW 425 426//===----------------------------------------------------------------------===// 427// Thread Local Storage Instructions 428// 429 430// ELF TLS Support 431// All calls clobber the non-callee saved registers. ESP is marked as 432// a use to prevent stack-pointer assignments that appear immediately 433// before calls from potentially appearing dead. 434let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 435 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 436 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 437 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 438 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 439 usesCustomInserter = 1, Uses = [ESP] in { 440def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 441 "# TLS_addr32", 442 [(X86tlsaddr tls32addr:$sym)]>, 443 Requires<[Not64BitMode]>; 444def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 445 "# TLS_base_addr32", 446 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 447 Requires<[Not64BitMode]>; 448} 449 450// All calls clobber the non-callee saved registers. RSP is marked as 451// a use to prevent stack-pointer assignments that appear immediately 452// before calls from potentially appearing dead. 453let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 454 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 455 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 456 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 457 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 458 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 459 usesCustomInserter = 1, Uses = [RSP] in { 460def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 461 "# TLS_addr64", 462 [(X86tlsaddr tls64addr:$sym)]>, 463 Requires<[In64BitMode]>; 464def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 465 "# TLS_base_addr64", 466 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 467 Requires<[In64BitMode]>; 468} 469 470// Darwin TLS Support 471// For i386, the address of the thunk is passed on the stack, on return the 472// address of the variable is in %eax. %ecx is trashed during the function 473// call. All other registers are preserved. 474let Defs = [EAX, ECX, EFLAGS], 475 Uses = [ESP], 476 usesCustomInserter = 1 in 477def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 478 "# TLSCall_32", 479 [(X86TLSCall addr:$sym)]>, 480 Requires<[Not64BitMode]>; 481 482// For x86_64, the address of the thunk is passed in %rdi, on return 483// the address of the variable is in %rax. All other registers are preserved. 484let Defs = [RAX, EFLAGS], 485 Uses = [RSP, RDI], 486 usesCustomInserter = 1 in 487def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 488 "# TLSCall_64", 489 [(X86TLSCall addr:$sym)]>, 490 Requires<[In64BitMode]>; 491 492 493//===----------------------------------------------------------------------===// 494// Conditional Move Pseudo Instructions 495 496// CMOV* - Used to implement the SELECT DAG operation. Expanded after 497// instruction selection into a branch sequence. 498multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 499 def CMOV#NAME : I<0, Pseudo, 500 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 501 "#CMOV_"#NAME#" PSEUDO!", 502 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond, 503 EFLAGS)))]>; 504} 505 506let usesCustomInserter = 1, Uses = [EFLAGS] in { 507 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 508 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 509 // however that requires promoting the operands, and can induce additional 510 // i8 register pressure. 511 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 512 513 let Predicates = [NoCMov] in { 514 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 515 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 516 } // Predicates = [NoCMov] 517 518 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 519 // SSE1/SSE2. 520 let Predicates = [FPStackf32] in 521 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 522 523 let Predicates = [FPStackf64] in 524 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 525 526 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 527 528 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 529 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 530 defm _FR128 : CMOVrr_PSEUDO<FR128, f128>; 531 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>; 532 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>; 533 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>; 534 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>; 535 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>; 536 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>; 537 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>; 538 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>; 539 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>; 540 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>; 541 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>; 542 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>; 543 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>; 544} // usesCustomInserter = 1, Uses = [EFLAGS] 545 546//===----------------------------------------------------------------------===// 547// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 548//===----------------------------------------------------------------------===// 549 550// FIXME: Use normal instructions and add lock prefix dynamically. 551 552// Memory barriers 553 554// TODO: Get this to fold the constant into the instruction. 555let isCodeGenOnly = 1, Defs = [EFLAGS] in 556def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 557 "or{l}\t{$zero, $dst|$dst, $zero}", [], 558 IIC_ALU_MEM>, Requires<[Not64BitMode]>, OpSize32, LOCK, 559 Sched<[WriteALULd, WriteRMW]>; 560 561let hasSideEffects = 1 in 562def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 563 "#MEMBARRIER", 564 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 565 566// RegOpc corresponds to the mr version of the instruction 567// ImmOpc corresponds to the mi version of the instruction 568// ImmOpc8 corresponds to the mi8 version of the instruction 569// ImmMod corresponds to the instruction format of the mi and mi8 versions 570multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 571 Format ImmMod, string mnemonic> { 572let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 573 SchedRW = [WriteALULd, WriteRMW] in { 574 575def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 576 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 577 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 578 !strconcat(mnemonic, "{b}\t", 579 "{$src2, $dst|$dst, $src2}"), 580 [], IIC_ALU_NONMEM>, LOCK; 581def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 582 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 583 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 584 !strconcat(mnemonic, "{w}\t", 585 "{$src2, $dst|$dst, $src2}"), 586 [], IIC_ALU_NONMEM>, OpSize16, LOCK; 587def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 588 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 589 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 590 !strconcat(mnemonic, "{l}\t", 591 "{$src2, $dst|$dst, $src2}"), 592 [], IIC_ALU_NONMEM>, OpSize32, LOCK; 593def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 594 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 595 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 596 !strconcat(mnemonic, "{q}\t", 597 "{$src2, $dst|$dst, $src2}"), 598 [], IIC_ALU_NONMEM>, LOCK; 599 600def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 601 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 602 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 603 !strconcat(mnemonic, "{b}\t", 604 "{$src2, $dst|$dst, $src2}"), 605 [], IIC_ALU_MEM>, LOCK; 606 607def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 608 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 609 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 610 !strconcat(mnemonic, "{w}\t", 611 "{$src2, $dst|$dst, $src2}"), 612 [], IIC_ALU_MEM>, OpSize16, LOCK; 613 614def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 615 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 616 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 617 !strconcat(mnemonic, "{l}\t", 618 "{$src2, $dst|$dst, $src2}"), 619 [], IIC_ALU_MEM>, OpSize32, LOCK; 620 621def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 622 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 623 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 624 !strconcat(mnemonic, "{q}\t", 625 "{$src2, $dst|$dst, $src2}"), 626 [], IIC_ALU_MEM>, LOCK; 627 628def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 629 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 630 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 631 !strconcat(mnemonic, "{w}\t", 632 "{$src2, $dst|$dst, $src2}"), 633 [], IIC_ALU_MEM>, OpSize16, LOCK; 634def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 635 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 636 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 637 !strconcat(mnemonic, "{l}\t", 638 "{$src2, $dst|$dst, $src2}"), 639 [], IIC_ALU_MEM>, OpSize32, LOCK; 640def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 641 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 642 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 643 !strconcat(mnemonic, "{q}\t", 644 "{$src2, $dst|$dst, $src2}"), 645 [], IIC_ALU_MEM>, LOCK; 646 647} 648 649} 650 651defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; 652defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; 653defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; 654defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">; 655defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">; 656 657// Optimized codegen when the non-memory output is not used. 658multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 659 string mnemonic> { 660let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 661 SchedRW = [WriteALULd, WriteRMW] in { 662 663def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 664 !strconcat(mnemonic, "{b}\t$dst"), 665 [], IIC_UNARY_MEM>, LOCK; 666def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 667 !strconcat(mnemonic, "{w}\t$dst"), 668 [], IIC_UNARY_MEM>, OpSize16, LOCK; 669def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 670 !strconcat(mnemonic, "{l}\t$dst"), 671 [], IIC_UNARY_MEM>, OpSize32, LOCK; 672def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 673 !strconcat(mnemonic, "{q}\t$dst"), 674 [], IIC_UNARY_MEM>, LOCK; 675} 676} 677 678defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">; 679defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">; 680 681// Atomic compare and swap. 682multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 683 SDPatternOperator frag, X86MemOperand x86memop, 684 InstrItinClass itin> { 685let isCodeGenOnly = 1 in { 686 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 687 !strconcat(mnemonic, "\t$ptr"), 688 [(frag addr:$ptr)], itin>, TB, LOCK; 689} 690} 691 692multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 693 string mnemonic, SDPatternOperator frag, 694 InstrItinClass itin8, InstrItinClass itin> { 695let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { 696 let Defs = [AL, EFLAGS], Uses = [AL] in 697 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 698 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 699 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 700 let Defs = [AX, EFLAGS], Uses = [AX] in 701 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 702 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 703 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK; 704 let Defs = [EAX, EFLAGS], Uses = [EAX] in 705 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 706 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 707 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK; 708 let Defs = [RAX, EFLAGS], Uses = [RAX] in 709 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 710 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 711 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 712} 713} 714 715let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 716 SchedRW = [WriteALULd, WriteRMW] in { 717defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 718 X86cas8, i64mem, 719 IIC_CMPX_LOCK_8B>; 720} 721 722let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 723 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { 724defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 725 X86cas16, i128mem, 726 IIC_CMPX_LOCK_16B>, REX_W; 727} 728 729defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 730 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 731 732// Atomic exchange and add 733multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 734 string frag, 735 InstrItinClass itin8, InstrItinClass itin> { 736 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, 737 SchedRW = [WriteALULd, WriteRMW] in { 738 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 739 (ins GR8:$val, i8mem:$ptr), 740 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 741 [(set GR8:$dst, 742 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 743 itin8>; 744 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 745 (ins GR16:$val, i16mem:$ptr), 746 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 747 [(set 748 GR16:$dst, 749 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 750 itin>, OpSize16; 751 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 752 (ins GR32:$val, i32mem:$ptr), 753 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 754 [(set 755 GR32:$dst, 756 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 757 itin>, OpSize32; 758 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 759 (ins GR64:$val, i64mem:$ptr), 760 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 761 [(set 762 GR64:$dst, 763 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 764 itin>; 765 } 766} 767 768defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 769 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 770 TB, LOCK; 771 772/* The following multiclass tries to make sure that in code like 773 * x.store (immediate op x.load(acquire), release) 774 * and 775 * x.store (register op x.load(acquire), release) 776 * an operation directly on memory is generated instead of wasting a register. 777 * It is not automatic as atomic_store/load are only lowered to MOV instructions 778 * extremely late to prevent them from being accidentally reordered in the backend 779 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 780 */ 781multiclass RELEASE_BINOP_MI<SDNode op> { 782 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 783 "#BINOP "#NAME#"8mi PSEUDO!", 784 [(atomic_store_8 addr:$dst, (op 785 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>; 786 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src), 787 "#BINOP "#NAME#"8mr PSEUDO!", 788 [(atomic_store_8 addr:$dst, (op 789 (atomic_load_8 addr:$dst), GR8:$src))]>; 790 // NAME#16 is not generated as 16-bit arithmetic instructions are considered 791 // costly and avoided as far as possible by this backend anyway 792 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 793 "#BINOP "#NAME#"32mi PSEUDO!", 794 [(atomic_store_32 addr:$dst, (op 795 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>; 796 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 797 "#BINOP "#NAME#"32mr PSEUDO!", 798 [(atomic_store_32 addr:$dst, (op 799 (atomic_load_32 addr:$dst), GR32:$src))]>; 800 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 801 "#BINOP "#NAME#"64mi32 PSEUDO!", 802 [(atomic_store_64 addr:$dst, (op 803 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>; 804 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 805 "#BINOP "#NAME#"64mr PSEUDO!", 806 [(atomic_store_64 addr:$dst, (op 807 (atomic_load_64 addr:$dst), GR64:$src))]>; 808} 809let Defs = [EFLAGS] in { 810 defm RELEASE_ADD : RELEASE_BINOP_MI<add>; 811 defm RELEASE_AND : RELEASE_BINOP_MI<and>; 812 defm RELEASE_OR : RELEASE_BINOP_MI<or>; 813 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>; 814 // Note: we don't deal with sub, because substractions of constants are 815 // optimized into additions before this code can run. 816} 817 818// Same as above, but for floating-point. 819// FIXME: imm version. 820// FIXME: Version that doesn't clobber $src, using AVX's VADDSS. 821// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 822let usesCustomInserter = 1 in { 823multiclass RELEASE_FP_BINOP_MI<SDNode op> { 824 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src), 825 "#BINOP "#NAME#"32mr PSEUDO!", 826 [(atomic_store_32 addr:$dst, 827 (i32 (bitconvert (op 828 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))), 829 FR32:$src))))]>, Requires<[HasSSE1]>; 830 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src), 831 "#BINOP "#NAME#"64mr PSEUDO!", 832 [(atomic_store_64 addr:$dst, 833 (i64 (bitconvert (op 834 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))), 835 FR64:$src))))]>, Requires<[HasSSE2]>; 836} 837defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>; 838// FIXME: Add fsub, fmul, fdiv, ... 839} 840 841multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> { 842 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst), 843 "#UNOP "#NAME#"8m PSEUDO!", 844 [(atomic_store_8 addr:$dst, dag8)]>; 845 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst), 846 "#UNOP "#NAME#"16m PSEUDO!", 847 [(atomic_store_16 addr:$dst, dag16)]>; 848 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst), 849 "#UNOP "#NAME#"32m PSEUDO!", 850 [(atomic_store_32 addr:$dst, dag32)]>; 851 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst), 852 "#UNOP "#NAME#"64m PSEUDO!", 853 [(atomic_store_64 addr:$dst, dag64)]>; 854} 855 856let Defs = [EFLAGS] in { 857 defm RELEASE_INC : RELEASE_UNOP< 858 (add (atomic_load_8 addr:$dst), (i8 1)), 859 (add (atomic_load_16 addr:$dst), (i16 1)), 860 (add (atomic_load_32 addr:$dst), (i32 1)), 861 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>; 862 defm RELEASE_DEC : RELEASE_UNOP< 863 (add (atomic_load_8 addr:$dst), (i8 -1)), 864 (add (atomic_load_16 addr:$dst), (i16 -1)), 865 (add (atomic_load_32 addr:$dst), (i32 -1)), 866 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>; 867} 868/* 869TODO: These don't work because the type inference of TableGen fails. 870TODO: find a way to fix it. 871let Defs = [EFLAGS] in { 872 defm RELEASE_NEG : RELEASE_UNOP< 873 (ineg (atomic_load_8 addr:$dst)), 874 (ineg (atomic_load_16 addr:$dst)), 875 (ineg (atomic_load_32 addr:$dst)), 876 (ineg (atomic_load_64 addr:$dst))>; 877} 878// NOT doesn't set flags. 879defm RELEASE_NOT : RELEASE_UNOP< 880 (not (atomic_load_8 addr:$dst)), 881 (not (atomic_load_16 addr:$dst)), 882 (not (atomic_load_32 addr:$dst)), 883 (not (atomic_load_64 addr:$dst))>; 884*/ 885 886def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 887 "#RELEASE_MOV8mi PSEUDO!", 888 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>; 889def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src), 890 "#RELEASE_MOV16mi PSEUDO!", 891 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>; 892def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 893 "#RELEASE_MOV32mi PSEUDO!", 894 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>; 895def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 896 "#RELEASE_MOV64mi32 PSEUDO!", 897 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>; 898 899def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 900 "#RELEASE_MOV8mr PSEUDO!", 901 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 902def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 903 "#RELEASE_MOV16mr PSEUDO!", 904 [(atomic_store_16 addr:$dst, GR16:$src)]>; 905def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 906 "#RELEASE_MOV32mr PSEUDO!", 907 [(atomic_store_32 addr:$dst, GR32:$src)]>; 908def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 909 "#RELEASE_MOV64mr PSEUDO!", 910 [(atomic_store_64 addr:$dst, GR64:$src)]>; 911 912def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 913 "#ACQUIRE_MOV8rm PSEUDO!", 914 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 915def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 916 "#ACQUIRE_MOV16rm PSEUDO!", 917 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 918def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 919 "#ACQUIRE_MOV32rm PSEUDO!", 920 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 921def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 922 "#ACQUIRE_MOV64rm PSEUDO!", 923 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 924 925//===----------------------------------------------------------------------===// 926// DAG Pattern Matching Rules 927//===----------------------------------------------------------------------===// 928 929// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 930def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 931def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 932def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 933def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 934def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 935def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>; 936def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 937 938def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 939 (ADD32ri GR32:$src1, tconstpool:$src2)>; 940def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 941 (ADD32ri GR32:$src1, tjumptable:$src2)>; 942def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 943 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 944def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 945 (ADD32ri GR32:$src1, texternalsym:$src2)>; 946def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)), 947 (ADD32ri GR32:$src1, mcsym:$src2)>; 948def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 949 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 950 951def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 952 (MOV32mi addr:$dst, tglobaladdr:$src)>; 953def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 954 (MOV32mi addr:$dst, texternalsym:$src)>; 955def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst), 956 (MOV32mi addr:$dst, mcsym:$src)>; 957def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 958 (MOV32mi addr:$dst, tblockaddress:$src)>; 959 960// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 961// code model mode, should use 'movabs'. FIXME: This is really a hack, the 962// 'movabs' predicate should handle this sort of thing. 963def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 964 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 965def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 966 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 967def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 968 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 969def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 970 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 971def : Pat<(i64 (X86Wrapper mcsym:$dst)), 972 (MOV64ri mcsym:$dst)>, Requires<[FarData]>; 973def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 974 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 975 976// In kernel code model, we can get the address of a label 977// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 978// the MOV64ri32 should accept these. 979def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 980 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 981def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 982 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 983def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 984 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 985def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 986 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 987def : Pat<(i64 (X86Wrapper mcsym:$dst)), 988 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 989def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 990 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 991 992// If we have small model and -static mode, it is safe to store global addresses 993// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 994// for MOV64mi32 should handle this sort of thing. 995def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 996 (MOV64mi32 addr:$dst, tconstpool:$src)>, 997 Requires<[NearData, IsStatic]>; 998def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 999 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1000 Requires<[NearData, IsStatic]>; 1001def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1002 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1003 Requires<[NearData, IsStatic]>; 1004def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1005 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1006 Requires<[NearData, IsStatic]>; 1007def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1008 (MOV64mi32 addr:$dst, mcsym:$src)>, 1009 Requires<[NearData, IsStatic]>; 1010def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1011 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1012 Requires<[NearData, IsStatic]>; 1013 1014def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1015def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1016 1017// Calls 1018 1019// tls has some funny stuff here... 1020// This corresponds to movabs $foo@tpoff, %rax 1021def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1022 (MOV64ri32 tglobaltlsaddr :$dst)>; 1023// This corresponds to add $foo@tpoff, %rax 1024def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1025 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1026 1027 1028// Direct PC relative function call for small code model. 32-bit displacement 1029// sign extended to 64-bit. 1030def : Pat<(X86call (i64 tglobaladdr:$dst)), 1031 (CALL64pcrel32 tglobaladdr:$dst)>; 1032def : Pat<(X86call (i64 texternalsym:$dst)), 1033 (CALL64pcrel32 texternalsym:$dst)>; 1034 1035// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1036// can never use callee-saved registers. That is the purpose of the GR64_TC 1037// register classes. 1038// 1039// The only volatile register that is never used by the calling convention is 1040// %r11. This happens when calling a vararg function with 6 arguments. 1041// 1042// Match an X86tcret that uses less than 7 volatile registers. 1043def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1044 (X86tcret node:$ptr, node:$off), [{ 1045 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1046 unsigned NumRegs = 0; 1047 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1048 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1049 return false; 1050 return true; 1051}]>; 1052 1053def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1054 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1055 Requires<[Not64BitMode]>; 1056 1057// FIXME: This is disabled for 32-bit PIC mode because the global base 1058// register which is part of the address mode may be assigned a 1059// callee-saved register. 1060def : Pat<(X86tcret (load addr:$dst), imm:$off), 1061 (TCRETURNmi addr:$dst, imm:$off)>, 1062 Requires<[Not64BitMode, IsNotPIC]>; 1063 1064def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1065 (TCRETURNdi tglobaladdr:$dst, imm:$off)>, 1066 Requires<[NotLP64]>; 1067 1068def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1069 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1070 Requires<[NotLP64]>; 1071 1072def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1073 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1074 Requires<[In64BitMode]>; 1075 1076// Don't fold loads into X86tcret requiring more than 6 regs. 1077// There wouldn't be enough scratch registers for base+index. 1078def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1079 (TCRETURNmi64 addr:$dst, imm:$off)>, 1080 Requires<[In64BitMode]>; 1081 1082def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1083 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1084 Requires<[IsLP64]>; 1085 1086def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1087 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1088 Requires<[IsLP64]>; 1089 1090// Normal calls, with various flavors of addresses. 1091def : Pat<(X86call (i32 tglobaladdr:$dst)), 1092 (CALLpcrel32 tglobaladdr:$dst)>; 1093def : Pat<(X86call (i32 texternalsym:$dst)), 1094 (CALLpcrel32 texternalsym:$dst)>; 1095def : Pat<(X86call (i32 imm:$dst)), 1096 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1097 1098// Comparisons. 1099 1100// TEST R,R is smaller than CMP R,0 1101def : Pat<(X86cmp GR8:$src1, 0), 1102 (TEST8rr GR8:$src1, GR8:$src1)>; 1103def : Pat<(X86cmp GR16:$src1, 0), 1104 (TEST16rr GR16:$src1, GR16:$src1)>; 1105def : Pat<(X86cmp GR32:$src1, 0), 1106 (TEST32rr GR32:$src1, GR32:$src1)>; 1107def : Pat<(X86cmp GR64:$src1, 0), 1108 (TEST64rr GR64:$src1, GR64:$src1)>; 1109 1110// Conditional moves with folded loads with operands swapped and conditions 1111// inverted. 1112multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1113 Instruction Inst64> { 1114 let Predicates = [HasCMov] in { 1115 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1116 (Inst16 GR16:$src2, addr:$src1)>; 1117 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1118 (Inst32 GR32:$src2, addr:$src1)>; 1119 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1120 (Inst64 GR64:$src2, addr:$src1)>; 1121 } 1122} 1123 1124defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1125defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1126defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1127defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1128defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1129defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1130defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1131defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1132defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1133defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1134defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1135defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1136defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1137defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1138defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1139defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1140 1141// zextload bool -> zextload byte 1142// i1 stored in one byte in zero-extended form. 1143// Upper bits cleanup should be executed before Store. 1144def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1145def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1146def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1147def : Pat<(zextloadi64i1 addr:$src), 1148 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1149 1150// extload bool -> extload byte 1151// When extloading from 16-bit and smaller memory locations into 64-bit 1152// registers, use zero-extending loads so that the entire 64-bit register is 1153// defined, avoiding partial-register updates. 1154 1155def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1156def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1157def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1158def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1159def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1160def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1161 1162// For other extloads, use subregs, since the high contents of the register are 1163// defined after an extload. 1164def : Pat<(extloadi64i1 addr:$src), 1165 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1166def : Pat<(extloadi64i8 addr:$src), 1167 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1168def : Pat<(extloadi64i16 addr:$src), 1169 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1170def : Pat<(extloadi64i32 addr:$src), 1171 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1172 1173// anyext. Define these to do an explicit zero-extend to 1174// avoid partial-register updates. 1175def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1176 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1177def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1178 1179// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1180def : Pat<(i32 (anyext GR16:$src)), 1181 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1182 1183def : Pat<(i64 (anyext GR8 :$src)), 1184 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1185def : Pat<(i64 (anyext GR16:$src)), 1186 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1187def : Pat<(i64 (anyext GR32:$src)), 1188 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1189 1190 1191// Any instruction that defines a 32-bit result leaves the high half of the 1192// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1193// be copying from a truncate. And x86's cmov doesn't do anything if the 1194// condition is false. But any other 32-bit operation will zero-extend 1195// up to 64 bits. 1196def def32 : PatLeaf<(i32 GR32:$src), [{ 1197 return N->getOpcode() != ISD::TRUNCATE && 1198 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1199 N->getOpcode() != ISD::CopyFromReg && 1200 N->getOpcode() != ISD::AssertSext && 1201 N->getOpcode() != X86ISD::CMOV; 1202}]>; 1203 1204// In the case of a 32-bit def that is known to implicitly zero-extend, 1205// we can use a SUBREG_TO_REG. 1206def : Pat<(i64 (zext def32:$src)), 1207 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1208 1209//===----------------------------------------------------------------------===// 1210// Pattern match OR as ADD 1211//===----------------------------------------------------------------------===// 1212 1213// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1214// 3-addressified into an LEA instruction to avoid copies. However, we also 1215// want to finally emit these instructions as an or at the end of the code 1216// generator to make the generated code easier to read. To do this, we select 1217// into "disjoint bits" pseudo ops. 1218 1219// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1220def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1221 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1222 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1223 1224 APInt KnownZero0, KnownOne0; 1225 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1226 APInt KnownZero1, KnownOne1; 1227 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1228 return (~KnownZero0 & ~KnownZero1) == 0; 1229}]>; 1230 1231 1232// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1233// Try this before the selecting to OR. 1234let AddedComplexity = 5, SchedRW = [WriteALU] in { 1235 1236let isConvertibleToThreeAddress = 1, 1237 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1238let isCommutable = 1 in { 1239def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1240 "", // orw/addw REG, REG 1241 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1242def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1243 "", // orl/addl REG, REG 1244 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1245def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1246 "", // orq/addq REG, REG 1247 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1248} // isCommutable 1249 1250// NOTE: These are order specific, we want the ri8 forms to be listed 1251// first so that they are slightly preferred to the ri forms. 1252 1253def ADD16ri8_DB : I<0, Pseudo, 1254 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1255 "", // orw/addw REG, imm8 1256 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1257def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1258 "", // orw/addw REG, imm 1259 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1260 1261def ADD32ri8_DB : I<0, Pseudo, 1262 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1263 "", // orl/addl REG, imm8 1264 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1265def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1266 "", // orl/addl REG, imm 1267 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1268 1269 1270def ADD64ri8_DB : I<0, Pseudo, 1271 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1272 "", // orq/addq REG, imm8 1273 [(set GR64:$dst, (or_is_add GR64:$src1, 1274 i64immSExt8:$src2))]>; 1275def ADD64ri32_DB : I<0, Pseudo, 1276 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1277 "", // orq/addq REG, imm 1278 [(set GR64:$dst, (or_is_add GR64:$src1, 1279 i64immSExt32:$src2))]>; 1280} 1281} // AddedComplexity, SchedRW 1282 1283 1284//===----------------------------------------------------------------------===// 1285// Some peepholes 1286//===----------------------------------------------------------------------===// 1287 1288// Odd encoding trick: -128 fits into an 8-bit immediate field while 1289// +128 doesn't, so in this special case use a sub instead of an add. 1290def : Pat<(add GR16:$src1, 128), 1291 (SUB16ri8 GR16:$src1, -128)>; 1292def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1293 (SUB16mi8 addr:$dst, -128)>; 1294 1295def : Pat<(add GR32:$src1, 128), 1296 (SUB32ri8 GR32:$src1, -128)>; 1297def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1298 (SUB32mi8 addr:$dst, -128)>; 1299 1300def : Pat<(add GR64:$src1, 128), 1301 (SUB64ri8 GR64:$src1, -128)>; 1302def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1303 (SUB64mi8 addr:$dst, -128)>; 1304 1305// The same trick applies for 32-bit immediate fields in 64-bit 1306// instructions. 1307def : Pat<(add GR64:$src1, 0x0000000080000000), 1308 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1309def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1310 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1311 1312// To avoid needing to materialize an immediate in a register, use a 32-bit and 1313// with implicit zero-extension instead of a 64-bit and if the immediate has at 1314// least 32 bits of leading zeros. If in addition the last 32 bits can be 1315// represented with a sign extension of a 8 bit constant, use that. 1316// This can also reduce instruction size by eliminating the need for the REX 1317// prefix. 1318 1319// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1320let AddedComplexity = 1 in { 1321def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1322 (SUBREG_TO_REG 1323 (i64 0), 1324 (AND32ri8 1325 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1326 (i32 (GetLo8XForm imm:$imm))), 1327 sub_32bit)>; 1328 1329def : Pat<(and GR64:$src, i64immZExt32:$imm), 1330 (SUBREG_TO_REG 1331 (i64 0), 1332 (AND32ri 1333 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1334 (i32 (GetLo32XForm imm:$imm))), 1335 sub_32bit)>; 1336} // AddedComplexity = 1 1337 1338 1339// AddedComplexity is needed due to the increased complexity on the 1340// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1341// the MOVZX patterns keeps thems together in DAGIsel tables. 1342let AddedComplexity = 1 in { 1343// r & (2^16-1) ==> movz 1344def : Pat<(and GR32:$src1, 0xffff), 1345 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1346// r & (2^8-1) ==> movz 1347def : Pat<(and GR32:$src1, 0xff), 1348 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1349 GR32_ABCD)), 1350 sub_8bit))>, 1351 Requires<[Not64BitMode]>; 1352// r & (2^8-1) ==> movz 1353def : Pat<(and GR16:$src1, 0xff), 1354 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1355 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1356 sub_16bit)>, 1357 Requires<[Not64BitMode]>; 1358 1359// r & (2^32-1) ==> movz 1360def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1361 (SUBREG_TO_REG (i64 0), 1362 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1363 sub_32bit)>; 1364// r & (2^16-1) ==> movz 1365def : Pat<(and GR64:$src, 0xffff), 1366 (SUBREG_TO_REG (i64 0), 1367 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1368 sub_32bit)>; 1369// r & (2^8-1) ==> movz 1370def : Pat<(and GR64:$src, 0xff), 1371 (SUBREG_TO_REG (i64 0), 1372 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1373 sub_32bit)>; 1374// r & (2^8-1) ==> movz 1375def : Pat<(and GR32:$src1, 0xff), 1376 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1377 Requires<[In64BitMode]>; 1378// r & (2^8-1) ==> movz 1379def : Pat<(and GR16:$src1, 0xff), 1380 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1381 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1382 Requires<[In64BitMode]>; 1383} // AddedComplexity = 1 1384 1385 1386// sext_inreg patterns 1387def : Pat<(sext_inreg GR32:$src, i16), 1388 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1389def : Pat<(sext_inreg GR32:$src, i8), 1390 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1391 GR32_ABCD)), 1392 sub_8bit))>, 1393 Requires<[Not64BitMode]>; 1394 1395def : Pat<(sext_inreg GR16:$src, i8), 1396 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1397 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1398 sub_16bit)>, 1399 Requires<[Not64BitMode]>; 1400 1401def : Pat<(sext_inreg GR64:$src, i32), 1402 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1403def : Pat<(sext_inreg GR64:$src, i16), 1404 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1405def : Pat<(sext_inreg GR64:$src, i8), 1406 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1407def : Pat<(sext_inreg GR32:$src, i8), 1408 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1409 Requires<[In64BitMode]>; 1410def : Pat<(sext_inreg GR16:$src, i8), 1411 (EXTRACT_SUBREG (MOVSX32rr8 1412 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1413 Requires<[In64BitMode]>; 1414 1415// sext, sext_load, zext, zext_load 1416def: Pat<(i16 (sext GR8:$src)), 1417 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1418def: Pat<(sextloadi16i8 addr:$src), 1419 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1420def: Pat<(i16 (zext GR8:$src)), 1421 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1422def: Pat<(zextloadi16i8 addr:$src), 1423 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1424 1425// trunc patterns 1426def : Pat<(i16 (trunc GR32:$src)), 1427 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1428def : Pat<(i8 (trunc GR32:$src)), 1429 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1430 sub_8bit)>, 1431 Requires<[Not64BitMode]>; 1432def : Pat<(i8 (trunc GR16:$src)), 1433 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1434 sub_8bit)>, 1435 Requires<[Not64BitMode]>; 1436def : Pat<(i32 (trunc GR64:$src)), 1437 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1438def : Pat<(i16 (trunc GR64:$src)), 1439 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1440def : Pat<(i8 (trunc GR64:$src)), 1441 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1442def : Pat<(i8 (trunc GR32:$src)), 1443 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1444 Requires<[In64BitMode]>; 1445def : Pat<(i8 (trunc GR16:$src)), 1446 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1447 Requires<[In64BitMode]>; 1448 1449// h-register tricks 1450def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1451 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1452 sub_8bit_hi)>, 1453 Requires<[Not64BitMode]>; 1454def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1455 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1456 sub_8bit_hi)>, 1457 Requires<[Not64BitMode]>; 1458def : Pat<(srl GR16:$src, (i8 8)), 1459 (EXTRACT_SUBREG 1460 (MOVZX32rr8 1461 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1462 sub_8bit_hi)), 1463 sub_16bit)>, 1464 Requires<[Not64BitMode]>; 1465def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1466 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1467 GR16_ABCD)), 1468 sub_8bit_hi))>, 1469 Requires<[Not64BitMode]>; 1470def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1471 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1472 GR16_ABCD)), 1473 sub_8bit_hi))>, 1474 Requires<[Not64BitMode]>; 1475def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1476 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1477 GR32_ABCD)), 1478 sub_8bit_hi))>, 1479 Requires<[Not64BitMode]>; 1480def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1481 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1482 GR32_ABCD)), 1483 sub_8bit_hi))>, 1484 Requires<[Not64BitMode]>; 1485 1486// h-register tricks. 1487// For now, be conservative on x86-64 and use an h-register extract only if the 1488// value is immediately zero-extended or stored, which are somewhat common 1489// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1490// from being allocated in the same instruction as the h register, as there's 1491// currently no way to describe this requirement to the register allocator. 1492 1493// h-register extract and zero-extend. 1494def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1495 (SUBREG_TO_REG 1496 (i64 0), 1497 (MOVZX32_NOREXrr8 1498 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1499 sub_8bit_hi)), 1500 sub_32bit)>; 1501def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1502 (MOVZX32_NOREXrr8 1503 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1504 sub_8bit_hi))>, 1505 Requires<[In64BitMode]>; 1506def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1507 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1508 GR32_ABCD)), 1509 sub_8bit_hi))>, 1510 Requires<[In64BitMode]>; 1511def : Pat<(srl GR16:$src, (i8 8)), 1512 (EXTRACT_SUBREG 1513 (MOVZX32_NOREXrr8 1514 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1515 sub_8bit_hi)), 1516 sub_16bit)>, 1517 Requires<[In64BitMode]>; 1518def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1519 (MOVZX32_NOREXrr8 1520 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1521 sub_8bit_hi))>, 1522 Requires<[In64BitMode]>; 1523def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1524 (MOVZX32_NOREXrr8 1525 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1526 sub_8bit_hi))>, 1527 Requires<[In64BitMode]>; 1528def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1529 (SUBREG_TO_REG 1530 (i64 0), 1531 (MOVZX32_NOREXrr8 1532 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1533 sub_8bit_hi)), 1534 sub_32bit)>; 1535def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1536 (SUBREG_TO_REG 1537 (i64 0), 1538 (MOVZX32_NOREXrr8 1539 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1540 sub_8bit_hi)), 1541 sub_32bit)>; 1542 1543// h-register extract and store. 1544def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1545 (MOV8mr_NOREX 1546 addr:$dst, 1547 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1548 sub_8bit_hi))>; 1549def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1550 (MOV8mr_NOREX 1551 addr:$dst, 1552 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1553 sub_8bit_hi))>, 1554 Requires<[In64BitMode]>; 1555def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1556 (MOV8mr_NOREX 1557 addr:$dst, 1558 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1559 sub_8bit_hi))>, 1560 Requires<[In64BitMode]>; 1561 1562 1563// (shl x, 1) ==> (add x, x) 1564// Note that if x is undef (immediate or otherwise), we could theoretically 1565// end up with the two uses of x getting different values, producing a result 1566// where the least significant bit is not 0. However, the probability of this 1567// happening is considered low enough that this is officially not a 1568// "real problem". 1569def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1570def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1571def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1572def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1573 1574// Helper imms that check if a mask doesn't change significant shift bits. 1575def immShift32 : ImmLeaf<i8, [{ 1576 return countTrailingOnes<uint64_t>(Imm) >= 5; 1577}]>; 1578def immShift64 : ImmLeaf<i8, [{ 1579 return countTrailingOnes<uint64_t>(Imm) >= 6; 1580}]>; 1581 1582// Shift amount is implicitly masked. 1583multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1584 // (shift x (and y, 31)) ==> (shift x, y) 1585 def : Pat<(frag GR8:$src1, (and CL, immShift32)), 1586 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1587 def : Pat<(frag GR16:$src1, (and CL, immShift32)), 1588 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1589 def : Pat<(frag GR32:$src1, (and CL, immShift32)), 1590 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1591 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1592 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1593 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1594 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1595 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1596 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1597 1598 // (shift x (and y, 63)) ==> (shift x, y) 1599 def : Pat<(frag GR64:$src1, (and CL, immShift64)), 1600 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1601 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1602 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1603} 1604 1605defm : MaskedShiftAmountPats<shl, "SHL">; 1606defm : MaskedShiftAmountPats<srl, "SHR">; 1607defm : MaskedShiftAmountPats<sra, "SAR">; 1608defm : MaskedShiftAmountPats<rotl, "ROL">; 1609defm : MaskedShiftAmountPats<rotr, "ROR">; 1610 1611// (anyext (setcc_carry)) -> (setcc_carry) 1612def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1613 (SETB_C16r)>; 1614def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1615 (SETB_C32r)>; 1616def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1617 (SETB_C32r)>; 1618 1619 1620 1621 1622//===----------------------------------------------------------------------===// 1623// EFLAGS-defining Patterns 1624//===----------------------------------------------------------------------===// 1625 1626// add reg, reg 1627def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1628def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1629def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1630 1631// add reg, mem 1632def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1633 (ADD8rm GR8:$src1, addr:$src2)>; 1634def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1635 (ADD16rm GR16:$src1, addr:$src2)>; 1636def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1637 (ADD32rm GR32:$src1, addr:$src2)>; 1638 1639// add reg, imm 1640def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1641def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1642def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1643def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1644 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1645def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1646 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1647 1648// sub reg, reg 1649def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1650def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1651def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1652 1653// sub reg, mem 1654def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1655 (SUB8rm GR8:$src1, addr:$src2)>; 1656def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1657 (SUB16rm GR16:$src1, addr:$src2)>; 1658def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1659 (SUB32rm GR32:$src1, addr:$src2)>; 1660 1661// sub reg, imm 1662def : Pat<(sub GR8:$src1, imm:$src2), 1663 (SUB8ri GR8:$src1, imm:$src2)>; 1664def : Pat<(sub GR16:$src1, imm:$src2), 1665 (SUB16ri GR16:$src1, imm:$src2)>; 1666def : Pat<(sub GR32:$src1, imm:$src2), 1667 (SUB32ri GR32:$src1, imm:$src2)>; 1668def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1669 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1670def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1671 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1672 1673// sub 0, reg 1674def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1675def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1676def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1677def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1678 1679// mul reg, reg 1680def : Pat<(mul GR16:$src1, GR16:$src2), 1681 (IMUL16rr GR16:$src1, GR16:$src2)>; 1682def : Pat<(mul GR32:$src1, GR32:$src2), 1683 (IMUL32rr GR32:$src1, GR32:$src2)>; 1684 1685// mul reg, mem 1686def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1687 (IMUL16rm GR16:$src1, addr:$src2)>; 1688def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1689 (IMUL32rm GR32:$src1, addr:$src2)>; 1690 1691// mul reg, imm 1692def : Pat<(mul GR16:$src1, imm:$src2), 1693 (IMUL16rri GR16:$src1, imm:$src2)>; 1694def : Pat<(mul GR32:$src1, imm:$src2), 1695 (IMUL32rri GR32:$src1, imm:$src2)>; 1696def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1697 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1698def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1699 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1700 1701// reg = mul mem, imm 1702def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1703 (IMUL16rmi addr:$src1, imm:$src2)>; 1704def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1705 (IMUL32rmi addr:$src1, imm:$src2)>; 1706def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1707 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1708def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1709 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1710 1711// Patterns for nodes that do not produce flags, for instructions that do. 1712 1713// addition 1714def : Pat<(add GR64:$src1, GR64:$src2), 1715 (ADD64rr GR64:$src1, GR64:$src2)>; 1716def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1717 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1718def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1719 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1720def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1721 (ADD64rm GR64:$src1, addr:$src2)>; 1722 1723// subtraction 1724def : Pat<(sub GR64:$src1, GR64:$src2), 1725 (SUB64rr GR64:$src1, GR64:$src2)>; 1726def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1727 (SUB64rm GR64:$src1, addr:$src2)>; 1728def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1729 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1730def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1731 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1732 1733// Multiply 1734def : Pat<(mul GR64:$src1, GR64:$src2), 1735 (IMUL64rr GR64:$src1, GR64:$src2)>; 1736def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1737 (IMUL64rm GR64:$src1, addr:$src2)>; 1738def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1739 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1740def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1741 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1742def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1743 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1744def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1745 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1746 1747// Increment/Decrement reg. 1748// Do not make INC/DEC if it is slow 1749let Predicates = [NotSlowIncDec] in { 1750 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 1751 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 1752 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 1753 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1754 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 1755 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 1756 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 1757 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1758} 1759 1760// or reg/reg. 1761def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1762def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1763def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1764def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1765 1766// or reg/mem 1767def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1768 (OR8rm GR8:$src1, addr:$src2)>; 1769def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1770 (OR16rm GR16:$src1, addr:$src2)>; 1771def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1772 (OR32rm GR32:$src1, addr:$src2)>; 1773def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1774 (OR64rm GR64:$src1, addr:$src2)>; 1775 1776// or reg/imm 1777def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1778def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1779def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1780def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1781 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1782def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1783 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1784def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1785 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1786def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1787 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1788 1789// xor reg/reg 1790def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1791def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1792def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1793def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1794 1795// xor reg/mem 1796def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1797 (XOR8rm GR8:$src1, addr:$src2)>; 1798def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1799 (XOR16rm GR16:$src1, addr:$src2)>; 1800def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1801 (XOR32rm GR32:$src1, addr:$src2)>; 1802def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1803 (XOR64rm GR64:$src1, addr:$src2)>; 1804 1805// xor reg/imm 1806def : Pat<(xor GR8:$src1, imm:$src2), 1807 (XOR8ri GR8:$src1, imm:$src2)>; 1808def : Pat<(xor GR16:$src1, imm:$src2), 1809 (XOR16ri GR16:$src1, imm:$src2)>; 1810def : Pat<(xor GR32:$src1, imm:$src2), 1811 (XOR32ri GR32:$src1, imm:$src2)>; 1812def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1813 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1814def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1815 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1816def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1817 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1818def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1819 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1820 1821// and reg/reg 1822def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1823def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1824def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1825def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1826 1827// and reg/mem 1828def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1829 (AND8rm GR8:$src1, addr:$src2)>; 1830def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1831 (AND16rm GR16:$src1, addr:$src2)>; 1832def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1833 (AND32rm GR32:$src1, addr:$src2)>; 1834def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1835 (AND64rm GR64:$src1, addr:$src2)>; 1836 1837// and reg/imm 1838def : Pat<(and GR8:$src1, imm:$src2), 1839 (AND8ri GR8:$src1, imm:$src2)>; 1840def : Pat<(and GR16:$src1, imm:$src2), 1841 (AND16ri GR16:$src1, imm:$src2)>; 1842def : Pat<(and GR32:$src1, imm:$src2), 1843 (AND32ri GR32:$src1, imm:$src2)>; 1844def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1845 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1846def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1847 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1848def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1849 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1850def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1851 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1852 1853// Bit scan instruction patterns to match explicit zero-undef behavior. 1854def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1855def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1856def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1857def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1858def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1859def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1860 1861// When HasMOVBE is enabled it is possible to get a non-legalized 1862// register-register 16 bit bswap. This maps it to a ROL instruction. 1863let Predicates = [HasMOVBE] in { 1864 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 1865} 1866