1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N)); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N)); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 47 "#ADJCALLSTACKDOWN", 48 []>, 49 Requires<[NotLP64]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[NotLP64]>; 54} 55def : Pat<(X86callseq_start timm:$amt1), 56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>; 57 58 59// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 60// a stack adjustment and the codegen must know that they may modify the stack 61// pointer before prolog-epilog rewriting occurs. 62// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 63// sub / add which can clobber EFLAGS. 64let Defs = [RSP, EFLAGS], Uses = [RSP] in { 65def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 66 "#ADJCALLSTACKDOWN", 67 []>, 68 Requires<[IsLP64]>; 69def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 70 "#ADJCALLSTACKUP", 71 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 72 Requires<[IsLP64]>; 73} 74def : Pat<(X86callseq_start timm:$amt1), 75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>; 76 77 78// x86-64 va_start lowering magic. 79let usesCustomInserter = 1, Defs = [EFLAGS] in { 80def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 81 (outs), 82 (ins GR8:$al, 83 i64imm:$regsavefi, i64imm:$offset, 84 variable_ops), 85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 86 [(X86vastart_save_xmm_regs GR8:$al, 87 imm:$regsavefi, 88 imm:$offset), 89 (implicit EFLAGS)]>; 90 91// The VAARG_64 pseudo-instruction takes the address of the va_list, 92// and places the address of the next argument into a register. 93let Defs = [EFLAGS] in 94def VAARG_64 : I<0, Pseudo, 95 (outs GR64:$dst), 96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 97 "#VAARG_64 $dst, $ap, $size, $mode, $align", 98 [(set GR64:$dst, 99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 100 (implicit EFLAGS)]>; 101 102 103// When using segmented stacks these are lowered into instructions which first 104// check if the current stacklet has enough free memory. If it does, memory is 105// allocated by bumping the stack pointer. Otherwise memory is allocated from 106// the heap. 107 108let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 109def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 110 "# variable sized alloca for segmented stacks", 111 [(set GR32:$dst, 112 (X86SegAlloca GR32:$size))]>, 113 Requires<[NotLP64]>; 114 115let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 116def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 117 "# variable sized alloca for segmented stacks", 118 [(set GR64:$dst, 119 (X86SegAlloca GR64:$size))]>, 120 Requires<[In64BitMode]>; 121} 122 123// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 124// targets. These calls are needed to probe the stack when allocating more than 125// 4k bytes in one go. Touching the stack at 4K increments is necessary to 126// ensure that the guard pages used by the OS virtual memory manager are 127// allocated in correct sequence. 128// The main point of having separate instruction are extra unmodelled effects 129// (compared to ordinary calls) like stack pointer change. 130 131let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 132def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), 133 "# dynamic stack allocation", 134 [(X86WinAlloca GR32:$size)]>, 135 Requires<[NotLP64]>; 136 137let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 138def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), 139 "# dynamic stack allocation", 140 [(X86WinAlloca GR64:$size)]>, 141 Requires<[In64BitMode]>; 142 143 144//===----------------------------------------------------------------------===// 145// EH Pseudo Instructions 146// 147let SchedRW = [WriteSystem] in { 148let isTerminator = 1, isReturn = 1, isBarrier = 1, 149 hasCtrlDep = 1, isCodeGenOnly = 1 in { 150def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 151 "ret\t#eh_return, addr: $addr", 152 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 153 154} 155 156let isTerminator = 1, isReturn = 1, isBarrier = 1, 157 hasCtrlDep = 1, isCodeGenOnly = 1 in { 158def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 159 "ret\t#eh_return, addr: $addr", 160 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 161 162} 163 164let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 165 isCodeGenOnly = 1, isReturn = 1 in { 166 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 167 168 // CATCHRET needs a custom inserter for SEH. 169 let usesCustomInserter = 1 in 170 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 171 "# CATCHRET", 172 [(catchret bb:$dst, bb:$from)]>; 173} 174 175let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, 176 usesCustomInserter = 1 in 177def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>; 178 179// This instruction is responsible for re-establishing stack pointers after an 180// exception has been caught and we are rejoining normal control flow in the 181// parent function or funclet. It generally sets ESP and EBP, and optionally 182// ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us 183// elsewhere. 184let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in 185def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>; 186 187let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 188 usesCustomInserter = 1 in { 189 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 190 "#EH_SJLJ_SETJMP32", 191 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 192 Requires<[Not64BitMode]>; 193 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 194 "#EH_SJLJ_SETJMP64", 195 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 196 Requires<[In64BitMode]>; 197 let isTerminator = 1 in { 198 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 199 "#EH_SJLJ_LONGJMP32", 200 [(X86eh_sjlj_longjmp addr:$buf)]>, 201 Requires<[Not64BitMode]>; 202 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 203 "#EH_SJLJ_LONGJMP64", 204 [(X86eh_sjlj_longjmp addr:$buf)]>, 205 Requires<[In64BitMode]>; 206 } 207} 208} // SchedRW 209 210let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 211 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 212 "#EH_SjLj_Setup\t$dst", []>; 213} 214 215//===----------------------------------------------------------------------===// 216// Pseudo instructions used by unwind info. 217// 218let isPseudo = 1 in { 219 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 220 "#SEH_PushReg $reg", []>; 221 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 222 "#SEH_SaveReg $reg, $dst", []>; 223 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 224 "#SEH_SaveXMM $reg, $dst", []>; 225 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 226 "#SEH_StackAlloc $size", []>; 227 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 228 "#SEH_SetFrame $reg, $offset", []>; 229 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 230 "#SEH_PushFrame $mode", []>; 231 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 232 "#SEH_EndPrologue", []>; 233 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 234 "#SEH_Epilogue", []>; 235} 236 237//===----------------------------------------------------------------------===// 238// Pseudo instructions used by segmented stacks. 239// 240 241// This is lowered into a RET instruction by MCInstLower. We need 242// this so that we don't have to have a MachineBasicBlock which ends 243// with a RET and also has successors. 244let isPseudo = 1 in { 245def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 246 "", []>; 247 248// This instruction is lowered to a RET followed by a MOV. The two 249// instructions are not generated on a higher level since then the 250// verifier sees a MachineBasicBlock ending with a non-terminator. 251def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 252 "", []>; 253} 254 255//===----------------------------------------------------------------------===// 256// Alias Instructions 257//===----------------------------------------------------------------------===// 258 259// Alias instruction mapping movr0 to xor. 260// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 261let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 262 isPseudo = 1, AddedComplexity = 20 in 263def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 264 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>; 265 266// Other widths can also make use of the 32-bit xor, which may have a smaller 267// encoding and avoid partial register updates. 268def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 269def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 270def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> { 271 let AddedComplexity = 20; 272} 273 274let Predicates = [OptForSize, NotSlowIncDec, Not64BitMode], 275 AddedComplexity = 15 in { 276 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 277 // which only require 3 bytes compared to MOV32ri which requires 5. 278 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 279 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 280 [(set GR32:$dst, 1)]>; 281 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 282 [(set GR32:$dst, -1)]>; 283 } 284 285 // MOV16ri is 4 bytes, so the instructions above are smaller. 286 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 287 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 288} 289 290let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 10 in { 291// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 292// FIXME: Add itinerary class and Schedule. 293def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 294 [(set GR32:$dst, i32immSExt8:$src)]>, 295 Requires<[OptForMinSize, NotWin64WithoutFP]>; 296def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 297 [(set GR64:$dst, i64immSExt8:$src)]>, 298 Requires<[OptForMinSize, NotWin64WithoutFP]>; 299} 300 301// Materialize i64 constant where top 32-bits are zero. This could theoretically 302// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 303// that would make it more difficult to rematerialize. 304let isReMaterializable = 1, isAsCheapAsAMove = 1, 305 isPseudo = 1, hasSideEffects = 0 in 306def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>; 307 308// This 64-bit pseudo-move can be used for both a 64-bit constant that is 309// actually the zero-extension of a 32-bit constant and for labels in the 310// x86-64 small code model. 311def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>; 312 313let AddedComplexity = 1 in 314def : Pat<(i64 mov64imm32:$src), 315 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; 316 317// Use sbb to materialize carry bit. 318let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { 319// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 320// However, Pat<> can't replicate the destination reg into the inputs of the 321// result. 322def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 323 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 324def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 325 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 326def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 327 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 328def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 329 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 330} // isCodeGenOnly 331 332 333def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 334 (SETB_C16r)>; 335def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 336 (SETB_C32r)>; 337def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 338 (SETB_C64r)>; 339 340def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 341 (SETB_C16r)>; 342def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 343 (SETB_C32r)>; 344def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 345 (SETB_C64r)>; 346 347// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 348// will be eliminated and that the sbb can be extended up to a wider type. When 349// this happens, it is great. However, if we are left with an 8-bit sbb and an 350// and, we might as well just match it as a setb. 351def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 352 (SETBr)>; 353 354// (add OP, SETB) -> (adc OP, 0) 355def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 356 (ADC8ri GR8:$op, 0)>; 357def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 358 (ADC32ri8 GR32:$op, 0)>; 359def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 360 (ADC64ri8 GR64:$op, 0)>; 361 362// (sub OP, SETB) -> (sbb OP, 0) 363def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 364 (SBB8ri GR8:$op, 0)>; 365def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 366 (SBB32ri8 GR32:$op, 0)>; 367def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 368 (SBB64ri8 GR64:$op, 0)>; 369 370// (sub OP, SETCC_CARRY) -> (adc OP, 0) 371def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 372 (ADC8ri GR8:$op, 0)>; 373def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 374 (ADC32ri8 GR32:$op, 0)>; 375def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 376 (ADC64ri8 GR64:$op, 0)>; 377 378//===----------------------------------------------------------------------===// 379// String Pseudo Instructions 380// 381let SchedRW = [WriteMicrocoded] in { 382let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 383def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 384 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 385 Requires<[Not64BitMode]>; 386def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 387 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 388 Requires<[Not64BitMode]>; 389def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 390 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 391 Requires<[Not64BitMode]>; 392} 393 394let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 395def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 396 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 397 Requires<[In64BitMode]>; 398def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 399 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 400 Requires<[In64BitMode]>; 401def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 402 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 403 Requires<[In64BitMode]>; 404def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 405 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 406 Requires<[In64BitMode]>; 407} 408 409// FIXME: Should use "(X86rep_stos AL)" as the pattern. 410let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 411 let Uses = [AL,ECX,EDI] in 412 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 413 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 414 Requires<[Not64BitMode]>; 415 let Uses = [AX,ECX,EDI] in 416 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 417 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 418 Requires<[Not64BitMode]>; 419 let Uses = [EAX,ECX,EDI] in 420 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 421 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 422 Requires<[Not64BitMode]>; 423} 424 425let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 426 let Uses = [AL,RCX,RDI] in 427 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 428 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 429 Requires<[In64BitMode]>; 430 let Uses = [AX,RCX,RDI] in 431 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 432 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 433 Requires<[In64BitMode]>; 434 let Uses = [RAX,RCX,RDI] in 435 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 436 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 437 Requires<[In64BitMode]>; 438 439 let Uses = [RAX,RCX,RDI] in 440 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 441 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 442 Requires<[In64BitMode]>; 443} 444} // SchedRW 445 446//===----------------------------------------------------------------------===// 447// Thread Local Storage Instructions 448// 449 450// ELF TLS Support 451// All calls clobber the non-callee saved registers. ESP is marked as 452// a use to prevent stack-pointer assignments that appear immediately 453// before calls from potentially appearing dead. 454let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 455 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 456 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 457 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 458 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 459 usesCustomInserter = 1, Uses = [ESP] in { 460def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 461 "# TLS_addr32", 462 [(X86tlsaddr tls32addr:$sym)]>, 463 Requires<[Not64BitMode]>; 464def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 465 "# TLS_base_addr32", 466 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 467 Requires<[Not64BitMode]>; 468} 469 470// All calls clobber the non-callee saved registers. RSP is marked as 471// a use to prevent stack-pointer assignments that appear immediately 472// before calls from potentially appearing dead. 473let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 474 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 475 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 477 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 478 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 479 usesCustomInserter = 1, Uses = [RSP] in { 480def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 481 "# TLS_addr64", 482 [(X86tlsaddr tls64addr:$sym)]>, 483 Requires<[In64BitMode]>; 484def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 485 "# TLS_base_addr64", 486 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 487 Requires<[In64BitMode]>; 488} 489 490// Darwin TLS Support 491// For i386, the address of the thunk is passed on the stack, on return the 492// address of the variable is in %eax. %ecx is trashed during the function 493// call. All other registers are preserved. 494let Defs = [EAX, ECX, EFLAGS], 495 Uses = [ESP], 496 usesCustomInserter = 1 in 497def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 498 "# TLSCall_32", 499 [(X86TLSCall addr:$sym)]>, 500 Requires<[Not64BitMode]>; 501 502// For x86_64, the address of the thunk is passed in %rdi, but the 503// pseudo directly use the symbol, so do not add an implicit use of 504// %rdi. The lowering will do the right thing with RDI. 505// On return the address of the variable is in %rax. All other 506// registers are preserved. 507let Defs = [RAX, EFLAGS], 508 Uses = [RSP], 509 usesCustomInserter = 1 in 510def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 511 "# TLSCall_64", 512 [(X86TLSCall addr:$sym)]>, 513 Requires<[In64BitMode]>; 514 515 516//===----------------------------------------------------------------------===// 517// Conditional Move Pseudo Instructions 518 519// CMOV* - Used to implement the SELECT DAG operation. Expanded after 520// instruction selection into a branch sequence. 521multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 522 def CMOV#NAME : I<0, Pseudo, 523 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 524 "#CMOV_"#NAME#" PSEUDO!", 525 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond, 526 EFLAGS)))]>; 527} 528 529let usesCustomInserter = 1, Uses = [EFLAGS] in { 530 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 531 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 532 // however that requires promoting the operands, and can induce additional 533 // i8 register pressure. 534 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 535 536 let Predicates = [NoCMov] in { 537 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 538 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 539 } // Predicates = [NoCMov] 540 541 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 542 // SSE1/SSE2. 543 let Predicates = [FPStackf32] in 544 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 545 546 let Predicates = [FPStackf64] in 547 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 548 549 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 550 551 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 552 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 553 defm _FR128 : CMOVrr_PSEUDO<FR128, f128>; 554 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>; 555 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>; 556 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>; 557 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>; 558 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>; 559 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>; 560 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>; 561 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>; 562 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>; 563 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>; 564 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>; 565 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>; 566 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>; 567} // usesCustomInserter = 1, Uses = [EFLAGS] 568 569//===----------------------------------------------------------------------===// 570// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 571//===----------------------------------------------------------------------===// 572 573// FIXME: Use normal instructions and add lock prefix dynamically. 574 575// Memory barriers 576 577// TODO: Get this to fold the constant into the instruction. 578let isCodeGenOnly = 1, Defs = [EFLAGS] in 579def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 580 "or{l}\t{$zero, $dst|$dst, $zero}", [], 581 IIC_ALU_MEM>, Requires<[Not64BitMode]>, OpSize32, LOCK, 582 Sched<[WriteALULd, WriteRMW]>; 583 584let hasSideEffects = 1 in 585def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 586 "#MEMBARRIER", 587 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 588 589// RegOpc corresponds to the mr version of the instruction 590// ImmOpc corresponds to the mi version of the instruction 591// ImmOpc8 corresponds to the mi8 version of the instruction 592// ImmMod corresponds to the instruction format of the mi and mi8 versions 593multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 594 Format ImmMod, SDPatternOperator Op, string mnemonic> { 595let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 596 SchedRW = [WriteALULd, WriteRMW] in { 597 598def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 599 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 600 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 601 !strconcat(mnemonic, "{b}\t", 602 "{$src2, $dst|$dst, $src2}"), 603 [(set EFLAGS, (Op addr:$dst, GR8:$src2))], 604 IIC_ALU_NONMEM>, LOCK; 605 606def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 607 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 608 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 609 !strconcat(mnemonic, "{w}\t", 610 "{$src2, $dst|$dst, $src2}"), 611 [(set EFLAGS, (Op addr:$dst, GR16:$src2))], 612 IIC_ALU_NONMEM>, OpSize16, LOCK; 613 614def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 615 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 616 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 617 !strconcat(mnemonic, "{l}\t", 618 "{$src2, $dst|$dst, $src2}"), 619 [(set EFLAGS, (Op addr:$dst, GR32:$src2))], 620 IIC_ALU_NONMEM>, OpSize32, LOCK; 621 622def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 623 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 624 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 625 !strconcat(mnemonic, "{q}\t", 626 "{$src2, $dst|$dst, $src2}"), 627 [(set EFLAGS, (Op addr:$dst, GR64:$src2))], 628 IIC_ALU_NONMEM>, LOCK; 629 630def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 631 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 632 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 633 !strconcat(mnemonic, "{b}\t", 634 "{$src2, $dst|$dst, $src2}"), 635 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))], 636 IIC_ALU_MEM>, LOCK; 637 638def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 639 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 640 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 641 !strconcat(mnemonic, "{w}\t", 642 "{$src2, $dst|$dst, $src2}"), 643 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))], 644 IIC_ALU_MEM>, OpSize16, LOCK; 645 646def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 647 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 648 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 649 !strconcat(mnemonic, "{l}\t", 650 "{$src2, $dst|$dst, $src2}"), 651 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))], 652 IIC_ALU_MEM>, OpSize32, LOCK; 653 654def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 655 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 656 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 657 !strconcat(mnemonic, "{q}\t", 658 "{$src2, $dst|$dst, $src2}"), 659 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))], 660 IIC_ALU_MEM>, LOCK; 661 662def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 663 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 664 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 665 !strconcat(mnemonic, "{w}\t", 666 "{$src2, $dst|$dst, $src2}"), 667 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))], 668 IIC_ALU_MEM>, OpSize16, LOCK; 669 670def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 671 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 672 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 673 !strconcat(mnemonic, "{l}\t", 674 "{$src2, $dst|$dst, $src2}"), 675 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))], 676 IIC_ALU_MEM>, OpSize32, LOCK; 677 678def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 679 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 680 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 681 !strconcat(mnemonic, "{q}\t", 682 "{$src2, $dst|$dst, $src2}"), 683 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))], 684 IIC_ALU_MEM>, LOCK; 685 686} 687 688} 689 690defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 691defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 692defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 693defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 694defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 695 696multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 697 int Increment, string mnemonic> { 698let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 699 SchedRW = [WriteALULd, WriteRMW], Predicates = [NotSlowIncDec] in { 700def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 701 !strconcat(mnemonic, "{b}\t$dst"), 702 [(set EFLAGS, (X86lock_add addr:$dst, (i8 Increment)))], 703 IIC_UNARY_MEM>, LOCK; 704def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 705 !strconcat(mnemonic, "{w}\t$dst"), 706 [(set EFLAGS, (X86lock_add addr:$dst, (i16 Increment)))], 707 IIC_UNARY_MEM>, OpSize16, LOCK; 708def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 709 !strconcat(mnemonic, "{l}\t$dst"), 710 [(set EFLAGS, (X86lock_add addr:$dst, (i32 Increment)))], 711 IIC_UNARY_MEM>, OpSize32, LOCK; 712def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 713 !strconcat(mnemonic, "{q}\t$dst"), 714 [(set EFLAGS, (X86lock_add addr:$dst, (i64 Increment)))], 715 IIC_UNARY_MEM>, LOCK; 716} 717} 718 719defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, 1, "inc">; 720defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, -1, "dec">; 721 722// Atomic compare and swap. 723multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 724 SDPatternOperator frag, X86MemOperand x86memop, 725 InstrItinClass itin> { 726let isCodeGenOnly = 1, usesCustomInserter = 1 in { 727 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 728 !strconcat(mnemonic, "\t$ptr"), 729 [(frag addr:$ptr)], itin>, TB, LOCK; 730} 731} 732 733multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 734 string mnemonic, SDPatternOperator frag, 735 InstrItinClass itin8, InstrItinClass itin> { 736let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { 737 let Defs = [AL, EFLAGS], Uses = [AL] in 738 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 739 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 740 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 741 let Defs = [AX, EFLAGS], Uses = [AX] in 742 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 743 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 744 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK; 745 let Defs = [EAX, EFLAGS], Uses = [EAX] in 746 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 747 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 748 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK; 749 let Defs = [RAX, EFLAGS], Uses = [RAX] in 750 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 751 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 752 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 753} 754} 755 756let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 757 SchedRW = [WriteALULd, WriteRMW] in { 758defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 759 X86cas8, i64mem, 760 IIC_CMPX_LOCK_8B>; 761} 762 763// This pseudo must be used when the frame uses RBX as 764// the base pointer. Indeed, in such situation RBX is a reserved 765// register and the register allocator will ignore any use/def of 766// it. In other words, the register will not fix the clobbering of 767// RBX that will happen when setting the arguments for the instrucion. 768// 769// Unlike the actual related instuction, we mark that this one 770// defines EBX (instead of using EBX). 771// The rationale is that we will define RBX during the expansion of 772// the pseudo. The argument feeding EBX is ebx_input. 773// 774// The additional argument, $ebx_save, is a temporary register used to 775// save the value of RBX accross the actual instruction. 776// 777// To make sure the register assigned to $ebx_save does not interfere with 778// the definition of the actual instruction, we use a definition $dst which 779// is tied to $rbx_save. That way, the live-range of $rbx_save spans accross 780// the instruction and we are sure we will have a valid register to restore 781// the value of RBX. 782let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX], 783 SchedRW = [WriteALULd, WriteRMW], isCodeGenOnly = 1, isPseudo = 1, 784 Constraints = "$ebx_save = $dst", usesCustomInserter = 1 in { 785def LCMPXCHG8B_SAVE_EBX : 786 I<0, Pseudo, (outs GR32:$dst), 787 (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save), 788 !strconcat("cmpxchg8b", "\t$ptr"), 789 [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input, 790 GR32:$ebx_save))], 791 IIC_CMPX_LOCK_8B>; 792} 793 794 795let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 796 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { 797defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 798 X86cas16, i128mem, 799 IIC_CMPX_LOCK_16B>, REX_W; 800} 801 802// Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant. 803let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 804 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW], 805 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst", 806 usesCustomInserter = 1 in { 807def LCMPXCHG16B_SAVE_RBX : 808 I<0, Pseudo, (outs GR64:$dst), 809 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), 810 !strconcat("cmpxchg16b", "\t$ptr"), 811 [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input, 812 GR64:$rbx_save))], 813 IIC_CMPX_LOCK_16B>; 814} 815 816defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 817 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 818 819// Atomic exchange and add 820multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 821 string frag, 822 InstrItinClass itin8, InstrItinClass itin> { 823 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, 824 SchedRW = [WriteALULd, WriteRMW] in { 825 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 826 (ins GR8:$val, i8mem:$ptr), 827 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 828 [(set GR8:$dst, 829 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 830 itin8>; 831 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 832 (ins GR16:$val, i16mem:$ptr), 833 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 834 [(set 835 GR16:$dst, 836 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 837 itin>, OpSize16; 838 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 839 (ins GR32:$val, i32mem:$ptr), 840 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 841 [(set 842 GR32:$dst, 843 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 844 itin>, OpSize32; 845 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 846 (ins GR64:$val, i64mem:$ptr), 847 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 848 [(set 849 GR64:$dst, 850 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 851 itin>; 852 } 853} 854 855defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 856 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 857 TB, LOCK; 858 859/* The following multiclass tries to make sure that in code like 860 * x.store (immediate op x.load(acquire), release) 861 * and 862 * x.store (register op x.load(acquire), release) 863 * an operation directly on memory is generated instead of wasting a register. 864 * It is not automatic as atomic_store/load are only lowered to MOV instructions 865 * extremely late to prevent them from being accidentally reordered in the backend 866 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 867 */ 868multiclass RELEASE_BINOP_MI<SDNode op> { 869 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 870 "#BINOP "#NAME#"8mi PSEUDO!", 871 [(atomic_store_8 addr:$dst, (op 872 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>; 873 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src), 874 "#BINOP "#NAME#"8mr PSEUDO!", 875 [(atomic_store_8 addr:$dst, (op 876 (atomic_load_8 addr:$dst), GR8:$src))]>; 877 // NAME#16 is not generated as 16-bit arithmetic instructions are considered 878 // costly and avoided as far as possible by this backend anyway 879 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 880 "#BINOP "#NAME#"32mi PSEUDO!", 881 [(atomic_store_32 addr:$dst, (op 882 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>; 883 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 884 "#BINOP "#NAME#"32mr PSEUDO!", 885 [(atomic_store_32 addr:$dst, (op 886 (atomic_load_32 addr:$dst), GR32:$src))]>; 887 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 888 "#BINOP "#NAME#"64mi32 PSEUDO!", 889 [(atomic_store_64 addr:$dst, (op 890 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>; 891 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 892 "#BINOP "#NAME#"64mr PSEUDO!", 893 [(atomic_store_64 addr:$dst, (op 894 (atomic_load_64 addr:$dst), GR64:$src))]>; 895} 896let Defs = [EFLAGS] in { 897 defm RELEASE_ADD : RELEASE_BINOP_MI<add>; 898 defm RELEASE_AND : RELEASE_BINOP_MI<and>; 899 defm RELEASE_OR : RELEASE_BINOP_MI<or>; 900 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>; 901 // Note: we don't deal with sub, because substractions of constants are 902 // optimized into additions before this code can run. 903} 904 905// Same as above, but for floating-point. 906// FIXME: imm version. 907// FIXME: Version that doesn't clobber $src, using AVX's VADDSS. 908// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 909let usesCustomInserter = 1 in { 910multiclass RELEASE_FP_BINOP_MI<SDNode op> { 911 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src), 912 "#BINOP "#NAME#"32mr PSEUDO!", 913 [(atomic_store_32 addr:$dst, 914 (i32 (bitconvert (op 915 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))), 916 FR32:$src))))]>, Requires<[HasSSE1]>; 917 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src), 918 "#BINOP "#NAME#"64mr PSEUDO!", 919 [(atomic_store_64 addr:$dst, 920 (i64 (bitconvert (op 921 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))), 922 FR64:$src))))]>, Requires<[HasSSE2]>; 923} 924defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>; 925// FIXME: Add fsub, fmul, fdiv, ... 926} 927 928multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> { 929 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst), 930 "#UNOP "#NAME#"8m PSEUDO!", 931 [(atomic_store_8 addr:$dst, dag8)]>; 932 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst), 933 "#UNOP "#NAME#"16m PSEUDO!", 934 [(atomic_store_16 addr:$dst, dag16)]>; 935 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst), 936 "#UNOP "#NAME#"32m PSEUDO!", 937 [(atomic_store_32 addr:$dst, dag32)]>; 938 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst), 939 "#UNOP "#NAME#"64m PSEUDO!", 940 [(atomic_store_64 addr:$dst, dag64)]>; 941} 942 943let Defs = [EFLAGS] in { 944 defm RELEASE_INC : RELEASE_UNOP< 945 (add (atomic_load_8 addr:$dst), (i8 1)), 946 (add (atomic_load_16 addr:$dst), (i16 1)), 947 (add (atomic_load_32 addr:$dst), (i32 1)), 948 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>; 949 defm RELEASE_DEC : RELEASE_UNOP< 950 (add (atomic_load_8 addr:$dst), (i8 -1)), 951 (add (atomic_load_16 addr:$dst), (i16 -1)), 952 (add (atomic_load_32 addr:$dst), (i32 -1)), 953 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>; 954} 955/* 956TODO: These don't work because the type inference of TableGen fails. 957TODO: find a way to fix it. 958let Defs = [EFLAGS] in { 959 defm RELEASE_NEG : RELEASE_UNOP< 960 (ineg (atomic_load_8 addr:$dst)), 961 (ineg (atomic_load_16 addr:$dst)), 962 (ineg (atomic_load_32 addr:$dst)), 963 (ineg (atomic_load_64 addr:$dst))>; 964} 965// NOT doesn't set flags. 966defm RELEASE_NOT : RELEASE_UNOP< 967 (not (atomic_load_8 addr:$dst)), 968 (not (atomic_load_16 addr:$dst)), 969 (not (atomic_load_32 addr:$dst)), 970 (not (atomic_load_64 addr:$dst))>; 971*/ 972 973def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 974 "#RELEASE_MOV8mi PSEUDO!", 975 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>; 976def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src), 977 "#RELEASE_MOV16mi PSEUDO!", 978 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>; 979def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 980 "#RELEASE_MOV32mi PSEUDO!", 981 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>; 982def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 983 "#RELEASE_MOV64mi32 PSEUDO!", 984 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>; 985 986def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 987 "#RELEASE_MOV8mr PSEUDO!", 988 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 989def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 990 "#RELEASE_MOV16mr PSEUDO!", 991 [(atomic_store_16 addr:$dst, GR16:$src)]>; 992def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 993 "#RELEASE_MOV32mr PSEUDO!", 994 [(atomic_store_32 addr:$dst, GR32:$src)]>; 995def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 996 "#RELEASE_MOV64mr PSEUDO!", 997 [(atomic_store_64 addr:$dst, GR64:$src)]>; 998 999def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 1000 "#ACQUIRE_MOV8rm PSEUDO!", 1001 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 1002def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 1003 "#ACQUIRE_MOV16rm PSEUDO!", 1004 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 1005def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 1006 "#ACQUIRE_MOV32rm PSEUDO!", 1007 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 1008def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 1009 "#ACQUIRE_MOV64rm PSEUDO!", 1010 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 1011 1012//===----------------------------------------------------------------------===// 1013// DAG Pattern Matching Rules 1014//===----------------------------------------------------------------------===// 1015 1016// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1017// binary size compared to a regular MOV, but it introduces an unnecessary 1018// load, so is not suitable for regular or optsize functions. 1019let Predicates = [OptForMinSize] in { 1020def : Pat<(store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>; 1021def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>; 1022def : Pat<(store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>; 1023def : Pat<(store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>; 1024def : Pat<(store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>; 1025def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>; 1026} 1027 1028// In kernel code model, we can get the address of a label 1029// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1030// the MOV64ri32 should accept these. 1031def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1032 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1033def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1034 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1035def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1036 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1037def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1038 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1039def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1040 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1041def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1042 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1043 1044// If we have small model and -static mode, it is safe to store global addresses 1045// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1046// for MOV64mi32 should handle this sort of thing. 1047def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1048 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1049 Requires<[NearData, IsNotPIC]>; 1050def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1051 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1052 Requires<[NearData, IsNotPIC]>; 1053def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1054 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1055 Requires<[NearData, IsNotPIC]>; 1056def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1057 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1058 Requires<[NearData, IsNotPIC]>; 1059def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1060 (MOV64mi32 addr:$dst, mcsym:$src)>, 1061 Requires<[NearData, IsNotPIC]>; 1062def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1063 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1064 Requires<[NearData, IsNotPIC]>; 1065 1066def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1067def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1068 1069// Calls 1070 1071// tls has some funny stuff here... 1072// This corresponds to movabs $foo@tpoff, %rax 1073def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1074 (MOV64ri32 tglobaltlsaddr :$dst)>; 1075// This corresponds to add $foo@tpoff, %rax 1076def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1077 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1078 1079 1080// Direct PC relative function call for small code model. 32-bit displacement 1081// sign extended to 64-bit. 1082def : Pat<(X86call (i64 tglobaladdr:$dst)), 1083 (CALL64pcrel32 tglobaladdr:$dst)>; 1084def : Pat<(X86call (i64 texternalsym:$dst)), 1085 (CALL64pcrel32 texternalsym:$dst)>; 1086 1087// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1088// can never use callee-saved registers. That is the purpose of the GR64_TC 1089// register classes. 1090// 1091// The only volatile register that is never used by the calling convention is 1092// %r11. This happens when calling a vararg function with 6 arguments. 1093// 1094// Match an X86tcret that uses less than 7 volatile registers. 1095def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1096 (X86tcret node:$ptr, node:$off), [{ 1097 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1098 unsigned NumRegs = 0; 1099 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1100 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1101 return false; 1102 return true; 1103}]>; 1104 1105def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1106 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1107 Requires<[Not64BitMode]>; 1108 1109// FIXME: This is disabled for 32-bit PIC mode because the global base 1110// register which is part of the address mode may be assigned a 1111// callee-saved register. 1112def : Pat<(X86tcret (load addr:$dst), imm:$off), 1113 (TCRETURNmi addr:$dst, imm:$off)>, 1114 Requires<[Not64BitMode, IsNotPIC]>; 1115 1116def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1117 (TCRETURNdi tglobaladdr:$dst, imm:$off)>, 1118 Requires<[NotLP64]>; 1119 1120def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1121 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1122 Requires<[NotLP64]>; 1123 1124def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1125 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1126 Requires<[In64BitMode]>; 1127 1128// Don't fold loads into X86tcret requiring more than 6 regs. 1129// There wouldn't be enough scratch registers for base+index. 1130def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1131 (TCRETURNmi64 addr:$dst, imm:$off)>, 1132 Requires<[In64BitMode]>; 1133 1134def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1135 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1136 Requires<[IsLP64]>; 1137 1138def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1139 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1140 Requires<[IsLP64]>; 1141 1142// Normal calls, with various flavors of addresses. 1143def : Pat<(X86call (i32 tglobaladdr:$dst)), 1144 (CALLpcrel32 tglobaladdr:$dst)>; 1145def : Pat<(X86call (i32 texternalsym:$dst)), 1146 (CALLpcrel32 texternalsym:$dst)>; 1147def : Pat<(X86call (i32 imm:$dst)), 1148 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1149 1150// Comparisons. 1151 1152// TEST R,R is smaller than CMP R,0 1153def : Pat<(X86cmp GR8:$src1, 0), 1154 (TEST8rr GR8:$src1, GR8:$src1)>; 1155def : Pat<(X86cmp GR16:$src1, 0), 1156 (TEST16rr GR16:$src1, GR16:$src1)>; 1157def : Pat<(X86cmp GR32:$src1, 0), 1158 (TEST32rr GR32:$src1, GR32:$src1)>; 1159def : Pat<(X86cmp GR64:$src1, 0), 1160 (TEST64rr GR64:$src1, GR64:$src1)>; 1161 1162// Conditional moves with folded loads with operands swapped and conditions 1163// inverted. 1164multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1165 Instruction Inst64> { 1166 let Predicates = [HasCMov] in { 1167 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1168 (Inst16 GR16:$src2, addr:$src1)>; 1169 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1170 (Inst32 GR32:$src2, addr:$src1)>; 1171 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1172 (Inst64 GR64:$src2, addr:$src1)>; 1173 } 1174} 1175 1176defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1177defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1178defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1179defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1180defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1181defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1182defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1183defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1184defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1185defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1186defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1187defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1188defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1189defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1190defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1191defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1192 1193// zextload bool -> zextload byte 1194// i1 stored in one byte in zero-extended form. 1195// Upper bits cleanup should be executed before Store. 1196def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1197def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1198def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1199def : Pat<(zextloadi64i1 addr:$src), 1200 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1201 1202// extload bool -> extload byte 1203// When extloading from 16-bit and smaller memory locations into 64-bit 1204// registers, use zero-extending loads so that the entire 64-bit register is 1205// defined, avoiding partial-register updates. 1206 1207def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1208def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1209def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1210def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1211def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1212def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1213 1214// For other extloads, use subregs, since the high contents of the register are 1215// defined after an extload. 1216def : Pat<(extloadi64i1 addr:$src), 1217 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1218def : Pat<(extloadi64i8 addr:$src), 1219 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1220def : Pat<(extloadi64i16 addr:$src), 1221 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1222def : Pat<(extloadi64i32 addr:$src), 1223 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1224 1225// anyext. Define these to do an explicit zero-extend to 1226// avoid partial-register updates. 1227def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1228 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1229def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1230 1231// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1232def : Pat<(i32 (anyext GR16:$src)), 1233 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1234 1235def : Pat<(i64 (anyext GR8 :$src)), 1236 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1237def : Pat<(i64 (anyext GR16:$src)), 1238 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1239def : Pat<(i64 (anyext GR32:$src)), 1240 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1241 1242 1243// Any instruction that defines a 32-bit result leaves the high half of the 1244// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1245// be copying from a truncate. Any other 32-bit operation will zero-extend 1246// up to 64 bits. 1247def def32 : PatLeaf<(i32 GR32:$src), [{ 1248 return N->getOpcode() != ISD::TRUNCATE && 1249 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1250 N->getOpcode() != ISD::CopyFromReg && 1251 N->getOpcode() != ISD::AssertSext; 1252}]>; 1253 1254// In the case of a 32-bit def that is known to implicitly zero-extend, 1255// we can use a SUBREG_TO_REG. 1256def : Pat<(i64 (zext def32:$src)), 1257 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1258 1259//===----------------------------------------------------------------------===// 1260// Pattern match OR as ADD 1261//===----------------------------------------------------------------------===// 1262 1263// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1264// 3-addressified into an LEA instruction to avoid copies. However, we also 1265// want to finally emit these instructions as an or at the end of the code 1266// generator to make the generated code easier to read. To do this, we select 1267// into "disjoint bits" pseudo ops. 1268 1269// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1270def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1271 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1272 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1273 1274 APInt KnownZero0, KnownOne0; 1275 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1276 APInt KnownZero1, KnownOne1; 1277 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1278 return (~KnownZero0 & ~KnownZero1) == 0; 1279}]>; 1280 1281 1282// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1283// Try this before the selecting to OR. 1284let AddedComplexity = 5, SchedRW = [WriteALU] in { 1285 1286let isConvertibleToThreeAddress = 1, 1287 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1288let isCommutable = 1 in { 1289def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1290 "", // orw/addw REG, REG 1291 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1292def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1293 "", // orl/addl REG, REG 1294 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1295def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1296 "", // orq/addq REG, REG 1297 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1298} // isCommutable 1299 1300// NOTE: These are order specific, we want the ri8 forms to be listed 1301// first so that they are slightly preferred to the ri forms. 1302 1303def ADD16ri8_DB : I<0, Pseudo, 1304 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1305 "", // orw/addw REG, imm8 1306 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1307def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1308 "", // orw/addw REG, imm 1309 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1310 1311def ADD32ri8_DB : I<0, Pseudo, 1312 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1313 "", // orl/addl REG, imm8 1314 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1315def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1316 "", // orl/addl REG, imm 1317 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1318 1319 1320def ADD64ri8_DB : I<0, Pseudo, 1321 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1322 "", // orq/addq REG, imm8 1323 [(set GR64:$dst, (or_is_add GR64:$src1, 1324 i64immSExt8:$src2))]>; 1325def ADD64ri32_DB : I<0, Pseudo, 1326 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1327 "", // orq/addq REG, imm 1328 [(set GR64:$dst, (or_is_add GR64:$src1, 1329 i64immSExt32:$src2))]>; 1330} 1331} // AddedComplexity, SchedRW 1332 1333 1334//===----------------------------------------------------------------------===// 1335// Some peepholes 1336//===----------------------------------------------------------------------===// 1337 1338// Odd encoding trick: -128 fits into an 8-bit immediate field while 1339// +128 doesn't, so in this special case use a sub instead of an add. 1340def : Pat<(add GR16:$src1, 128), 1341 (SUB16ri8 GR16:$src1, -128)>; 1342def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1343 (SUB16mi8 addr:$dst, -128)>; 1344 1345def : Pat<(add GR32:$src1, 128), 1346 (SUB32ri8 GR32:$src1, -128)>; 1347def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1348 (SUB32mi8 addr:$dst, -128)>; 1349 1350def : Pat<(add GR64:$src1, 128), 1351 (SUB64ri8 GR64:$src1, -128)>; 1352def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1353 (SUB64mi8 addr:$dst, -128)>; 1354 1355// The same trick applies for 32-bit immediate fields in 64-bit 1356// instructions. 1357def : Pat<(add GR64:$src1, 0x0000000080000000), 1358 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1359def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), 1360 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1361 1362// To avoid needing to materialize an immediate in a register, use a 32-bit and 1363// with implicit zero-extension instead of a 64-bit and if the immediate has at 1364// least 32 bits of leading zeros. If in addition the last 32 bits can be 1365// represented with a sign extension of a 8 bit constant, use that. 1366// This can also reduce instruction size by eliminating the need for the REX 1367// prefix. 1368 1369// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1370let AddedComplexity = 1 in { 1371def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1372 (SUBREG_TO_REG 1373 (i64 0), 1374 (AND32ri8 1375 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1376 (i32 (GetLo8XForm imm:$imm))), 1377 sub_32bit)>; 1378 1379def : Pat<(and GR64:$src, i64immZExt32:$imm), 1380 (SUBREG_TO_REG 1381 (i64 0), 1382 (AND32ri 1383 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1384 (i32 (GetLo32XForm imm:$imm))), 1385 sub_32bit)>; 1386} // AddedComplexity = 1 1387 1388 1389// AddedComplexity is needed due to the increased complexity on the 1390// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1391// the MOVZX patterns keeps thems together in DAGIsel tables. 1392let AddedComplexity = 1 in { 1393// r & (2^16-1) ==> movz 1394def : Pat<(and GR32:$src1, 0xffff), 1395 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1396// r & (2^8-1) ==> movz 1397def : Pat<(and GR32:$src1, 0xff), 1398 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1399 GR32_ABCD)), 1400 sub_8bit))>, 1401 Requires<[Not64BitMode]>; 1402// r & (2^8-1) ==> movz 1403def : Pat<(and GR16:$src1, 0xff), 1404 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1405 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1406 sub_16bit)>, 1407 Requires<[Not64BitMode]>; 1408 1409// r & (2^32-1) ==> movz 1410def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1411 (SUBREG_TO_REG (i64 0), 1412 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1413 sub_32bit)>; 1414// r & (2^16-1) ==> movz 1415def : Pat<(and GR64:$src, 0xffff), 1416 (SUBREG_TO_REG (i64 0), 1417 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1418 sub_32bit)>; 1419// r & (2^8-1) ==> movz 1420def : Pat<(and GR64:$src, 0xff), 1421 (SUBREG_TO_REG (i64 0), 1422 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1423 sub_32bit)>; 1424// r & (2^8-1) ==> movz 1425def : Pat<(and GR32:$src1, 0xff), 1426 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1427 Requires<[In64BitMode]>; 1428// r & (2^8-1) ==> movz 1429def : Pat<(and GR16:$src1, 0xff), 1430 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1431 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1432 Requires<[In64BitMode]>; 1433} // AddedComplexity = 1 1434 1435 1436// sext_inreg patterns 1437def : Pat<(sext_inreg GR32:$src, i16), 1438 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1439def : Pat<(sext_inreg GR32:$src, i8), 1440 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1441 GR32_ABCD)), 1442 sub_8bit))>, 1443 Requires<[Not64BitMode]>; 1444 1445def : Pat<(sext_inreg GR16:$src, i8), 1446 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1447 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1448 sub_16bit)>, 1449 Requires<[Not64BitMode]>; 1450 1451def : Pat<(sext_inreg GR64:$src, i32), 1452 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1453def : Pat<(sext_inreg GR64:$src, i16), 1454 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1455def : Pat<(sext_inreg GR64:$src, i8), 1456 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1457def : Pat<(sext_inreg GR32:$src, i8), 1458 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1459 Requires<[In64BitMode]>; 1460def : Pat<(sext_inreg GR16:$src, i8), 1461 (EXTRACT_SUBREG (MOVSX32rr8 1462 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1463 Requires<[In64BitMode]>; 1464 1465// sext, sext_load, zext, zext_load 1466def: Pat<(i16 (sext GR8:$src)), 1467 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1468def: Pat<(sextloadi16i8 addr:$src), 1469 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1470def: Pat<(i16 (zext GR8:$src)), 1471 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1472def: Pat<(zextloadi16i8 addr:$src), 1473 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1474 1475// trunc patterns 1476def : Pat<(i16 (trunc GR32:$src)), 1477 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1478def : Pat<(i8 (trunc GR32:$src)), 1479 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1480 sub_8bit)>, 1481 Requires<[Not64BitMode]>; 1482def : Pat<(i8 (trunc GR16:$src)), 1483 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1484 sub_8bit)>, 1485 Requires<[Not64BitMode]>; 1486def : Pat<(i32 (trunc GR64:$src)), 1487 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1488def : Pat<(i16 (trunc GR64:$src)), 1489 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1490def : Pat<(i8 (trunc GR64:$src)), 1491 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1492def : Pat<(i8 (trunc GR32:$src)), 1493 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1494 Requires<[In64BitMode]>; 1495def : Pat<(i8 (trunc GR16:$src)), 1496 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1497 Requires<[In64BitMode]>; 1498 1499// h-register tricks 1500def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1501 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1502 sub_8bit_hi)>, 1503 Requires<[Not64BitMode]>; 1504def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), 1505 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1506 sub_8bit_hi)>, 1507 Requires<[Not64BitMode]>; 1508def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1509 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1510 sub_8bit_hi)>, 1511 Requires<[Not64BitMode]>; 1512def : Pat<(srl GR16:$src, (i8 8)), 1513 (EXTRACT_SUBREG 1514 (MOVZX32rr8 1515 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1516 sub_8bit_hi)), 1517 sub_16bit)>, 1518 Requires<[Not64BitMode]>; 1519def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1520 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1521 GR16_ABCD)), 1522 sub_8bit_hi))>, 1523 Requires<[Not64BitMode]>; 1524def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1525 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1526 GR16_ABCD)), 1527 sub_8bit_hi))>, 1528 Requires<[Not64BitMode]>; 1529def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1530 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1531 GR32_ABCD)), 1532 sub_8bit_hi))>, 1533 Requires<[Not64BitMode]>; 1534def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1535 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1536 GR32_ABCD)), 1537 sub_8bit_hi))>, 1538 Requires<[Not64BitMode]>; 1539 1540// h-register tricks. 1541// For now, be conservative on x86-64 and use an h-register extract only if the 1542// value is immediately zero-extended or stored, which are somewhat common 1543// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1544// from being allocated in the same instruction as the h register, as there's 1545// currently no way to describe this requirement to the register allocator. 1546 1547// h-register extract and zero-extend. 1548def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1549 (SUBREG_TO_REG 1550 (i64 0), 1551 (MOVZX32_NOREXrr8 1552 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1553 sub_8bit_hi)), 1554 sub_32bit)>; 1555def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1556 (MOVZX32_NOREXrr8 1557 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1558 sub_8bit_hi))>, 1559 Requires<[In64BitMode]>; 1560def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1561 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1562 GR32_ABCD)), 1563 sub_8bit_hi))>, 1564 Requires<[In64BitMode]>; 1565def : Pat<(srl GR16:$src, (i8 8)), 1566 (EXTRACT_SUBREG 1567 (MOVZX32_NOREXrr8 1568 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1569 sub_8bit_hi)), 1570 sub_16bit)>, 1571 Requires<[In64BitMode]>; 1572def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1573 (MOVZX32_NOREXrr8 1574 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1575 sub_8bit_hi))>, 1576 Requires<[In64BitMode]>; 1577def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1578 (MOVZX32_NOREXrr8 1579 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1580 sub_8bit_hi))>, 1581 Requires<[In64BitMode]>; 1582def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1583 (SUBREG_TO_REG 1584 (i64 0), 1585 (MOVZX32_NOREXrr8 1586 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1587 sub_8bit_hi)), 1588 sub_32bit)>; 1589def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1590 (SUBREG_TO_REG 1591 (i64 0), 1592 (MOVZX32_NOREXrr8 1593 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1594 sub_8bit_hi)), 1595 sub_32bit)>; 1596 1597// h-register extract and store. 1598def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1599 (MOV8mr_NOREX 1600 addr:$dst, 1601 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1602 sub_8bit_hi))>; 1603def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1604 (MOV8mr_NOREX 1605 addr:$dst, 1606 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1607 sub_8bit_hi))>, 1608 Requires<[In64BitMode]>; 1609def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1610 (MOV8mr_NOREX 1611 addr:$dst, 1612 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1613 sub_8bit_hi))>, 1614 Requires<[In64BitMode]>; 1615 1616 1617// (shl x, 1) ==> (add x, x) 1618// Note that if x is undef (immediate or otherwise), we could theoretically 1619// end up with the two uses of x getting different values, producing a result 1620// where the least significant bit is not 0. However, the probability of this 1621// happening is considered low enough that this is officially not a 1622// "real problem". 1623def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1624def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1625def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1626def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1627 1628// Helper imms that check if a mask doesn't change significant shift bits. 1629def immShift32 : ImmLeaf<i8, [{ 1630 return countTrailingOnes<uint64_t>(Imm) >= 5; 1631}]>; 1632def immShift64 : ImmLeaf<i8, [{ 1633 return countTrailingOnes<uint64_t>(Imm) >= 6; 1634}]>; 1635 1636// Shift amount is implicitly masked. 1637multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1638 // (shift x (and y, 31)) ==> (shift x, y) 1639 def : Pat<(frag GR8:$src1, (and CL, immShift32)), 1640 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1641 def : Pat<(frag GR16:$src1, (and CL, immShift32)), 1642 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1643 def : Pat<(frag GR32:$src1, (and CL, immShift32)), 1644 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1645 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1646 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1647 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1648 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1649 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1650 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1651 1652 // (shift x (and y, 63)) ==> (shift x, y) 1653 def : Pat<(frag GR64:$src1, (and CL, immShift64)), 1654 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1655 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1656 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1657} 1658 1659defm : MaskedShiftAmountPats<shl, "SHL">; 1660defm : MaskedShiftAmountPats<srl, "SHR">; 1661defm : MaskedShiftAmountPats<sra, "SAR">; 1662defm : MaskedShiftAmountPats<rotl, "ROL">; 1663defm : MaskedShiftAmountPats<rotr, "ROR">; 1664 1665// Double shift amount is implicitly masked. 1666multiclass MaskedDoubleShiftAmountPats<SDNode frag, string name> { 1667 // (shift x (and y, 31)) ==> (shift x, y) 1668 def : Pat<(frag GR16:$src1, GR16:$src2, (and CL, immShift32)), 1669 (!cast<Instruction>(name # "16rrCL") GR16:$src1, GR16:$src2)>; 1670 def : Pat<(frag GR32:$src1, GR32:$src2, (and CL, immShift32)), 1671 (!cast<Instruction>(name # "32rrCL") GR32:$src1, GR32:$src2)>; 1672 1673 // (shift x (and y, 63)) ==> (shift x, y) 1674 def : Pat<(frag GR64:$src1, GR64:$src2, (and CL, immShift64)), 1675 (!cast<Instruction>(name # "64rrCL") GR64:$src1, GR64:$src2)>; 1676} 1677 1678defm : MaskedDoubleShiftAmountPats<X86shld, "SHLD">; 1679defm : MaskedDoubleShiftAmountPats<X86shrd, "SHRD">; 1680 1681// (anyext (setcc_carry)) -> (setcc_carry) 1682def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1683 (SETB_C16r)>; 1684def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1685 (SETB_C32r)>; 1686def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1687 (SETB_C32r)>; 1688 1689//===----------------------------------------------------------------------===// 1690// EFLAGS-defining Patterns 1691//===----------------------------------------------------------------------===// 1692 1693// add reg, reg 1694def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1695def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1696def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1697 1698// add reg, mem 1699def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1700 (ADD8rm GR8:$src1, addr:$src2)>; 1701def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1702 (ADD16rm GR16:$src1, addr:$src2)>; 1703def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1704 (ADD32rm GR32:$src1, addr:$src2)>; 1705 1706// add reg, imm 1707def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1708def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1709def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1710def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1711 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1712def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1713 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1714 1715// sub reg, reg 1716def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1717def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1718def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1719 1720// sub reg, mem 1721def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1722 (SUB8rm GR8:$src1, addr:$src2)>; 1723def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1724 (SUB16rm GR16:$src1, addr:$src2)>; 1725def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1726 (SUB32rm GR32:$src1, addr:$src2)>; 1727 1728// sub reg, imm 1729def : Pat<(sub GR8:$src1, imm:$src2), 1730 (SUB8ri GR8:$src1, imm:$src2)>; 1731def : Pat<(sub GR16:$src1, imm:$src2), 1732 (SUB16ri GR16:$src1, imm:$src2)>; 1733def : Pat<(sub GR32:$src1, imm:$src2), 1734 (SUB32ri GR32:$src1, imm:$src2)>; 1735def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1736 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1737def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1738 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1739 1740// sub 0, reg 1741def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1742def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1743def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1744def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1745 1746// mul reg, reg 1747def : Pat<(mul GR16:$src1, GR16:$src2), 1748 (IMUL16rr GR16:$src1, GR16:$src2)>; 1749def : Pat<(mul GR32:$src1, GR32:$src2), 1750 (IMUL32rr GR32:$src1, GR32:$src2)>; 1751 1752// mul reg, mem 1753def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1754 (IMUL16rm GR16:$src1, addr:$src2)>; 1755def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1756 (IMUL32rm GR32:$src1, addr:$src2)>; 1757 1758// mul reg, imm 1759def : Pat<(mul GR16:$src1, imm:$src2), 1760 (IMUL16rri GR16:$src1, imm:$src2)>; 1761def : Pat<(mul GR32:$src1, imm:$src2), 1762 (IMUL32rri GR32:$src1, imm:$src2)>; 1763def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1764 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1765def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1766 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1767 1768// reg = mul mem, imm 1769def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1770 (IMUL16rmi addr:$src1, imm:$src2)>; 1771def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1772 (IMUL32rmi addr:$src1, imm:$src2)>; 1773def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1774 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1775def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1776 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1777 1778// Patterns for nodes that do not produce flags, for instructions that do. 1779 1780// addition 1781def : Pat<(add GR64:$src1, GR64:$src2), 1782 (ADD64rr GR64:$src1, GR64:$src2)>; 1783def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1784 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1785def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1786 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1787def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1788 (ADD64rm GR64:$src1, addr:$src2)>; 1789 1790// subtraction 1791def : Pat<(sub GR64:$src1, GR64:$src2), 1792 (SUB64rr GR64:$src1, GR64:$src2)>; 1793def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1794 (SUB64rm GR64:$src1, addr:$src2)>; 1795def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1796 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1797def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1798 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1799 1800// Multiply 1801def : Pat<(mul GR64:$src1, GR64:$src2), 1802 (IMUL64rr GR64:$src1, GR64:$src2)>; 1803def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1804 (IMUL64rm GR64:$src1, addr:$src2)>; 1805def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1806 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1807def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1808 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1809def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1810 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1811def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1812 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1813 1814// Increment/Decrement reg. 1815// Do not make INC/DEC if it is slow 1816let Predicates = [NotSlowIncDec] in { 1817 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 1818 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 1819 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 1820 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1821 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 1822 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 1823 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 1824 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1825} 1826 1827// or reg/reg. 1828def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1829def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1830def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1831def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1832 1833// or reg/mem 1834def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1835 (OR8rm GR8:$src1, addr:$src2)>; 1836def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1837 (OR16rm GR16:$src1, addr:$src2)>; 1838def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1839 (OR32rm GR32:$src1, addr:$src2)>; 1840def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1841 (OR64rm GR64:$src1, addr:$src2)>; 1842 1843// or reg/imm 1844def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1845def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1846def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1847def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1848 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1849def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1850 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1851def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1852 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1853def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1854 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1855 1856// xor reg/reg 1857def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1858def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1859def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1860def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1861 1862// xor reg/mem 1863def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1864 (XOR8rm GR8:$src1, addr:$src2)>; 1865def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1866 (XOR16rm GR16:$src1, addr:$src2)>; 1867def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1868 (XOR32rm GR32:$src1, addr:$src2)>; 1869def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1870 (XOR64rm GR64:$src1, addr:$src2)>; 1871 1872// xor reg/imm 1873def : Pat<(xor GR8:$src1, imm:$src2), 1874 (XOR8ri GR8:$src1, imm:$src2)>; 1875def : Pat<(xor GR16:$src1, imm:$src2), 1876 (XOR16ri GR16:$src1, imm:$src2)>; 1877def : Pat<(xor GR32:$src1, imm:$src2), 1878 (XOR32ri GR32:$src1, imm:$src2)>; 1879def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1880 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1881def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1882 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1883def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1884 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1885def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1886 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1887 1888// and reg/reg 1889def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1890def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1891def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1892def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1893 1894// and reg/mem 1895def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1896 (AND8rm GR8:$src1, addr:$src2)>; 1897def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1898 (AND16rm GR16:$src1, addr:$src2)>; 1899def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1900 (AND32rm GR32:$src1, addr:$src2)>; 1901def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1902 (AND64rm GR64:$src1, addr:$src2)>; 1903 1904// and reg/imm 1905def : Pat<(and GR8:$src1, imm:$src2), 1906 (AND8ri GR8:$src1, imm:$src2)>; 1907def : Pat<(and GR16:$src1, imm:$src2), 1908 (AND16ri GR16:$src1, imm:$src2)>; 1909def : Pat<(and GR32:$src1, imm:$src2), 1910 (AND32ri GR32:$src1, imm:$src2)>; 1911def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1912 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1913def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1914 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1915def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1916 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1917def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1918 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1919 1920// Bit scan instruction patterns to match explicit zero-undef behavior. 1921def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1922def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1923def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1924def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1925def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1926def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1927 1928// When HasMOVBE is enabled it is possible to get a non-legalized 1929// register-register 16 bit bswap. This maps it to a ROL instruction. 1930let Predicates = [HasMOVBE] in { 1931 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 1932} 1933