1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the pass which converts floating point instructions from 10 // pseudo registers into register stack instructions. This pass uses live 11 // variable information to indicate where the FPn registers are used and their 12 // lifetimes. 13 // 14 // The x87 hardware tracks liveness of the stack registers, so it is necessary 15 // to implement exact liveness tracking between basic blocks. The CFG edges are 16 // partitioned into bundles where the same FP registers must be live in 17 // identical stack positions. Instructions are inserted at the end of each basic 18 // block to rearrange the live registers to match the outgoing bundle. 19 // 20 // This approach avoids splitting critical edges at the potential cost of more 21 // live register shuffling instructions when critical edges are present. 22 // 23 //===----------------------------------------------------------------------===// 24 25 #include "X86.h" 26 #include "X86InstrInfo.h" 27 #include "llvm/ADT/DepthFirstIterator.h" 28 #include "llvm/ADT/STLExtras.h" 29 #include "llvm/ADT/SmallPtrSet.h" 30 #include "llvm/ADT/SmallSet.h" 31 #include "llvm/ADT/SmallVector.h" 32 #include "llvm/ADT/Statistic.h" 33 #include "llvm/CodeGen/EdgeBundles.h" 34 #include "llvm/CodeGen/LivePhysRegs.h" 35 #include "llvm/CodeGen/MachineFunctionPass.h" 36 #include "llvm/CodeGen/MachineInstrBuilder.h" 37 #include "llvm/CodeGen/MachineRegisterInfo.h" 38 #include "llvm/CodeGen/Passes.h" 39 #include "llvm/CodeGen/TargetInstrInfo.h" 40 #include "llvm/CodeGen/TargetSubtargetInfo.h" 41 #include "llvm/Config/llvm-config.h" 42 #include "llvm/IR/InlineAsm.h" 43 #include "llvm/InitializePasses.h" 44 #include "llvm/Support/Debug.h" 45 #include "llvm/Support/ErrorHandling.h" 46 #include "llvm/Support/raw_ostream.h" 47 #include "llvm/Target/TargetMachine.h" 48 #include <algorithm> 49 #include <bitset> 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86-codegen" 53 54 STATISTIC(NumFXCH, "Number of fxch instructions inserted"); 55 STATISTIC(NumFP , "Number of floating point instructions"); 56 57 namespace { 58 const unsigned ScratchFPReg = 7; 59 60 struct FPS : public MachineFunctionPass { 61 static char ID; 62 FPS() : MachineFunctionPass(ID) { 63 // This is really only to keep valgrind quiet. 64 // The logic in isLive() is too much for it. 65 memset(Stack, 0, sizeof(Stack)); 66 memset(RegMap, 0, sizeof(RegMap)); 67 } 68 69 void getAnalysisUsage(AnalysisUsage &AU) const override { 70 AU.setPreservesCFG(); 71 AU.addRequired<EdgeBundles>(); 72 AU.addPreservedID(MachineLoopInfoID); 73 AU.addPreservedID(MachineDominatorsID); 74 MachineFunctionPass::getAnalysisUsage(AU); 75 } 76 77 bool runOnMachineFunction(MachineFunction &MF) override; 78 79 MachineFunctionProperties getRequiredProperties() const override { 80 return MachineFunctionProperties().set( 81 MachineFunctionProperties::Property::NoVRegs); 82 } 83 84 StringRef getPassName() const override { return "X86 FP Stackifier"; } 85 86 private: 87 const TargetInstrInfo *TII = nullptr; // Machine instruction info. 88 89 // Two CFG edges are related if they leave the same block, or enter the same 90 // block. The transitive closure of an edge under this relation is a 91 // LiveBundle. It represents a set of CFG edges where the live FP stack 92 // registers must be allocated identically in the x87 stack. 93 // 94 // A LiveBundle is usually all the edges leaving a block, or all the edges 95 // entering a block, but it can contain more edges if critical edges are 96 // present. 97 // 98 // The set of live FP registers in a LiveBundle is calculated by bundleCFG, 99 // but the exact mapping of FP registers to stack slots is fixed later. 100 struct LiveBundle { 101 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c. 102 unsigned Mask; 103 104 // Number of pre-assigned live registers in FixStack. This is 0 when the 105 // stack order has not yet been fixed. 106 unsigned FixCount; 107 108 // Assigned stack order for live-in registers. 109 // FixStack[i] == getStackEntry(i) for all i < FixCount. 110 unsigned char FixStack[8]; 111 112 LiveBundle() : Mask(0), FixCount(0) {} 113 114 // Have the live registers been assigned a stack order yet? 115 bool isFixed() const { return !Mask || FixCount; } 116 }; 117 118 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges 119 // with no live FP registers. 120 SmallVector<LiveBundle, 8> LiveBundles; 121 122 // The edge bundle analysis provides indices into the LiveBundles vector. 123 EdgeBundles *Bundles = nullptr; 124 125 // Return a bitmask of FP registers in block's live-in list. 126 static unsigned calcLiveInMask(MachineBasicBlock *MBB, bool RemoveFPs) { 127 unsigned Mask = 0; 128 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(); 129 I != MBB->livein_end(); ) { 130 MCPhysReg Reg = I->PhysReg; 131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); 132 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 133 Mask |= 1 << (Reg - X86::FP0); 134 if (RemoveFPs) { 135 I = MBB->removeLiveIn(I); 136 continue; 137 } 138 } 139 ++I; 140 } 141 return Mask; 142 } 143 144 // Partition all the CFG edges into LiveBundles. 145 void bundleCFGRecomputeKillFlags(MachineFunction &MF); 146 147 MachineBasicBlock *MBB = nullptr; // Current basic block 148 149 // The hardware keeps track of how many FP registers are live, so we have 150 // to model that exactly. Usually, each live register corresponds to an 151 // FP<n> register, but when dealing with calls, returns, and inline 152 // assembly, it is sometimes necessary to have live scratch registers. 153 unsigned Stack[8]; // FP<n> Registers in each stack slot... 154 unsigned StackTop = 0; // The current top of the FP stack. 155 156 enum { 157 NumFPRegs = 8 // Including scratch pseudo-registers. 158 }; 159 160 // For each live FP<n> register, point to its Stack[] entry. 161 // The first entries correspond to FP0-FP6, the rest are scratch registers 162 // used when we need slightly different live registers than what the 163 // register allocator thinks. 164 unsigned RegMap[NumFPRegs]; 165 166 // Set up our stack model to match the incoming registers to MBB. 167 void setupBlockStack(); 168 169 // Shuffle live registers to match the expectations of successor blocks. 170 void finishBlockStack(); 171 172 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 173 void dumpStack() const { 174 dbgs() << "Stack contents:"; 175 for (unsigned i = 0; i != StackTop; ++i) { 176 dbgs() << " FP" << Stack[i]; 177 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 178 } 179 } 180 #endif 181 182 /// getSlot - Return the stack slot number a particular register number is 183 /// in. 184 unsigned getSlot(unsigned RegNo) const { 185 assert(RegNo < NumFPRegs && "Regno out of range!"); 186 return RegMap[RegNo]; 187 } 188 189 /// isLive - Is RegNo currently live in the stack? 190 bool isLive(unsigned RegNo) const { 191 unsigned Slot = getSlot(RegNo); 192 return Slot < StackTop && Stack[Slot] == RegNo; 193 } 194 195 /// getStackEntry - Return the X86::FP<n> register in register ST(i). 196 unsigned getStackEntry(unsigned STi) const { 197 if (STi >= StackTop) 198 report_fatal_error("Access past stack top!"); 199 return Stack[StackTop-1-STi]; 200 } 201 202 /// getSTReg - Return the X86::ST(i) register which contains the specified 203 /// FP<RegNo> register. 204 unsigned getSTReg(unsigned RegNo) const { 205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; 206 } 207 208 // pushReg - Push the specified FP<n> register onto the stack. 209 void pushReg(unsigned Reg) { 210 assert(Reg < NumFPRegs && "Register number out of range!"); 211 if (StackTop >= 8) 212 report_fatal_error("Stack overflow!"); 213 Stack[StackTop] = Reg; 214 RegMap[Reg] = StackTop++; 215 } 216 217 // popReg - Pop a register from the stack. 218 void popReg() { 219 if (StackTop == 0) 220 report_fatal_error("Cannot pop empty stack!"); 221 RegMap[Stack[--StackTop]] = ~0; // Update state 222 } 223 224 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 225 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { 226 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 227 if (isAtTop(RegNo)) return; 228 229 unsigned STReg = getSTReg(RegNo); 230 unsigned RegOnTop = getStackEntry(0); 231 232 // Swap the slots the regs are in. 233 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 234 235 // Swap stack slot contents. 236 if (RegMap[RegOnTop] >= StackTop) 237 report_fatal_error("Access past stack top!"); 238 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 239 240 // Emit an fxch to update the runtime processors version of the state. 241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 242 ++NumFXCH; 243 } 244 245 void duplicateToTop(unsigned RegNo, unsigned AsReg, 246 MachineBasicBlock::iterator I) { 247 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 248 unsigned STReg = getSTReg(RegNo); 249 pushReg(AsReg); // New register on top of stack 250 251 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 252 } 253 254 /// popStackAfter - Pop the current value off of the top of the FP stack 255 /// after the specified instruction. 256 void popStackAfter(MachineBasicBlock::iterator &I); 257 258 /// freeStackSlotAfter - Free the specified register from the register 259 /// stack, so that it is no longer in a register. If the register is 260 /// currently at the top of the stack, we just pop the current instruction, 261 /// otherwise we store the current top-of-stack into the specified slot, 262 /// then pop the top of stack. 263 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 264 265 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted 266 /// instruction. 267 MachineBasicBlock::iterator 268 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo); 269 270 /// Adjust the live registers to be the set in Mask. 271 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I); 272 273 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is 274 /// st(0), FP reg FixStack[1] is st(1) etc. 275 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount, 276 MachineBasicBlock::iterator I); 277 278 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 279 280 void handleCall(MachineBasicBlock::iterator &I); 281 void handleReturn(MachineBasicBlock::iterator &I); 282 void handleZeroArgFP(MachineBasicBlock::iterator &I); 283 void handleOneArgFP(MachineBasicBlock::iterator &I); 284 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 285 void handleTwoArgFP(MachineBasicBlock::iterator &I); 286 void handleCompareFP(MachineBasicBlock::iterator &I); 287 void handleCondMovFP(MachineBasicBlock::iterator &I); 288 void handleSpecialFP(MachineBasicBlock::iterator &I); 289 290 // Check if a COPY instruction is using FP registers. 291 static bool isFPCopy(MachineInstr &MI) { 292 Register DstReg = MI.getOperand(0).getReg(); 293 Register SrcReg = MI.getOperand(1).getReg(); 294 295 return X86::RFP80RegClass.contains(DstReg) || 296 X86::RFP80RegClass.contains(SrcReg); 297 } 298 299 void setKillFlags(MachineBasicBlock &MBB) const; 300 }; 301 } 302 303 char FPS::ID = 0; 304 305 INITIALIZE_PASS_BEGIN(FPS, DEBUG_TYPE, "X86 FP Stackifier", 306 false, false) 307 INITIALIZE_PASS_DEPENDENCY(EdgeBundles) 308 INITIALIZE_PASS_END(FPS, DEBUG_TYPE, "X86 FP Stackifier", 309 false, false) 310 311 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 312 313 /// getFPReg - Return the X86::FPx register number for the specified operand. 314 /// For example, this returns 3 for X86::FP3. 315 static unsigned getFPReg(const MachineOperand &MO) { 316 assert(MO.isReg() && "Expected an FP register!"); 317 Register Reg = MO.getReg(); 318 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 319 return Reg - X86::FP0; 320 } 321 322 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 323 /// register references into FP stack references. 324 /// 325 bool FPS::runOnMachineFunction(MachineFunction &MF) { 326 // We only need to run this pass if there are any FP registers used in this 327 // function. If it is all integer, there is nothing for us to do! 328 bool FPIsUsed = false; 329 330 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!"); 331 const MachineRegisterInfo &MRI = MF.getRegInfo(); 332 for (unsigned i = 0; i <= 6; ++i) 333 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) { 334 FPIsUsed = true; 335 break; 336 } 337 338 // Early exit. 339 if (!FPIsUsed) return false; 340 341 Bundles = &getAnalysis<EdgeBundles>(); 342 TII = MF.getSubtarget().getInstrInfo(); 343 344 // Prepare cross-MBB liveness. 345 bundleCFGRecomputeKillFlags(MF); 346 347 StackTop = 0; 348 349 // Process the function in depth first order so that we process at least one 350 // of the predecessors for every reachable block in the function. 351 df_iterator_default_set<MachineBasicBlock*> Processed; 352 MachineBasicBlock *Entry = &MF.front(); 353 354 LiveBundle &Bundle = 355 LiveBundles[Bundles->getBundle(Entry->getNumber(), false)]; 356 357 // In regcall convention, some FP registers may not be passed through 358 // the stack, so they will need to be assigned to the stack first 359 if ((Entry->getParent()->getFunction().getCallingConv() == 360 CallingConv::X86_RegCall) && (Bundle.Mask && !Bundle.FixCount)) { 361 // In the register calling convention, up to one FP argument could be 362 // saved in the first FP register. 363 // If bundle.mask is non-zero and Bundle.FixCount is zero, it means 364 // that the FP registers contain arguments. 365 // The actual value is passed in FP0. 366 // Here we fix the stack and mark FP0 as pre-assigned register. 367 assert((Bundle.Mask & 0xFE) == 0 && 368 "Only FP0 could be passed as an argument"); 369 Bundle.FixCount = 1; 370 Bundle.FixStack[0] = 0; 371 } 372 373 bool Changed = false; 374 for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed)) 375 Changed |= processBasicBlock(MF, *BB); 376 377 // Process any unreachable blocks in arbitrary order now. 378 if (MF.size() != Processed.size()) 379 for (MachineBasicBlock &BB : MF) 380 if (Processed.insert(&BB).second) 381 Changed |= processBasicBlock(MF, BB); 382 383 LiveBundles.clear(); 384 385 return Changed; 386 } 387 388 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and 389 /// live-out sets for the FP registers. Consistent means that the set of 390 /// registers live-out from a block is identical to the live-in set of all 391 /// successors. This is not enforced by the normal live-in lists since 392 /// registers may be implicitly defined, or not used by all successors. 393 void FPS::bundleCFGRecomputeKillFlags(MachineFunction &MF) { 394 assert(LiveBundles.empty() && "Stale data in LiveBundles"); 395 LiveBundles.resize(Bundles->getNumBundles()); 396 397 // Gather the actual live-in masks for all MBBs. 398 for (MachineBasicBlock &MBB : MF) { 399 setKillFlags(MBB); 400 401 const unsigned Mask = calcLiveInMask(&MBB, false); 402 if (!Mask) 403 continue; 404 // Update MBB ingoing bundle mask. 405 LiveBundles[Bundles->getBundle(MBB.getNumber(), false)].Mask |= Mask; 406 } 407 } 408 409 /// processBasicBlock - Loop over all of the instructions in the basic block, 410 /// transforming FP instructions into their stack form. 411 /// 412 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 413 bool Changed = false; 414 MBB = &BB; 415 416 setupBlockStack(); 417 418 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 419 MachineInstr &MI = *I; 420 uint64_t Flags = MI.getDesc().TSFlags; 421 422 unsigned FPInstClass = Flags & X86II::FPTypeMask; 423 if (MI.isInlineAsm()) 424 FPInstClass = X86II::SpecialFP; 425 426 if (MI.isCopy() && isFPCopy(MI)) 427 FPInstClass = X86II::SpecialFP; 428 429 if (MI.isImplicitDef() && 430 X86::RFP80RegClass.contains(MI.getOperand(0).getReg())) 431 FPInstClass = X86II::SpecialFP; 432 433 if (MI.isCall()) 434 FPInstClass = X86II::SpecialFP; 435 436 if (FPInstClass == X86II::NotFP) 437 continue; // Efficiently ignore non-fp insts! 438 439 MachineInstr *PrevMI = nullptr; 440 if (I != BB.begin()) 441 PrevMI = &*std::prev(I); 442 443 ++NumFP; // Keep track of # of pseudo instrs 444 LLVM_DEBUG(dbgs() << "\nFPInst:\t" << MI); 445 446 // Get dead variables list now because the MI pointer may be deleted as part 447 // of processing! 448 SmallVector<unsigned, 8> DeadRegs; 449 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 450 const MachineOperand &MO = MI.getOperand(i); 451 if (MO.isReg() && MO.isDead()) 452 DeadRegs.push_back(MO.getReg()); 453 } 454 455 switch (FPInstClass) { 456 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 457 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 458 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 459 case X86II::TwoArgFP: handleTwoArgFP(I); break; 460 case X86II::CompareFP: handleCompareFP(I); break; 461 case X86II::CondMovFP: handleCondMovFP(I); break; 462 case X86II::SpecialFP: handleSpecialFP(I); break; 463 default: llvm_unreachable("Unknown FP Type!"); 464 } 465 466 // Check to see if any of the values defined by this instruction are dead 467 // after definition. If so, pop them. 468 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { 469 unsigned Reg = DeadRegs[i]; 470 // Check if Reg is live on the stack. An inline-asm register operand that 471 // is in the clobber list and marked dead might not be live on the stack. 472 static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers"); 473 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) { 474 LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n"); 475 freeStackSlotAfter(I, Reg-X86::FP0); 476 } 477 } 478 479 // Print out all of the instructions expanded to if -debug 480 LLVM_DEBUG({ 481 MachineBasicBlock::iterator PrevI = PrevMI; 482 if (I == PrevI) { 483 dbgs() << "Just deleted pseudo instruction\n"; 484 } else { 485 MachineBasicBlock::iterator Start = I; 486 // Rewind to first instruction newly inserted. 487 while (Start != BB.begin() && std::prev(Start) != PrevI) 488 --Start; 489 dbgs() << "Inserted instructions:\n\t"; 490 Start->print(dbgs()); 491 while (++Start != std::next(I)) { 492 } 493 } 494 dumpStack(); 495 }); 496 (void)PrevMI; 497 498 Changed = true; 499 } 500 501 finishBlockStack(); 502 503 return Changed; 504 } 505 506 /// setupBlockStack - Use the live bundles to set up our model of the stack 507 /// to match predecessors' live out stack. 508 void FPS::setupBlockStack() { 509 LLVM_DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB) 510 << " derived from " << MBB->getName() << ".\n"); 511 StackTop = 0; 512 // Get the live-in bundle for MBB. 513 const LiveBundle &Bundle = 514 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)]; 515 516 if (!Bundle.Mask) { 517 LLVM_DEBUG(dbgs() << "Block has no FP live-ins.\n"); 518 return; 519 } 520 521 // Depth-first iteration should ensure that we always have an assigned stack. 522 assert(Bundle.isFixed() && "Reached block before any predecessors"); 523 524 // Push the fixed live-in registers. 525 for (unsigned i = Bundle.FixCount; i > 0; --i) { 526 LLVM_DEBUG(dbgs() << "Live-in st(" << (i - 1) << "): %fp" 527 << unsigned(Bundle.FixStack[i - 1]) << '\n'); 528 pushReg(Bundle.FixStack[i-1]); 529 } 530 531 // Kill off unwanted live-ins. This can happen with a critical edge. 532 // FIXME: We could keep these live registers around as zombies. They may need 533 // to be revived at the end of a short block. It might save a few instrs. 534 unsigned Mask = calcLiveInMask(MBB, /*RemoveFPs=*/true); 535 adjustLiveRegs(Mask, MBB->begin()); 536 LLVM_DEBUG(MBB->dump()); 537 } 538 539 /// finishBlockStack - Revive live-outs that are implicitly defined out of 540 /// MBB. Shuffle live registers to match the expected fixed stack of any 541 /// predecessors, and ensure that all predecessors are expecting the same 542 /// stack. 543 void FPS::finishBlockStack() { 544 // The RET handling below takes care of return blocks for us. 545 if (MBB->succ_empty()) 546 return; 547 548 LLVM_DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB) 549 << " derived from " << MBB->getName() << ".\n"); 550 551 // Get MBB's live-out bundle. 552 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true); 553 LiveBundle &Bundle = LiveBundles[BundleIdx]; 554 555 // We may need to kill and define some registers to match successors. 556 // FIXME: This can probably be combined with the shuffle below. 557 MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); 558 adjustLiveRegs(Bundle.Mask, Term); 559 560 if (!Bundle.Mask) { 561 LLVM_DEBUG(dbgs() << "No live-outs.\n"); 562 return; 563 } 564 565 // Has the stack order been fixed yet? 566 LLVM_DEBUG(dbgs() << "LB#" << BundleIdx << ": "); 567 if (Bundle.isFixed()) { 568 LLVM_DEBUG(dbgs() << "Shuffling stack to match.\n"); 569 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term); 570 } else { 571 // Not fixed yet, we get to choose. 572 LLVM_DEBUG(dbgs() << "Fixing stack order now.\n"); 573 Bundle.FixCount = StackTop; 574 for (unsigned i = 0; i < StackTop; ++i) 575 Bundle.FixStack[i] = getStackEntry(i); 576 } 577 } 578 579 580 //===----------------------------------------------------------------------===// 581 // Efficient Lookup Table Support 582 //===----------------------------------------------------------------------===// 583 584 namespace { 585 struct TableEntry { 586 uint16_t from; 587 uint16_t to; 588 bool operator<(const TableEntry &TE) const { return from < TE.from; } 589 friend bool operator<(const TableEntry &TE, unsigned V) { 590 return TE.from < V; 591 } 592 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V, 593 const TableEntry &TE) { 594 return V < TE.from; 595 } 596 }; 597 } 598 599 static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) { 600 const TableEntry *I = llvm::lower_bound(Table, Opcode); 601 if (I != Table.end() && I->from == Opcode) 602 return I->to; 603 return -1; 604 } 605 606 #ifdef NDEBUG 607 #define ASSERT_SORTED(TABLE) 608 #else 609 #define ASSERT_SORTED(TABLE) \ 610 { \ 611 static std::atomic<bool> TABLE##Checked(false); \ 612 if (!TABLE##Checked.load(std::memory_order_relaxed)) { \ 613 assert(is_sorted(TABLE) && \ 614 "All lookup tables must be sorted for efficient access!"); \ 615 TABLE##Checked.store(true, std::memory_order_relaxed); \ 616 } \ 617 } 618 #endif 619 620 //===----------------------------------------------------------------------===// 621 // Register File -> Register Stack Mapping Methods 622 //===----------------------------------------------------------------------===// 623 624 // OpcodeTable - Sorted map of register instructions to their stack version. 625 // The first element is an register file pseudo instruction, the second is the 626 // concrete X86 instruction which uses the register stack. 627 // 628 static const TableEntry OpcodeTable[] = { 629 { X86::ABS_Fp32 , X86::ABS_F }, 630 { X86::ABS_Fp64 , X86::ABS_F }, 631 { X86::ABS_Fp80 , X86::ABS_F }, 632 { X86::ADD_Fp32m , X86::ADD_F32m }, 633 { X86::ADD_Fp64m , X86::ADD_F64m }, 634 { X86::ADD_Fp64m32 , X86::ADD_F32m }, 635 { X86::ADD_Fp80m32 , X86::ADD_F32m }, 636 { X86::ADD_Fp80m64 , X86::ADD_F64m }, 637 { X86::ADD_FpI16m32 , X86::ADD_FI16m }, 638 { X86::ADD_FpI16m64 , X86::ADD_FI16m }, 639 { X86::ADD_FpI16m80 , X86::ADD_FI16m }, 640 { X86::ADD_FpI32m32 , X86::ADD_FI32m }, 641 { X86::ADD_FpI32m64 , X86::ADD_FI32m }, 642 { X86::ADD_FpI32m80 , X86::ADD_FI32m }, 643 { X86::CHS_Fp32 , X86::CHS_F }, 644 { X86::CHS_Fp64 , X86::CHS_F }, 645 { X86::CHS_Fp80 , X86::CHS_F }, 646 { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, 647 { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, 648 { X86::CMOVBE_Fp80 , X86::CMOVBE_F }, 649 { X86::CMOVB_Fp32 , X86::CMOVB_F }, 650 { X86::CMOVB_Fp64 , X86::CMOVB_F }, 651 { X86::CMOVB_Fp80 , X86::CMOVB_F }, 652 { X86::CMOVE_Fp32 , X86::CMOVE_F }, 653 { X86::CMOVE_Fp64 , X86::CMOVE_F }, 654 { X86::CMOVE_Fp80 , X86::CMOVE_F }, 655 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, 656 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, 657 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F }, 658 { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, 659 { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, 660 { X86::CMOVNB_Fp80 , X86::CMOVNB_F }, 661 { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, 662 { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, 663 { X86::CMOVNE_Fp80 , X86::CMOVNE_F }, 664 { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, 665 { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, 666 { X86::CMOVNP_Fp80 , X86::CMOVNP_F }, 667 { X86::CMOVP_Fp32 , X86::CMOVP_F }, 668 { X86::CMOVP_Fp64 , X86::CMOVP_F }, 669 { X86::CMOVP_Fp80 , X86::CMOVP_F }, 670 { X86::COM_FpIr32 , X86::COM_FIr }, 671 { X86::COM_FpIr64 , X86::COM_FIr }, 672 { X86::COM_FpIr80 , X86::COM_FIr }, 673 { X86::COM_Fpr32 , X86::COM_FST0r }, 674 { X86::COM_Fpr64 , X86::COM_FST0r }, 675 { X86::COM_Fpr80 , X86::COM_FST0r }, 676 { X86::DIVR_Fp32m , X86::DIVR_F32m }, 677 { X86::DIVR_Fp64m , X86::DIVR_F64m }, 678 { X86::DIVR_Fp64m32 , X86::DIVR_F32m }, 679 { X86::DIVR_Fp80m32 , X86::DIVR_F32m }, 680 { X86::DIVR_Fp80m64 , X86::DIVR_F64m }, 681 { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, 682 { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, 683 { X86::DIVR_FpI16m80, X86::DIVR_FI16m}, 684 { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, 685 { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, 686 { X86::DIVR_FpI32m80, X86::DIVR_FI32m}, 687 { X86::DIV_Fp32m , X86::DIV_F32m }, 688 { X86::DIV_Fp64m , X86::DIV_F64m }, 689 { X86::DIV_Fp64m32 , X86::DIV_F32m }, 690 { X86::DIV_Fp80m32 , X86::DIV_F32m }, 691 { X86::DIV_Fp80m64 , X86::DIV_F64m }, 692 { X86::DIV_FpI16m32 , X86::DIV_FI16m }, 693 { X86::DIV_FpI16m64 , X86::DIV_FI16m }, 694 { X86::DIV_FpI16m80 , X86::DIV_FI16m }, 695 { X86::DIV_FpI32m32 , X86::DIV_FI32m }, 696 { X86::DIV_FpI32m64 , X86::DIV_FI32m }, 697 { X86::DIV_FpI32m80 , X86::DIV_FI32m }, 698 { X86::ILD_Fp16m32 , X86::ILD_F16m }, 699 { X86::ILD_Fp16m64 , X86::ILD_F16m }, 700 { X86::ILD_Fp16m80 , X86::ILD_F16m }, 701 { X86::ILD_Fp32m32 , X86::ILD_F32m }, 702 { X86::ILD_Fp32m64 , X86::ILD_F32m }, 703 { X86::ILD_Fp32m80 , X86::ILD_F32m }, 704 { X86::ILD_Fp64m32 , X86::ILD_F64m }, 705 { X86::ILD_Fp64m64 , X86::ILD_F64m }, 706 { X86::ILD_Fp64m80 , X86::ILD_F64m }, 707 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, 708 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, 709 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m}, 710 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, 711 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, 712 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m}, 713 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, 714 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, 715 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m}, 716 { X86::IST_Fp16m32 , X86::IST_F16m }, 717 { X86::IST_Fp16m64 , X86::IST_F16m }, 718 { X86::IST_Fp16m80 , X86::IST_F16m }, 719 { X86::IST_Fp32m32 , X86::IST_F32m }, 720 { X86::IST_Fp32m64 , X86::IST_F32m }, 721 { X86::IST_Fp32m80 , X86::IST_F32m }, 722 { X86::IST_Fp64m32 , X86::IST_FP64m }, 723 { X86::IST_Fp64m64 , X86::IST_FP64m }, 724 { X86::IST_Fp64m80 , X86::IST_FP64m }, 725 { X86::LD_Fp032 , X86::LD_F0 }, 726 { X86::LD_Fp064 , X86::LD_F0 }, 727 { X86::LD_Fp080 , X86::LD_F0 }, 728 { X86::LD_Fp132 , X86::LD_F1 }, 729 { X86::LD_Fp164 , X86::LD_F1 }, 730 { X86::LD_Fp180 , X86::LD_F1 }, 731 { X86::LD_Fp32m , X86::LD_F32m }, 732 { X86::LD_Fp32m64 , X86::LD_F32m }, 733 { X86::LD_Fp32m80 , X86::LD_F32m }, 734 { X86::LD_Fp64m , X86::LD_F64m }, 735 { X86::LD_Fp64m80 , X86::LD_F64m }, 736 { X86::LD_Fp80m , X86::LD_F80m }, 737 { X86::MUL_Fp32m , X86::MUL_F32m }, 738 { X86::MUL_Fp64m , X86::MUL_F64m }, 739 { X86::MUL_Fp64m32 , X86::MUL_F32m }, 740 { X86::MUL_Fp80m32 , X86::MUL_F32m }, 741 { X86::MUL_Fp80m64 , X86::MUL_F64m }, 742 { X86::MUL_FpI16m32 , X86::MUL_FI16m }, 743 { X86::MUL_FpI16m64 , X86::MUL_FI16m }, 744 { X86::MUL_FpI16m80 , X86::MUL_FI16m }, 745 { X86::MUL_FpI32m32 , X86::MUL_FI32m }, 746 { X86::MUL_FpI32m64 , X86::MUL_FI32m }, 747 { X86::MUL_FpI32m80 , X86::MUL_FI32m }, 748 { X86::SQRT_Fp32 , X86::SQRT_F }, 749 { X86::SQRT_Fp64 , X86::SQRT_F }, 750 { X86::SQRT_Fp80 , X86::SQRT_F }, 751 { X86::ST_Fp32m , X86::ST_F32m }, 752 { X86::ST_Fp64m , X86::ST_F64m }, 753 { X86::ST_Fp64m32 , X86::ST_F32m }, 754 { X86::ST_Fp80m32 , X86::ST_F32m }, 755 { X86::ST_Fp80m64 , X86::ST_F64m }, 756 { X86::ST_FpP80m , X86::ST_FP80m }, 757 { X86::SUBR_Fp32m , X86::SUBR_F32m }, 758 { X86::SUBR_Fp64m , X86::SUBR_F64m }, 759 { X86::SUBR_Fp64m32 , X86::SUBR_F32m }, 760 { X86::SUBR_Fp80m32 , X86::SUBR_F32m }, 761 { X86::SUBR_Fp80m64 , X86::SUBR_F64m }, 762 { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, 763 { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, 764 { X86::SUBR_FpI16m80, X86::SUBR_FI16m}, 765 { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, 766 { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, 767 { X86::SUBR_FpI32m80, X86::SUBR_FI32m}, 768 { X86::SUB_Fp32m , X86::SUB_F32m }, 769 { X86::SUB_Fp64m , X86::SUB_F64m }, 770 { X86::SUB_Fp64m32 , X86::SUB_F32m }, 771 { X86::SUB_Fp80m32 , X86::SUB_F32m }, 772 { X86::SUB_Fp80m64 , X86::SUB_F64m }, 773 { X86::SUB_FpI16m32 , X86::SUB_FI16m }, 774 { X86::SUB_FpI16m64 , X86::SUB_FI16m }, 775 { X86::SUB_FpI16m80 , X86::SUB_FI16m }, 776 { X86::SUB_FpI32m32 , X86::SUB_FI32m }, 777 { X86::SUB_FpI32m64 , X86::SUB_FI32m }, 778 { X86::SUB_FpI32m80 , X86::SUB_FI32m }, 779 { X86::TST_Fp32 , X86::TST_F }, 780 { X86::TST_Fp64 , X86::TST_F }, 781 { X86::TST_Fp80 , X86::TST_F }, 782 { X86::UCOM_FpIr32 , X86::UCOM_FIr }, 783 { X86::UCOM_FpIr64 , X86::UCOM_FIr }, 784 { X86::UCOM_FpIr80 , X86::UCOM_FIr }, 785 { X86::UCOM_Fpr32 , X86::UCOM_Fr }, 786 { X86::UCOM_Fpr64 , X86::UCOM_Fr }, 787 { X86::UCOM_Fpr80 , X86::UCOM_Fr }, 788 { X86::XAM_Fp32 , X86::XAM_F }, 789 { X86::XAM_Fp64 , X86::XAM_F }, 790 { X86::XAM_Fp80 , X86::XAM_F }, 791 }; 792 793 static unsigned getConcreteOpcode(unsigned Opcode) { 794 ASSERT_SORTED(OpcodeTable); 795 int Opc = Lookup(OpcodeTable, Opcode); 796 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 797 return Opc; 798 } 799 800 //===----------------------------------------------------------------------===// 801 // Helper Methods 802 //===----------------------------------------------------------------------===// 803 804 // PopTable - Sorted map of instructions to their popping version. The first 805 // element is an instruction, the second is the version which pops. 806 // 807 static const TableEntry PopTable[] = { 808 { X86::ADD_FrST0 , X86::ADD_FPrST0 }, 809 810 { X86::COMP_FST0r, X86::FCOMPP }, 811 { X86::COM_FIr , X86::COM_FIPr }, 812 { X86::COM_FST0r , X86::COMP_FST0r }, 813 814 { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, 815 { X86::DIV_FrST0 , X86::DIV_FPrST0 }, 816 817 { X86::IST_F16m , X86::IST_FP16m }, 818 { X86::IST_F32m , X86::IST_FP32m }, 819 820 { X86::MUL_FrST0 , X86::MUL_FPrST0 }, 821 822 { X86::ST_F32m , X86::ST_FP32m }, 823 { X86::ST_F64m , X86::ST_FP64m }, 824 { X86::ST_Frr , X86::ST_FPrr }, 825 826 { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, 827 { X86::SUB_FrST0 , X86::SUB_FPrST0 }, 828 829 { X86::UCOM_FIr , X86::UCOM_FIPr }, 830 831 { X86::UCOM_FPr , X86::UCOM_FPPr }, 832 { X86::UCOM_Fr , X86::UCOM_FPr }, 833 }; 834 835 /// popStackAfter - Pop the current value off of the top of the FP stack after 836 /// the specified instruction. This attempts to be sneaky and combine the pop 837 /// into the instruction itself if possible. The iterator is left pointing to 838 /// the last instruction, be it a new pop instruction inserted, or the old 839 /// instruction if it was modified in place. 840 /// 841 void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 842 MachineInstr &MI = *I; 843 const DebugLoc &dl = MI.getDebugLoc(); 844 ASSERT_SORTED(PopTable); 845 846 popReg(); 847 848 // Check to see if there is a popping version of this instruction... 849 int Opcode = Lookup(PopTable, I->getOpcode()); 850 if (Opcode != -1) { 851 I->setDesc(TII->get(Opcode)); 852 if (Opcode == X86::FCOMPP || Opcode == X86::UCOM_FPPr) 853 I->RemoveOperand(0); 854 } else { // Insert an explicit pop 855 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 856 } 857 } 858 859 /// freeStackSlotAfter - Free the specified register from the register stack, so 860 /// that it is no longer in a register. If the register is currently at the top 861 /// of the stack, we just pop the current instruction, otherwise we store the 862 /// current top-of-stack into the specified slot, then pop the top of stack. 863 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 864 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 865 popStackAfter(I); 866 return; 867 } 868 869 // Otherwise, store the top of stack into the dead slot, killing the operand 870 // without having to add in an explicit xchg then pop. 871 // 872 I = freeStackSlotBefore(++I, FPRegNo); 873 } 874 875 /// freeStackSlotBefore - Free the specified register without trying any 876 /// folding. 877 MachineBasicBlock::iterator 878 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) { 879 unsigned STReg = getSTReg(FPRegNo); 880 unsigned OldSlot = getSlot(FPRegNo); 881 unsigned TopReg = Stack[StackTop-1]; 882 Stack[OldSlot] = TopReg; 883 RegMap[TopReg] = OldSlot; 884 RegMap[FPRegNo] = ~0; 885 Stack[--StackTop] = ~0; 886 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)) 887 .addReg(STReg) 888 .getInstr(); 889 } 890 891 /// adjustLiveRegs - Kill and revive registers such that exactly the FP 892 /// registers with a bit in Mask are live. 893 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { 894 unsigned Defs = Mask; 895 unsigned Kills = 0; 896 for (unsigned i = 0; i < StackTop; ++i) { 897 unsigned RegNo = Stack[i]; 898 if (!(Defs & (1 << RegNo))) 899 // This register is live, but we don't want it. 900 Kills |= (1 << RegNo); 901 else 902 // We don't need to imp-def this live register. 903 Defs &= ~(1 << RegNo); 904 } 905 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?"); 906 907 // Produce implicit-defs for free by using killed registers. 908 while (Kills && Defs) { 909 unsigned KReg = countTrailingZeros(Kills); 910 unsigned DReg = countTrailingZeros(Defs); 911 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg 912 << "\n"); 913 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); 914 std::swap(RegMap[KReg], RegMap[DReg]); 915 Kills &= ~(1 << KReg); 916 Defs &= ~(1 << DReg); 917 } 918 919 // Kill registers by popping. 920 if (Kills && I != MBB->begin()) { 921 MachineBasicBlock::iterator I2 = std::prev(I); 922 while (StackTop) { 923 unsigned KReg = getStackEntry(0); 924 if (!(Kills & (1 << KReg))) 925 break; 926 LLVM_DEBUG(dbgs() << "Popping %fp" << KReg << "\n"); 927 popStackAfter(I2); 928 Kills &= ~(1 << KReg); 929 } 930 } 931 932 // Manually kill the rest. 933 while (Kills) { 934 unsigned KReg = countTrailingZeros(Kills); 935 LLVM_DEBUG(dbgs() << "Killing %fp" << KReg << "\n"); 936 freeStackSlotBefore(I, KReg); 937 Kills &= ~(1 << KReg); 938 } 939 940 // Load zeros for all the imp-defs. 941 while(Defs) { 942 unsigned DReg = countTrailingZeros(Defs); 943 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); 944 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); 945 pushReg(DReg); 946 Defs &= ~(1 << DReg); 947 } 948 949 // Now we should have the correct registers live. 950 LLVM_DEBUG(dumpStack()); 951 assert(StackTop == countPopulation(Mask) && "Live count mismatch"); 952 } 953 954 /// shuffleStackTop - emit fxch instructions before I to shuffle the top 955 /// FixCount entries into the order given by FixStack. 956 /// FIXME: Is there a better algorithm than insertion sort? 957 void FPS::shuffleStackTop(const unsigned char *FixStack, 958 unsigned FixCount, 959 MachineBasicBlock::iterator I) { 960 // Move items into place, starting from the desired stack bottom. 961 while (FixCount--) { 962 // Old register at position FixCount. 963 unsigned OldReg = getStackEntry(FixCount); 964 // Desired register at position FixCount. 965 unsigned Reg = FixStack[FixCount]; 966 if (Reg == OldReg) 967 continue; 968 // (Reg st0) (OldReg st0) = (Reg OldReg st0) 969 moveToTop(Reg, I); 970 if (FixCount > 0) 971 moveToTop(OldReg, I); 972 } 973 LLVM_DEBUG(dumpStack()); 974 } 975 976 977 //===----------------------------------------------------------------------===// 978 // Instruction transformation implementation 979 //===----------------------------------------------------------------------===// 980 981 void FPS::handleCall(MachineBasicBlock::iterator &I) { 982 MachineInstr &MI = *I; 983 unsigned STReturns = 0; 984 985 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 986 MachineOperand &Op = MI.getOperand(i); 987 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 988 continue; 989 990 assert(Op.isImplicit() && "Expected implicit def/use"); 991 992 if (Op.isDef()) 993 STReturns |= 1 << getFPReg(Op); 994 995 // Remove the operand so that later passes don't see it. 996 MI.RemoveOperand(i); 997 --i; 998 --e; 999 } 1000 1001 unsigned N = countTrailingOnes(STReturns); 1002 1003 // FP registers used for function return must be consecutive starting at 1004 // FP0 1005 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2)); 1006 1007 // Reset the FP Stack - It is required because of possible leftovers from 1008 // passed arguments. The caller should assume that the FP stack is 1009 // returned empty (unless the callee returns values on FP stack). 1010 while (StackTop > 0) 1011 popReg(); 1012 1013 for (unsigned I = 0; I < N; ++I) 1014 pushReg(N - I - 1); 1015 } 1016 1017 /// If RET has an FP register use operand, pass the first one in ST(0) and 1018 /// the second one in ST(1). 1019 void FPS::handleReturn(MachineBasicBlock::iterator &I) { 1020 MachineInstr &MI = *I; 1021 1022 // Find the register operands. 1023 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; 1024 unsigned LiveMask = 0; 1025 1026 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1027 MachineOperand &Op = MI.getOperand(i); 1028 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1029 continue; 1030 // FP Register uses must be kills unless there are two uses of the same 1031 // register, in which case only one will be a kill. 1032 assert(Op.isUse() && 1033 (Op.isKill() || // Marked kill. 1034 getFPReg(Op) == FirstFPRegOp || // Second instance. 1035 MI.killsRegister(Op.getReg())) && // Later use is marked kill. 1036 "Ret only defs operands, and values aren't live beyond it"); 1037 1038 if (FirstFPRegOp == ~0U) 1039 FirstFPRegOp = getFPReg(Op); 1040 else { 1041 assert(SecondFPRegOp == ~0U && "More than two fp operands!"); 1042 SecondFPRegOp = getFPReg(Op); 1043 } 1044 LiveMask |= (1 << getFPReg(Op)); 1045 1046 // Remove the operand so that later passes don't see it. 1047 MI.RemoveOperand(i); 1048 --i; 1049 --e; 1050 } 1051 1052 // We may have been carrying spurious live-ins, so make sure only the 1053 // returned registers are left live. 1054 adjustLiveRegs(LiveMask, MI); 1055 if (!LiveMask) return; // Quick check to see if any are possible. 1056 1057 // There are only four possibilities here: 1058 // 1) we are returning a single FP value. In this case, it has to be in 1059 // ST(0) already, so just declare success by removing the value from the 1060 // FP Stack. 1061 if (SecondFPRegOp == ~0U) { 1062 // Assert that the top of stack contains the right FP register. 1063 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) && 1064 "Top of stack not the right register for RET!"); 1065 1066 // Ok, everything is good, mark the value as not being on the stack 1067 // anymore so that our assertion about the stack being empty at end of 1068 // block doesn't fire. 1069 StackTop = 0; 1070 return; 1071 } 1072 1073 // Otherwise, we are returning two values: 1074 // 2) If returning the same value for both, we only have one thing in the FP 1075 // stack. Consider: RET FP1, FP1 1076 if (StackTop == 1) { 1077 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&& 1078 "Stack misconfiguration for RET!"); 1079 1080 // Duplicate the TOS so that we return it twice. Just pick some other FPx 1081 // register to hold it. 1082 unsigned NewReg = ScratchFPReg; 1083 duplicateToTop(FirstFPRegOp, NewReg, MI); 1084 FirstFPRegOp = NewReg; 1085 } 1086 1087 /// Okay we know we have two different FPx operands now: 1088 assert(StackTop == 2 && "Must have two values live!"); 1089 1090 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently 1091 /// in ST(1). In this case, emit an fxch. 1092 if (getStackEntry(0) == SecondFPRegOp) { 1093 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live"); 1094 moveToTop(FirstFPRegOp, MI); 1095 } 1096 1097 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in 1098 /// ST(1). Just remove both from our understanding of the stack and return. 1099 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live"); 1100 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live"); 1101 StackTop = 0; 1102 } 1103 1104 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 1105 /// 1106 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 1107 MachineInstr &MI = *I; 1108 unsigned DestReg = getFPReg(MI.getOperand(0)); 1109 1110 // Change from the pseudo instruction to the concrete instruction. 1111 MI.RemoveOperand(0); // Remove the explicit ST(0) operand 1112 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1113 MI.addOperand( 1114 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true)); 1115 1116 // Result gets pushed on the stack. 1117 pushReg(DestReg); 1118 } 1119 1120 /// handleOneArgFP - fst <mem>, ST(0) 1121 /// 1122 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 1123 MachineInstr &MI = *I; 1124 unsigned NumOps = MI.getDesc().getNumOperands(); 1125 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) && 1126 "Can only handle fst* & ftst instructions!"); 1127 1128 // Is this the last use of the source register? 1129 unsigned Reg = getFPReg(MI.getOperand(NumOps - 1)); 1130 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg); 1131 1132 // FISTP64m is strange because there isn't a non-popping versions. 1133 // If we have one _and_ we don't want to pop the operand, duplicate the value 1134 // on the stack instead of moving it. This ensure that popping the value is 1135 // always ok. 1136 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m. 1137 // 1138 if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 || 1139 MI.getOpcode() == X86::ISTT_Fp16m32 || 1140 MI.getOpcode() == X86::ISTT_Fp32m32 || 1141 MI.getOpcode() == X86::ISTT_Fp64m32 || 1142 MI.getOpcode() == X86::IST_Fp64m64 || 1143 MI.getOpcode() == X86::ISTT_Fp16m64 || 1144 MI.getOpcode() == X86::ISTT_Fp32m64 || 1145 MI.getOpcode() == X86::ISTT_Fp64m64 || 1146 MI.getOpcode() == X86::IST_Fp64m80 || 1147 MI.getOpcode() == X86::ISTT_Fp16m80 || 1148 MI.getOpcode() == X86::ISTT_Fp32m80 || 1149 MI.getOpcode() == X86::ISTT_Fp64m80 || 1150 MI.getOpcode() == X86::ST_FpP80m)) { 1151 duplicateToTop(Reg, ScratchFPReg, I); 1152 } else { 1153 moveToTop(Reg, I); // Move to the top of the stack... 1154 } 1155 1156 // Convert from the pseudo instruction to the concrete instruction. 1157 MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand 1158 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1159 MI.addOperand( 1160 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true)); 1161 1162 if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m || 1163 MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m || 1164 MI.getOpcode() == X86::ST_FP80m) { 1165 if (StackTop == 0) 1166 report_fatal_error("Stack empty??"); 1167 --StackTop; 1168 } else if (KillsSrc) { // Last use of operand? 1169 popStackAfter(I); 1170 } 1171 } 1172 1173 1174 /// handleOneArgFPRW: Handle instructions that read from the top of stack and 1175 /// replace the value with a newly computed value. These instructions may have 1176 /// non-fp operands after their FP operands. 1177 /// 1178 /// Examples: 1179 /// R1 = fchs R2 1180 /// R1 = fadd R2, [mem] 1181 /// 1182 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 1183 MachineInstr &MI = *I; 1184 #ifndef NDEBUG 1185 unsigned NumOps = MI.getDesc().getNumOperands(); 1186 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); 1187 #endif 1188 1189 // Is this the last use of the source register? 1190 unsigned Reg = getFPReg(MI.getOperand(1)); 1191 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg); 1192 1193 if (KillsSrc) { 1194 // If this is the last use of the source register, just make sure it's on 1195 // the top of the stack. 1196 moveToTop(Reg, I); 1197 if (StackTop == 0) 1198 report_fatal_error("Stack cannot be empty!"); 1199 --StackTop; 1200 pushReg(getFPReg(MI.getOperand(0))); 1201 } else { 1202 // If this is not the last use of the source register, _copy_ it to the top 1203 // of the stack. 1204 duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I); 1205 } 1206 1207 // Change from the pseudo instruction to the concrete instruction. 1208 MI.RemoveOperand(1); // Drop the source operand. 1209 MI.RemoveOperand(0); // Drop the destination operand. 1210 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1211 } 1212 1213 1214 //===----------------------------------------------------------------------===// 1215 // Define tables of various ways to map pseudo instructions 1216 // 1217 1218 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 1219 static const TableEntry ForwardST0Table[] = { 1220 { X86::ADD_Fp32 , X86::ADD_FST0r }, 1221 { X86::ADD_Fp64 , X86::ADD_FST0r }, 1222 { X86::ADD_Fp80 , X86::ADD_FST0r }, 1223 { X86::DIV_Fp32 , X86::DIV_FST0r }, 1224 { X86::DIV_Fp64 , X86::DIV_FST0r }, 1225 { X86::DIV_Fp80 , X86::DIV_FST0r }, 1226 { X86::MUL_Fp32 , X86::MUL_FST0r }, 1227 { X86::MUL_Fp64 , X86::MUL_FST0r }, 1228 { X86::MUL_Fp80 , X86::MUL_FST0r }, 1229 { X86::SUB_Fp32 , X86::SUB_FST0r }, 1230 { X86::SUB_Fp64 , X86::SUB_FST0r }, 1231 { X86::SUB_Fp80 , X86::SUB_FST0r }, 1232 }; 1233 1234 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 1235 static const TableEntry ReverseST0Table[] = { 1236 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative 1237 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative 1238 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative 1239 { X86::DIV_Fp32 , X86::DIVR_FST0r }, 1240 { X86::DIV_Fp64 , X86::DIVR_FST0r }, 1241 { X86::DIV_Fp80 , X86::DIVR_FST0r }, 1242 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative 1243 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative 1244 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative 1245 { X86::SUB_Fp32 , X86::SUBR_FST0r }, 1246 { X86::SUB_Fp64 , X86::SUBR_FST0r }, 1247 { X86::SUB_Fp80 , X86::SUBR_FST0r }, 1248 }; 1249 1250 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 1251 static const TableEntry ForwardSTiTable[] = { 1252 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative 1253 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative 1254 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative 1255 { X86::DIV_Fp32 , X86::DIVR_FrST0 }, 1256 { X86::DIV_Fp64 , X86::DIVR_FrST0 }, 1257 { X86::DIV_Fp80 , X86::DIVR_FrST0 }, 1258 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative 1259 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative 1260 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative 1261 { X86::SUB_Fp32 , X86::SUBR_FrST0 }, 1262 { X86::SUB_Fp64 , X86::SUBR_FrST0 }, 1263 { X86::SUB_Fp80 , X86::SUBR_FrST0 }, 1264 }; 1265 1266 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 1267 static const TableEntry ReverseSTiTable[] = { 1268 { X86::ADD_Fp32 , X86::ADD_FrST0 }, 1269 { X86::ADD_Fp64 , X86::ADD_FrST0 }, 1270 { X86::ADD_Fp80 , X86::ADD_FrST0 }, 1271 { X86::DIV_Fp32 , X86::DIV_FrST0 }, 1272 { X86::DIV_Fp64 , X86::DIV_FrST0 }, 1273 { X86::DIV_Fp80 , X86::DIV_FrST0 }, 1274 { X86::MUL_Fp32 , X86::MUL_FrST0 }, 1275 { X86::MUL_Fp64 , X86::MUL_FrST0 }, 1276 { X86::MUL_Fp80 , X86::MUL_FrST0 }, 1277 { X86::SUB_Fp32 , X86::SUB_FrST0 }, 1278 { X86::SUB_Fp64 , X86::SUB_FrST0 }, 1279 { X86::SUB_Fp80 , X86::SUB_FrST0 }, 1280 }; 1281 1282 1283 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 1284 /// instructions which need to be simplified and possibly transformed. 1285 /// 1286 /// Result: ST(0) = fsub ST(0), ST(i) 1287 /// ST(i) = fsub ST(0), ST(i) 1288 /// ST(0) = fsubr ST(0), ST(i) 1289 /// ST(i) = fsubr ST(0), ST(i) 1290 /// 1291 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 1292 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 1293 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 1294 MachineInstr &MI = *I; 1295 1296 unsigned NumOperands = MI.getDesc().getNumOperands(); 1297 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 1298 unsigned Dest = getFPReg(MI.getOperand(0)); 1299 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); 1300 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1)); 1301 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0); 1302 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); 1303 const DebugLoc &dl = MI.getDebugLoc(); 1304 1305 unsigned TOS = getStackEntry(0); 1306 1307 // One of our operands must be on the top of the stack. If neither is yet, we 1308 // need to move one. 1309 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1310 // We can choose to move either operand to the top of the stack. If one of 1311 // the operands is killed by this instruction, we want that one so that we 1312 // can update right on top of the old version. 1313 if (KillsOp0) { 1314 moveToTop(Op0, I); // Move dead operand to TOS. 1315 TOS = Op0; 1316 } else if (KillsOp1) { 1317 moveToTop(Op1, I); 1318 TOS = Op1; 1319 } else { 1320 // All of the operands are live after this instruction executes, so we 1321 // cannot update on top of any operand. Because of this, we must 1322 // duplicate one of the stack elements to the top. It doesn't matter 1323 // which one we pick. 1324 // 1325 duplicateToTop(Op0, Dest, I); 1326 Op0 = TOS = Dest; 1327 KillsOp0 = true; 1328 } 1329 } else if (!KillsOp0 && !KillsOp1) { 1330 // If we DO have one of our operands at the top of the stack, but we don't 1331 // have a dead operand, we must duplicate one of the operands to a new slot 1332 // on the stack. 1333 duplicateToTop(Op0, Dest, I); 1334 Op0 = TOS = Dest; 1335 KillsOp0 = true; 1336 } 1337 1338 // Now we know that one of our operands is on the top of the stack, and at 1339 // least one of our operands is killed by this instruction. 1340 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 1341 "Stack conditions not set up right!"); 1342 1343 // We decide which form to use based on what is on the top of the stack, and 1344 // which operand is killed by this instruction. 1345 ArrayRef<TableEntry> InstTable; 1346 bool isForward = TOS == Op0; 1347 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 1348 if (updateST0) { 1349 if (isForward) 1350 InstTable = ForwardST0Table; 1351 else 1352 InstTable = ReverseST0Table; 1353 } else { 1354 if (isForward) 1355 InstTable = ForwardSTiTable; 1356 else 1357 InstTable = ReverseSTiTable; 1358 } 1359 1360 int Opcode = Lookup(InstTable, MI.getOpcode()); 1361 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 1362 1363 // NotTOS - The register which is not on the top of stack... 1364 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 1365 1366 // Replace the old instruction with a new instruction 1367 MBB->remove(&*I++); 1368 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); 1369 1370 if (!MI.mayRaiseFPException()) 1371 I->setFlag(MachineInstr::MIFlag::NoFPExcept); 1372 1373 // If both operands are killed, pop one off of the stack in addition to 1374 // overwriting the other one. 1375 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 1376 assert(!updateST0 && "Should have updated other operand!"); 1377 popStackAfter(I); // Pop the top of stack 1378 } 1379 1380 // Update stack information so that we know the destination register is now on 1381 // the stack. 1382 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 1383 assert(UpdatedSlot < StackTop && Dest < 7); 1384 Stack[UpdatedSlot] = Dest; 1385 RegMap[Dest] = UpdatedSlot; 1386 MBB->getParent()->DeleteMachineInstr(&MI); // Remove the old instruction 1387 } 1388 1389 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 1390 /// register arguments and no explicit destinations. 1391 /// 1392 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 1393 MachineInstr &MI = *I; 1394 1395 unsigned NumOperands = MI.getDesc().getNumOperands(); 1396 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 1397 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); 1398 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1)); 1399 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0); 1400 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); 1401 1402 // Make sure the first operand is on the top of stack, the other one can be 1403 // anywhere. 1404 moveToTop(Op0, I); 1405 1406 // Change from the pseudo instruction to the concrete instruction. 1407 MI.getOperand(0).setReg(getSTReg(Op1)); 1408 MI.RemoveOperand(1); 1409 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1410 1411 // If any of the operands are killed by this instruction, free them. 1412 if (KillsOp0) freeStackSlotAfter(I, Op0); 1413 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 1414 } 1415 1416 /// handleCondMovFP - Handle two address conditional move instructions. These 1417 /// instructions move a st(i) register to st(0) iff a condition is true. These 1418 /// instructions require that the first operand is at the top of the stack, but 1419 /// otherwise don't modify the stack at all. 1420 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 1421 MachineInstr &MI = *I; 1422 1423 unsigned Op0 = getFPReg(MI.getOperand(0)); 1424 unsigned Op1 = getFPReg(MI.getOperand(2)); 1425 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); 1426 1427 // The first operand *must* be on the top of the stack. 1428 moveToTop(Op0, I); 1429 1430 // Change the second operand to the stack register that the operand is in. 1431 // Change from the pseudo instruction to the concrete instruction. 1432 MI.RemoveOperand(0); 1433 MI.RemoveOperand(1); 1434 MI.getOperand(0).setReg(getSTReg(Op1)); 1435 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode()))); 1436 1437 // If we kill the second operand, make sure to pop it from the stack. 1438 if (Op0 != Op1 && KillsOp1) { 1439 // Get this value off of the register stack. 1440 freeStackSlotAfter(I, Op1); 1441 } 1442 } 1443 1444 1445 /// handleSpecialFP - Handle special instructions which behave unlike other 1446 /// floating point instructions. This is primarily intended for use by pseudo 1447 /// instructions. 1448 /// 1449 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { 1450 MachineInstr &MI = *Inst; 1451 1452 if (MI.isCall()) { 1453 handleCall(Inst); 1454 return; 1455 } 1456 1457 if (MI.isReturn()) { 1458 handleReturn(Inst); 1459 return; 1460 } 1461 1462 switch (MI.getOpcode()) { 1463 default: llvm_unreachable("Unknown SpecialFP instruction!"); 1464 case TargetOpcode::COPY: { 1465 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP. 1466 const MachineOperand &MO1 = MI.getOperand(1); 1467 const MachineOperand &MO0 = MI.getOperand(0); 1468 bool KillsSrc = MI.killsRegister(MO1.getReg()); 1469 1470 // FP <- FP copy. 1471 unsigned DstFP = getFPReg(MO0); 1472 unsigned SrcFP = getFPReg(MO1); 1473 assert(isLive(SrcFP) && "Cannot copy dead register"); 1474 if (KillsSrc) { 1475 // If the input operand is killed, we can just change the owner of the 1476 // incoming stack slot into the result. 1477 unsigned Slot = getSlot(SrcFP); 1478 Stack[Slot] = DstFP; 1479 RegMap[DstFP] = Slot; 1480 } else { 1481 // For COPY we just duplicate the specified value to a new stack slot. 1482 // This could be made better, but would require substantial changes. 1483 duplicateToTop(SrcFP, DstFP, Inst); 1484 } 1485 break; 1486 } 1487 1488 case TargetOpcode::IMPLICIT_DEF: { 1489 // All FP registers must be explicitly defined, so load a 0 instead. 1490 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0; 1491 LLVM_DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n'); 1492 BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0)); 1493 pushReg(Reg); 1494 break; 1495 } 1496 1497 case TargetOpcode::INLINEASM: 1498 case TargetOpcode::INLINEASM_BR: { 1499 // The inline asm MachineInstr currently only *uses* FP registers for the 1500 // 'f' constraint. These should be turned into the current ST(x) register 1501 // in the machine instr. 1502 // 1503 // There are special rules for x87 inline assembly. The compiler must know 1504 // exactly how many registers are popped and pushed implicitly by the asm. 1505 // Otherwise it is not possible to restore the stack state after the inline 1506 // asm. 1507 // 1508 // There are 3 kinds of input operands: 1509 // 1510 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A 1511 // popped input operand must be in a fixed stack slot, and it is either 1512 // tied to an output operand, or in the clobber list. The MI has ST use 1513 // and def operands for these inputs. 1514 // 1515 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are 1516 // preserved by the inline asm. The fixed stack slots must be STn-STm 1517 // following the popped inputs. A fixed input operand cannot be tied to 1518 // an output or appear in the clobber list. The MI has ST use operands 1519 // and no defs for these inputs. 1520 // 1521 // 3. Preserved inputs. These inputs use the "f" constraint which is 1522 // represented as an FP register. The inline asm won't change these 1523 // stack slots. 1524 // 1525 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered 1526 // registers do not count as output operands. The inline asm changes the 1527 // stack as if it popped all the popped inputs and then pushed all the 1528 // output operands. 1529 1530 // Scan the assembly for ST registers used, defined and clobbered. We can 1531 // only tell clobbers from defs by looking at the asm descriptor. 1532 unsigned STUses = 0, STDefs = 0, STClobbers = 0; 1533 unsigned NumOps = 0; 1534 SmallSet<unsigned, 1> FRegIdx; 1535 unsigned RCID; 1536 1537 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands(); 1538 i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) { 1539 unsigned Flags = MI.getOperand(i).getImm(); 1540 1541 NumOps = InlineAsm::getNumOperandRegisters(Flags); 1542 if (NumOps != 1) 1543 continue; 1544 const MachineOperand &MO = MI.getOperand(i + 1); 1545 if (!MO.isReg()) 1546 continue; 1547 unsigned STReg = MO.getReg() - X86::FP0; 1548 if (STReg >= 8) 1549 continue; 1550 1551 // If the flag has a register class constraint, this must be an operand 1552 // with constraint "f". Record its index and continue. 1553 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { 1554 FRegIdx.insert(i + 1); 1555 continue; 1556 } 1557 1558 switch (InlineAsm::getKind(Flags)) { 1559 case InlineAsm::Kind_RegUse: 1560 STUses |= (1u << STReg); 1561 break; 1562 case InlineAsm::Kind_RegDef: 1563 case InlineAsm::Kind_RegDefEarlyClobber: 1564 STDefs |= (1u << STReg); 1565 break; 1566 case InlineAsm::Kind_Clobber: 1567 STClobbers |= (1u << STReg); 1568 break; 1569 default: 1570 break; 1571 } 1572 } 1573 1574 if (STUses && !isMask_32(STUses)) 1575 MI.emitError("fixed input regs must be last on the x87 stack"); 1576 unsigned NumSTUses = countTrailingOnes(STUses); 1577 1578 // Defs must be contiguous from the stack top. ST0-STn. 1579 if (STDefs && !isMask_32(STDefs)) { 1580 MI.emitError("output regs must be last on the x87 stack"); 1581 STDefs = NextPowerOf2(STDefs) - 1; 1582 } 1583 unsigned NumSTDefs = countTrailingOnes(STDefs); 1584 1585 // So must the clobbered stack slots. ST0-STm, m >= n. 1586 if (STClobbers && !isMask_32(STDefs | STClobbers)) 1587 MI.emitError("clobbers must be last on the x87 stack"); 1588 1589 // Popped inputs are the ones that are also clobbered or defined. 1590 unsigned STPopped = STUses & (STDefs | STClobbers); 1591 if (STPopped && !isMask_32(STPopped)) 1592 MI.emitError("implicitly popped regs must be last on the x87 stack"); 1593 unsigned NumSTPopped = countTrailingOnes(STPopped); 1594 1595 LLVM_DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops " 1596 << NumSTPopped << ", and defines " << NumSTDefs 1597 << " regs.\n"); 1598 1599 #ifndef NDEBUG 1600 // If any input operand uses constraint "f", all output register 1601 // constraints must be early-clobber defs. 1602 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) 1603 if (FRegIdx.count(I)) { 1604 assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 && 1605 "Operands with constraint \"f\" cannot overlap with defs"); 1606 } 1607 #endif 1608 1609 // Collect all FP registers (register operands with constraints "t", "u", 1610 // and "f") to kill afer the instruction. 1611 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff; 1612 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1613 MachineOperand &Op = MI.getOperand(i); 1614 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1615 continue; 1616 unsigned FPReg = getFPReg(Op); 1617 1618 // If we kill this operand, make sure to pop it from the stack after the 1619 // asm. We just remember it for now, and pop them all off at the end in 1620 // a batch. 1621 if (Op.isUse() && Op.isKill()) 1622 FPKills |= 1U << FPReg; 1623 } 1624 1625 // Do not include registers that are implicitly popped by defs/clobbers. 1626 FPKills &= ~(STDefs | STClobbers); 1627 1628 // Now we can rearrange the live registers to match what was requested. 1629 unsigned char STUsesArray[8]; 1630 1631 for (unsigned I = 0; I < NumSTUses; ++I) 1632 STUsesArray[I] = I; 1633 1634 shuffleStackTop(STUsesArray, NumSTUses, Inst); 1635 LLVM_DEBUG({ 1636 dbgs() << "Before asm: "; 1637 dumpStack(); 1638 }); 1639 1640 // With the stack layout fixed, rewrite the FP registers. 1641 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1642 MachineOperand &Op = MI.getOperand(i); 1643 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1644 continue; 1645 1646 unsigned FPReg = getFPReg(Op); 1647 1648 if (FRegIdx.count(i)) 1649 // Operand with constraint "f". 1650 Op.setReg(getSTReg(FPReg)); 1651 else 1652 // Operand with a single register class constraint ("t" or "u"). 1653 Op.setReg(X86::ST0 + FPReg); 1654 } 1655 1656 // Simulate the inline asm popping its inputs and pushing its outputs. 1657 StackTop -= NumSTPopped; 1658 1659 for (unsigned i = 0; i < NumSTDefs; ++i) 1660 pushReg(NumSTDefs - i - 1); 1661 1662 // If this asm kills any FP registers (is the last use of them) we must 1663 // explicitly emit pop instructions for them. Do this now after the asm has 1664 // executed so that the ST(x) numbers are not off (which would happen if we 1665 // did this inline with operand rewriting). 1666 // 1667 // Note: this might be a non-optimal pop sequence. We might be able to do 1668 // better by trying to pop in stack order or something. 1669 while (FPKills) { 1670 unsigned FPReg = countTrailingZeros(FPKills); 1671 if (isLive(FPReg)) 1672 freeStackSlotAfter(Inst, FPReg); 1673 FPKills &= ~(1U << FPReg); 1674 } 1675 1676 // Don't delete the inline asm! 1677 return; 1678 } 1679 } 1680 1681 Inst = MBB->erase(Inst); // Remove the pseudo instruction 1682 1683 // We want to leave I pointing to the previous instruction, but what if we 1684 // just erased the first instruction? 1685 if (Inst == MBB->begin()) { 1686 LLVM_DEBUG(dbgs() << "Inserting dummy KILL\n"); 1687 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL)); 1688 } else 1689 --Inst; 1690 } 1691 1692 void FPS::setKillFlags(MachineBasicBlock &MBB) const { 1693 const TargetRegisterInfo &TRI = 1694 *MBB.getParent()->getSubtarget().getRegisterInfo(); 1695 LivePhysRegs LPR(TRI); 1696 1697 LPR.addLiveOuts(MBB); 1698 1699 for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend(); 1700 I != E; ++I) { 1701 if (I->isDebugInstr()) 1702 continue; 1703 1704 std::bitset<8> Defs; 1705 SmallVector<MachineOperand *, 2> Uses; 1706 MachineInstr &MI = *I; 1707 1708 for (auto &MO : I->operands()) { 1709 if (!MO.isReg()) 1710 continue; 1711 1712 unsigned Reg = MO.getReg() - X86::FP0; 1713 1714 if (Reg >= 8) 1715 continue; 1716 1717 if (MO.isDef()) { 1718 Defs.set(Reg); 1719 if (!LPR.contains(MO.getReg())) 1720 MO.setIsDead(); 1721 } else 1722 Uses.push_back(&MO); 1723 } 1724 1725 for (auto *MO : Uses) 1726 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg())) 1727 MO->setIsKill(); 1728 1729 LPR.stepBackward(MI); 1730 } 1731 } 1732