1 //===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, other late
12 // optimizations, or simply the encoding of the instructions.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86InstrInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/Analysis/EHPersonalities.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
26 #include "llvm/IR/GlobalValue.h"
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "x86-pseudo"
30 
31 namespace {
32 class X86ExpandPseudo : public MachineFunctionPass {
33 public:
34   static char ID;
35   X86ExpandPseudo() : MachineFunctionPass(ID) {}
36 
37   void getAnalysisUsage(AnalysisUsage &AU) const override {
38     AU.setPreservesCFG();
39     AU.addPreservedID(MachineLoopInfoID);
40     AU.addPreservedID(MachineDominatorsID);
41     MachineFunctionPass::getAnalysisUsage(AU);
42   }
43 
44   const X86Subtarget *STI;
45   const X86InstrInfo *TII;
46   const X86RegisterInfo *TRI;
47   const X86FrameLowering *X86FL;
48 
49   bool runOnMachineFunction(MachineFunction &Fn) override;
50 
51   const char *getPassName() const override {
52     return "X86 pseudo instruction expansion pass";
53   }
54 
55 private:
56   bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
57   bool ExpandMBB(MachineBasicBlock &MBB);
58 };
59 char X86ExpandPseudo::ID = 0;
60 } // End anonymous namespace.
61 
62 /// If \p MBBI is a pseudo instruction, this method expands
63 /// it to the corresponding (sequence of) actual instruction(s).
64 /// \returns true if \p MBBI has been expanded.
65 bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
66                                MachineBasicBlock::iterator MBBI) {
67   MachineInstr &MI = *MBBI;
68   unsigned Opcode = MI.getOpcode();
69   DebugLoc DL = MBBI->getDebugLoc();
70   switch (Opcode) {
71   default:
72     return false;
73   case X86::TCRETURNdi:
74   case X86::TCRETURNri:
75   case X86::TCRETURNmi:
76   case X86::TCRETURNdi64:
77   case X86::TCRETURNri64:
78   case X86::TCRETURNmi64: {
79     bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
80     MachineOperand &JumpTarget = MBBI->getOperand(0);
81     MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
82     assert(StackAdjust.isImm() && "Expecting immediate value.");
83 
84     // Adjust stack pointer.
85     int StackAdj = StackAdjust.getImm();
86 
87     if (StackAdj) {
88       // Check for possible merge with preceding ADD instruction.
89       StackAdj += X86FL->mergeSPUpdates(MBB, MBBI, true);
90       X86FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);
91     }
92 
93     // Jump to label or value in register.
94     bool IsWin64 = STI->isTargetWin64();
95     if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdi64) {
96       unsigned Op = (Opcode == X86::TCRETURNdi)
97                         ? X86::TAILJMPd
98                         : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);
99       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
100       if (JumpTarget.isGlobal())
101         MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
102                              JumpTarget.getTargetFlags());
103       else {
104         assert(JumpTarget.isSymbol());
105         MIB.addExternalSymbol(JumpTarget.getSymbolName(),
106                               JumpTarget.getTargetFlags());
107       }
108     } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
109       unsigned Op = (Opcode == X86::TCRETURNmi)
110                         ? X86::TAILJMPm
111                         : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
112       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
113       for (unsigned i = 0; i != 5; ++i)
114         MIB.addOperand(MBBI->getOperand(i));
115     } else if (Opcode == X86::TCRETURNri64) {
116       BuildMI(MBB, MBBI, DL,
117               TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
118           .addReg(JumpTarget.getReg(), RegState::Kill);
119     } else {
120       BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
121           .addReg(JumpTarget.getReg(), RegState::Kill);
122     }
123 
124     MachineInstr *NewMI = std::prev(MBBI);
125     NewMI->copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
126 
127     // Delete the pseudo instruction TCRETURN.
128     MBB.erase(MBBI);
129 
130     return true;
131   }
132   case X86::EH_RETURN:
133   case X86::EH_RETURN64: {
134     MachineOperand &DestAddr = MBBI->getOperand(0);
135     assert(DestAddr.isReg() && "Offset should be in register!");
136     const bool Uses64BitFramePtr =
137         STI->isTarget64BitLP64() || STI->isTargetNaCl64();
138     unsigned StackPtr = TRI->getStackRegister();
139     BuildMI(MBB, MBBI, DL,
140             TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
141         .addReg(DestAddr.getReg());
142     // The EH_RETURN pseudo is really removed during the MC Lowering.
143     return true;
144   }
145   case X86::IRET: {
146     // Adjust stack to erase error code
147     int64_t StackAdj = MBBI->getOperand(0).getImm();
148     X86FL->emitSPUpdate(MBB, MBBI, StackAdj, true);
149     // Replace pseudo with machine iret
150     BuildMI(MBB, MBBI, DL,
151             TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));
152     MBB.erase(MBBI);
153     return true;
154   }
155   case X86::RET: {
156     // Adjust stack to erase error code
157     int64_t StackAdj = MBBI->getOperand(0).getImm();
158     MachineInstrBuilder MIB;
159     if (StackAdj == 0) {
160       MIB = BuildMI(MBB, MBBI, DL,
161                     TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL));
162     } else if (isUInt<16>(StackAdj)) {
163       MIB = BuildMI(MBB, MBBI, DL,
164                     TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL))
165                 .addImm(StackAdj);
166     } else {
167       assert(!STI->is64Bit() &&
168              "shouldn't need to do this for x86_64 targets!");
169       // A ret can only handle immediates as big as 2**16-1.  If we need to pop
170       // off bytes before the return address, we must do it manually.
171       BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
172       X86FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);
173       BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
174       MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
175     }
176     for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
177       MIB.addOperand(MBBI->getOperand(I));
178     MBB.erase(MBBI);
179     return true;
180   }
181   case X86::EH_RESTORE: {
182     // Restore ESP and EBP, and optionally ESI if required.
183     bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(
184         MBB.getParent()->getFunction()->getPersonalityFn()));
185     X86FL->restoreWin32EHStackPointers(MBB, MBBI, DL, /*RestoreSP=*/IsSEH);
186     MBBI->eraseFromParent();
187     return true;
188   }
189   case X86::LCMPXCHG8B_SAVE_EBX:
190   case X86::LCMPXCHG16B_SAVE_RBX: {
191     // Perform the following transformation.
192     // SaveRbx = pseudocmpxchg Addr, <4 opds for the address>, InArg, SaveRbx
193     // =>
194     // [E|R]BX = InArg
195     // actualcmpxchg Addr
196     // [E|R]BX = SaveRbx
197     const MachineOperand &InArg = MBBI->getOperand(6);
198     unsigned SaveRbx = MBBI->getOperand(7).getReg();
199 
200     unsigned ActualInArg =
201         Opcode == X86::LCMPXCHG8B_SAVE_EBX ? X86::EBX : X86::RBX;
202     // Copy the input argument of the pseudo into the argument of the
203     // actual instruction.
204     TII->copyPhysReg(MBB, MBBI, DL, ActualInArg, InArg.getReg(),
205                      InArg.isKill());
206     // Create the actual instruction.
207     unsigned ActualOpc =
208         Opcode == X86::LCMPXCHG8B_SAVE_EBX ? X86::LCMPXCHG8B : X86::LCMPXCHG16B;
209     MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(ActualOpc));
210     // Copy the operands related to the address.
211     for (unsigned Idx = 1; Idx < 6; ++Idx)
212       NewInstr->addOperand(MBBI->getOperand(Idx));
213     // Finally, restore the value of RBX.
214     TII->copyPhysReg(MBB, MBBI, DL, ActualInArg, SaveRbx,
215                      /*SrcIsKill*/ true);
216 
217     // Delete the pseudo.
218     MBBI->eraseFromParent();
219     return true;
220   }
221   }
222   llvm_unreachable("Previous switch has a fallthrough?");
223 }
224 
225 /// Expand all pseudo instructions contained in \p MBB.
226 /// \returns true if any expansion occurred for \p MBB.
227 bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
228   bool Modified = false;
229 
230   // MBBI may be invalidated by the expansion.
231   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
232   while (MBBI != E) {
233     MachineBasicBlock::iterator NMBBI = std::next(MBBI);
234     Modified |= ExpandMI(MBB, MBBI);
235     MBBI = NMBBI;
236   }
237 
238   return Modified;
239 }
240 
241 bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
242   STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
243   TII = STI->getInstrInfo();
244   TRI = STI->getRegisterInfo();
245   X86FL = STI->getFrameLowering();
246 
247   bool Modified = false;
248   for (MachineBasicBlock &MBB : MF)
249     Modified |= ExpandMBB(MBB);
250   return Modified;
251 }
252 
253 /// Returns an instance of the pseudo instruction expansion pass.
254 FunctionPass *llvm::createX86ExpandPseudoPass() {
255   return new X86ExpandPseudo();
256 }
257