1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// This file implements the lowering of LLVM calls to machine code calls for 12 /// GlobalISel. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86CallLowering.h" 17 #include "X86CallingConv.h" 18 #include "X86ISelLowering.h" 19 #include "X86InstrInfo.h" 20 #include "X86RegisterInfo.h" 21 #include "X86Subtarget.h" 22 #include "llvm/ADT/ArrayRef.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/CodeGen/Analysis.h" 25 #include "llvm/CodeGen/CallingConvLower.h" 26 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 27 #include "llvm/CodeGen/GlobalISel/Utils.h" 28 #include "llvm/CodeGen/LowLevelType.h" 29 #include "llvm/CodeGen/MachineBasicBlock.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineFunction.h" 32 #include "llvm/CodeGen/MachineInstrBuilder.h" 33 #include "llvm/CodeGen/MachineMemOperand.h" 34 #include "llvm/CodeGen/MachineOperand.h" 35 #include "llvm/CodeGen/MachineRegisterInfo.h" 36 #include "llvm/CodeGen/MachineValueType.h" 37 #include "llvm/CodeGen/ValueTypes.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/DataLayout.h" 40 #include "llvm/IR/Function.h" 41 #include "llvm/IR/Value.h" 42 #include "llvm/MC/MCRegisterInfo.h" 43 #include "llvm/Support/LowLevelTypeImpl.h" 44 #include "llvm/Target/TargetInstrInfo.h" 45 #include "llvm/Target/TargetSubtargetInfo.h" 46 #include <cassert> 47 #include <cstdint> 48 49 using namespace llvm; 50 51 #include "X86GenCallingConv.inc" 52 53 X86CallLowering::X86CallLowering(const X86TargetLowering &TLI) 54 : CallLowering(&TLI) {} 55 56 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg, 57 SmallVectorImpl<ArgInfo> &SplitArgs, 58 const DataLayout &DL, 59 MachineRegisterInfo &MRI, 60 SplitArgTy PerformArgSplit) const { 61 const X86TargetLowering &TLI = *getTLI<X86TargetLowering>(); 62 LLVMContext &Context = OrigArg.Ty->getContext(); 63 64 SmallVector<EVT, 4> SplitVTs; 65 SmallVector<uint64_t, 4> Offsets; 66 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0); 67 68 if (SplitVTs.size() != 1) { 69 // TODO: support struct/array split 70 return false; 71 } 72 73 EVT VT = SplitVTs[0]; 74 unsigned NumParts = TLI.getNumRegisters(Context, VT); 75 76 if (NumParts == 1) { 77 // replace the original type ( pointer -> GPR ). 78 SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context), 79 OrigArg.Flags, OrigArg.IsFixed); 80 return true; 81 } 82 83 SmallVector<unsigned, 8> SplitRegs; 84 85 EVT PartVT = TLI.getRegisterType(Context, VT); 86 Type *PartTy = PartVT.getTypeForEVT(Context); 87 88 for (unsigned i = 0; i < NumParts; ++i) { 89 ArgInfo Info = 90 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)), 91 PartTy, OrigArg.Flags}; 92 SplitArgs.push_back(Info); 93 SplitRegs.push_back(Info.Reg); 94 } 95 96 PerformArgSplit(SplitRegs); 97 return true; 98 } 99 100 namespace { 101 102 struct OutgoingValueHandler : public CallLowering::ValueHandler { 103 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 104 MachineInstrBuilder &MIB, CCAssignFn *AssignFn) 105 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), 106 DL(MIRBuilder.getMF().getDataLayout()), 107 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {} 108 109 unsigned getStackAddress(uint64_t Size, int64_t Offset, 110 MachinePointerInfo &MPO) override { 111 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0)); 112 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0)); 113 unsigned SPReg = MRI.createGenericVirtualRegister(p0); 114 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister()); 115 116 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType); 117 MIRBuilder.buildConstant(OffsetReg, Offset); 118 119 unsigned AddrReg = MRI.createGenericVirtualRegister(p0); 120 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); 121 122 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); 123 return AddrReg; 124 } 125 126 void assignValueToReg(unsigned ValVReg, unsigned PhysReg, 127 CCValAssign &VA) override { 128 MIB.addUse(PhysReg, RegState::Implicit); 129 unsigned ExtReg = extendRegister(ValVReg, VA); 130 MIRBuilder.buildCopy(PhysReg, ExtReg); 131 } 132 133 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size, 134 MachinePointerInfo &MPO, CCValAssign &VA) override { 135 unsigned ExtReg = extendRegister(ValVReg, VA); 136 auto MMO = MIRBuilder.getMF().getMachineMemOperand( 137 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), 138 /* Alignment */ 0); 139 MIRBuilder.buildStore(ExtReg, Addr, *MMO); 140 } 141 142 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT, 143 CCValAssign::LocInfo LocInfo, 144 const CallLowering::ArgInfo &Info, CCState &State) override { 145 bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State); 146 StackSize = State.getNextStackOffset(); 147 148 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2, 149 X86::XMM3, X86::XMM4, X86::XMM5, 150 X86::XMM6, X86::XMM7}; 151 if (!Info.IsFixed) 152 NumXMMRegs = State.getFirstUnallocated(XMMArgRegs); 153 154 return Res; 155 } 156 157 uint64_t getStackSize() { return StackSize; } 158 uint64_t getNumXmmRegs() { return NumXMMRegs; } 159 160 protected: 161 MachineInstrBuilder &MIB; 162 uint64_t StackSize = 0; 163 const DataLayout &DL; 164 const X86Subtarget &STI; 165 unsigned NumXMMRegs = 0; 166 }; 167 168 } // end anonymous namespace 169 170 bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, 171 const Value *Val, unsigned VReg) const { 172 assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg"); 173 174 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); 175 176 if (VReg) { 177 MachineFunction &MF = MIRBuilder.getMF(); 178 MachineRegisterInfo &MRI = MF.getRegInfo(); 179 auto &DL = MF.getDataLayout(); 180 const Function &F = *MF.getFunction(); 181 182 ArgInfo OrigArg{VReg, Val->getType()}; 183 setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); 184 185 SmallVector<ArgInfo, 8> SplitArgs; 186 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI, 187 [&](ArrayRef<unsigned> Regs) { 188 MIRBuilder.buildUnmerge(Regs, VReg); 189 })) 190 return false; 191 192 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86); 193 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) 194 return false; 195 } 196 197 MIRBuilder.insertInstr(MIB); 198 return true; 199 } 200 201 namespace { 202 203 struct IncomingValueHandler : public CallLowering::ValueHandler { 204 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 205 CCAssignFn *AssignFn) 206 : ValueHandler(MIRBuilder, MRI, AssignFn), 207 DL(MIRBuilder.getMF().getDataLayout()) {} 208 209 unsigned getStackAddress(uint64_t Size, int64_t Offset, 210 MachinePointerInfo &MPO) override { 211 auto &MFI = MIRBuilder.getMF().getFrameInfo(); 212 int FI = MFI.CreateFixedObject(Size, Offset, true); 213 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); 214 215 unsigned AddrReg = MRI.createGenericVirtualRegister( 216 LLT::pointer(0, DL.getPointerSizeInBits(0))); 217 MIRBuilder.buildFrameIndex(AddrReg, FI); 218 return AddrReg; 219 } 220 221 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size, 222 MachinePointerInfo &MPO, CCValAssign &VA) override { 223 auto MMO = MIRBuilder.getMF().getMachineMemOperand( 224 MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size, 225 0); 226 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); 227 } 228 229 protected: 230 const DataLayout &DL; 231 }; 232 233 struct FormalArgHandler : public IncomingValueHandler { 234 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 235 CCAssignFn *AssignFn) 236 : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {} 237 238 void assignValueToReg(unsigned ValVReg, unsigned PhysReg, 239 CCValAssign &VA) override { 240 MIRBuilder.getMBB().addLiveIn(PhysReg); 241 MIRBuilder.buildCopy(ValVReg, PhysReg); 242 } 243 }; 244 245 struct CallReturnHandler : public IncomingValueHandler { 246 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 247 CCAssignFn *AssignFn, MachineInstrBuilder &MIB) 248 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} 249 250 void assignValueToReg(unsigned ValVReg, unsigned PhysReg, 251 CCValAssign &VA) override { 252 MIB.addDef(PhysReg, RegState::Implicit); 253 MIRBuilder.buildCopy(ValVReg, PhysReg); 254 } 255 256 protected: 257 MachineInstrBuilder &MIB; 258 }; 259 260 } // end anonymous namespace 261 262 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, 263 const Function &F, 264 ArrayRef<unsigned> VRegs) const { 265 if (F.arg_empty()) 266 return true; 267 268 // TODO: handle variadic function 269 if (F.isVarArg()) 270 return false; 271 272 MachineFunction &MF = MIRBuilder.getMF(); 273 MachineRegisterInfo &MRI = MF.getRegInfo(); 274 auto DL = MF.getDataLayout(); 275 276 SmallVector<ArgInfo, 8> SplitArgs; 277 unsigned Idx = 0; 278 for (auto &Arg : F.args()) { 279 280 // TODO: handle not simple cases. 281 if (Arg.hasAttribute(Attribute::ByVal) || 282 Arg.hasAttribute(Attribute::InReg) || 283 Arg.hasAttribute(Attribute::StructRet) || 284 Arg.hasAttribute(Attribute::SwiftSelf) || 285 Arg.hasAttribute(Attribute::SwiftError) || 286 Arg.hasAttribute(Attribute::Nest)) 287 return false; 288 289 ArgInfo OrigArg(VRegs[Idx], Arg.getType()); 290 setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F); 291 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI, 292 [&](ArrayRef<unsigned> Regs) { 293 MIRBuilder.buildMerge(VRegs[Idx], Regs); 294 })) 295 return false; 296 Idx++; 297 } 298 299 MachineBasicBlock &MBB = MIRBuilder.getMBB(); 300 if (!MBB.empty()) 301 MIRBuilder.setInstr(*MBB.begin()); 302 303 FormalArgHandler Handler(MIRBuilder, MRI, CC_X86); 304 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) 305 return false; 306 307 // Move back to the end of the basic block. 308 MIRBuilder.setMBB(MBB); 309 310 return true; 311 } 312 313 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, 314 CallingConv::ID CallConv, 315 const MachineOperand &Callee, 316 const ArgInfo &OrigRet, 317 ArrayRef<ArgInfo> OrigArgs) const { 318 MachineFunction &MF = MIRBuilder.getMF(); 319 const Function &F = *MF.getFunction(); 320 MachineRegisterInfo &MRI = MF.getRegInfo(); 321 auto &DL = F.getParent()->getDataLayout(); 322 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>(); 323 const TargetInstrInfo &TII = *STI.getInstrInfo(); 324 auto TRI = STI.getRegisterInfo(); 325 326 // Handle only Linux C, X86_64_SysV calling conventions for now. 327 if (!STI.isTargetLinux() || 328 !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV)) 329 return false; 330 331 unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); 332 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); 333 334 // Create a temporarily-floating call instruction so we can add the implicit 335 // uses of arg registers. 336 bool Is64Bit = STI.is64Bit(); 337 unsigned CallOpc = Callee.isReg() 338 ? (Is64Bit ? X86::CALL64r : X86::CALL32r) 339 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32); 340 341 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask( 342 TRI->getCallPreservedMask(MF, CallConv)); 343 344 SmallVector<ArgInfo, 8> SplitArgs; 345 for (const auto &OrigArg : OrigArgs) { 346 347 // TODO: handle not simple cases. 348 if (OrigArg.Flags.isByVal()) 349 return false; 350 351 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI, 352 [&](ArrayRef<unsigned> Regs) { 353 MIRBuilder.buildUnmerge(Regs, OrigArg.Reg); 354 })) 355 return false; 356 } 357 // Do the actual argument marshalling. 358 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86); 359 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) 360 return false; 361 362 bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed; 363 if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) { 364 // From AMD64 ABI document: 365 // For calls that may call functions that use varargs or stdargs 366 // (prototype-less calls or calls to functions containing ellipsis (...) in 367 // the declaration) %al is used as hidden argument to specify the number 368 // of SSE registers used. The contents of %al do not need to match exactly 369 // the number of registers, but must be an ubound on the number of SSE 370 // registers used and is in the range 0 - 8 inclusive. 371 372 MIRBuilder.buildInstr(X86::MOV8ri) 373 .addDef(X86::AL) 374 .addImm(Handler.getNumXmmRegs()); 375 MIB.addUse(X86::AL, RegState::Implicit); 376 } 377 378 // Now we can add the actual call instruction to the correct basic block. 379 MIRBuilder.insertInstr(MIB); 380 381 // If Callee is a reg, since it is used by a target specific 382 // instruction, it must have a register class matching the 383 // constraint of that instruction. 384 if (Callee.isReg()) 385 MIB->getOperand(0).setReg(constrainOperandRegClass( 386 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), 387 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), 388 Callee.getReg(), 0)); 389 390 // Finally we can copy the returned value back into its virtual-register. In 391 // symmetry with the arguments, the physical register must be an 392 // implicit-define of the call instruction. 393 394 if (OrigRet.Reg) { 395 SplitArgs.clear(); 396 SmallVector<unsigned, 8> NewRegs; 397 398 if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI, 399 [&](ArrayRef<unsigned> Regs) { 400 NewRegs.assign(Regs.begin(), Regs.end()); 401 })) 402 return false; 403 404 CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB); 405 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) 406 return false; 407 408 if (!NewRegs.empty()) 409 MIRBuilder.buildMerge(OrigRet.Reg, NewRegs); 410 } 411 412 CallSeqStart.addImm(Handler.getStackSize()) 413 .addImm(0 /* see getFrameTotalSize */) 414 .addImm(0 /* see getFrameAdjustment */); 415 416 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); 417 MIRBuilder.buildInstr(AdjStackUp) 418 .addImm(Handler.getStackSize()) 419 .addImm(0 /* NumBytesForCalleeToPop */); 420 421 return true; 422 } 423