1 //===- X86AvoidStoreForwardingBlockis.cpp - Avoid HW Store Forward Block --===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // If a load follows a store and reloads data that the store has written to 10 // memory, Intel microarchitectures can in many cases forward the data directly 11 // from the store to the load, This "store forwarding" saves cycles by enabling 12 // the load to directly obtain the data instead of accessing the data from 13 // cache or memory. 14 // A "store forward block" occurs in cases that a store cannot be forwarded to 15 // the load. The most typical case of store forward block on Intel Core 16 // microarchitecture that a small store cannot be forwarded to a large load. 17 // The estimated penalty for a store forward block is ~13 cycles. 18 // 19 // This pass tries to recognize and handle cases where "store forward block" 20 // is created by the compiler when lowering memcpy calls to a sequence 21 // of a load and a store. 22 // 23 // The pass currently only handles cases where memcpy is lowered to 24 // XMM/YMM registers, it tries to break the memcpy into smaller copies. 25 // breaking the memcpy should be possible since there is no atomicity 26 // guarantee for loads and stores to XMM/YMM. 27 // 28 // It could be better for performance to solve the problem by loading 29 // to XMM/YMM then inserting the partial store before storing back from XMM/YMM 30 // to memory, but this will result in a more conservative optimization since it 31 // requires we prove that all memory accesses between the blocking store and the 32 // load must alias/don't alias before we can move the store, whereas the 33 // transformation done here is correct regardless to other memory accesses. 34 //===----------------------------------------------------------------------===// 35 36 #include "X86InstrInfo.h" 37 #include "X86Subtarget.h" 38 #include "llvm/CodeGen/MachineBasicBlock.h" 39 #include "llvm/CodeGen/MachineFunction.h" 40 #include "llvm/CodeGen/MachineFunctionPass.h" 41 #include "llvm/CodeGen/MachineInstr.h" 42 #include "llvm/CodeGen/MachineInstrBuilder.h" 43 #include "llvm/CodeGen/MachineOperand.h" 44 #include "llvm/CodeGen/MachineRegisterInfo.h" 45 #include "llvm/IR/DebugInfoMetadata.h" 46 #include "llvm/IR/DebugLoc.h" 47 #include "llvm/IR/Function.h" 48 #include "llvm/MC/MCInstrDesc.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86-avoid-SFB" 53 54 static cl::opt<bool> DisableX86AvoidStoreForwardBlocks( 55 "x86-disable-avoid-SFB", cl::Hidden, 56 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false)); 57 58 static cl::opt<unsigned> X86AvoidSFBInspectionLimit( 59 "x86-sfb-inspection-limit", 60 cl::desc("X86: Number of instructions backward to " 61 "inspect for store forwarding blocks."), 62 cl::init(20), cl::Hidden); 63 64 namespace { 65 66 using DisplacementSizeMap = std::map<int64_t, unsigned>; 67 68 class X86AvoidSFBPass : public MachineFunctionPass { 69 public: 70 static char ID; 71 X86AvoidSFBPass() : MachineFunctionPass(ID) { 72 initializeX86AvoidSFBPassPass(*PassRegistry::getPassRegistry()); 73 } 74 75 StringRef getPassName() const override { 76 return "X86 Avoid Store Forwarding Blocks"; 77 } 78 79 bool runOnMachineFunction(MachineFunction &MF) override; 80 81 void getAnalysisUsage(AnalysisUsage &AU) const override { 82 MachineFunctionPass::getAnalysisUsage(AU); 83 AU.addRequired<AAResultsWrapperPass>(); 84 } 85 86 private: 87 MachineRegisterInfo *MRI; 88 const X86InstrInfo *TII; 89 const X86RegisterInfo *TRI; 90 SmallVector<std::pair<MachineInstr *, MachineInstr *>, 2> 91 BlockedLoadsStoresPairs; 92 SmallVector<MachineInstr *, 2> ForRemoval; 93 AliasAnalysis *AA; 94 95 /// Returns couples of Load then Store to memory which look 96 /// like a memcpy. 97 void findPotentiallylBlockedCopies(MachineFunction &MF); 98 /// Break the memcpy's load and store into smaller copies 99 /// such that each memory load that was blocked by a smaller store 100 /// would now be copied separately. 101 void breakBlockedCopies(MachineInstr *LoadInst, MachineInstr *StoreInst, 102 const DisplacementSizeMap &BlockingStoresDispSizeMap); 103 /// Break a copy of size Size to smaller copies. 104 void buildCopies(int Size, MachineInstr *LoadInst, int64_t LdDispImm, 105 MachineInstr *StoreInst, int64_t StDispImm, 106 int64_t LMMOffset, int64_t SMMOffset); 107 108 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp, 109 MachineInstr *StoreInst, unsigned NStoreOpcode, 110 int64_t StoreDisp, unsigned Size, int64_t LMMOffset, 111 int64_t SMMOffset); 112 113 bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const; 114 115 unsigned getRegSizeInBytes(MachineInstr *Inst); 116 }; 117 118 } // end anonymous namespace 119 120 char X86AvoidSFBPass::ID = 0; 121 122 INITIALIZE_PASS_BEGIN(X86AvoidSFBPass, DEBUG_TYPE, "Machine code sinking", 123 false, false) 124 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) 125 INITIALIZE_PASS_END(X86AvoidSFBPass, DEBUG_TYPE, "Machine code sinking", false, 126 false) 127 128 FunctionPass *llvm::createX86AvoidStoreForwardingBlocks() { 129 return new X86AvoidSFBPass(); 130 } 131 132 static bool isXMMLoadOpcode(unsigned Opcode) { 133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || 134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || 135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || 136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || 137 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || 138 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || 139 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || 140 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; 141 } 142 static bool isYMMLoadOpcode(unsigned Opcode) { 143 return Opcode == X86::VMOVUPSYrm || Opcode == X86::VMOVAPSYrm || 144 Opcode == X86::VMOVUPDYrm || Opcode == X86::VMOVAPDYrm || 145 Opcode == X86::VMOVDQUYrm || Opcode == X86::VMOVDQAYrm || 146 Opcode == X86::VMOVUPSZ256rm || Opcode == X86::VMOVAPSZ256rm || 147 Opcode == X86::VMOVUPDZ256rm || Opcode == X86::VMOVAPDZ256rm || 148 Opcode == X86::VMOVDQU64Z256rm || Opcode == X86::VMOVDQA64Z256rm || 149 Opcode == X86::VMOVDQU32Z256rm || Opcode == X86::VMOVDQA32Z256rm; 150 } 151 152 static bool isPotentialBlockedMemCpyLd(unsigned Opcode) { 153 return isXMMLoadOpcode(Opcode) || isYMMLoadOpcode(Opcode); 154 } 155 156 static bool isPotentialBlockedMemCpyPair(int LdOpcode, int StOpcode) { 157 switch (LdOpcode) { 158 case X86::MOVUPSrm: 159 case X86::MOVAPSrm: 160 return StOpcode == X86::MOVUPSmr || StOpcode == X86::MOVAPSmr; 161 case X86::VMOVUPSrm: 162 case X86::VMOVAPSrm: 163 return StOpcode == X86::VMOVUPSmr || StOpcode == X86::VMOVAPSmr; 164 case X86::VMOVUPDrm: 165 case X86::VMOVAPDrm: 166 return StOpcode == X86::VMOVUPDmr || StOpcode == X86::VMOVAPDmr; 167 case X86::VMOVDQUrm: 168 case X86::VMOVDQArm: 169 return StOpcode == X86::VMOVDQUmr || StOpcode == X86::VMOVDQAmr; 170 case X86::VMOVUPSZ128rm: 171 case X86::VMOVAPSZ128rm: 172 return StOpcode == X86::VMOVUPSZ128mr || StOpcode == X86::VMOVAPSZ128mr; 173 case X86::VMOVUPDZ128rm: 174 case X86::VMOVAPDZ128rm: 175 return StOpcode == X86::VMOVUPDZ128mr || StOpcode == X86::VMOVAPDZ128mr; 176 case X86::VMOVUPSYrm: 177 case X86::VMOVAPSYrm: 178 return StOpcode == X86::VMOVUPSYmr || StOpcode == X86::VMOVAPSYmr; 179 case X86::VMOVUPDYrm: 180 case X86::VMOVAPDYrm: 181 return StOpcode == X86::VMOVUPDYmr || StOpcode == X86::VMOVAPDYmr; 182 case X86::VMOVDQUYrm: 183 case X86::VMOVDQAYrm: 184 return StOpcode == X86::VMOVDQUYmr || StOpcode == X86::VMOVDQAYmr; 185 case X86::VMOVUPSZ256rm: 186 case X86::VMOVAPSZ256rm: 187 return StOpcode == X86::VMOVUPSZ256mr || StOpcode == X86::VMOVAPSZ256mr; 188 case X86::VMOVUPDZ256rm: 189 case X86::VMOVAPDZ256rm: 190 return StOpcode == X86::VMOVUPDZ256mr || StOpcode == X86::VMOVAPDZ256mr; 191 case X86::VMOVDQU64Z128rm: 192 case X86::VMOVDQA64Z128rm: 193 return StOpcode == X86::VMOVDQU64Z128mr || StOpcode == X86::VMOVDQA64Z128mr; 194 case X86::VMOVDQU32Z128rm: 195 case X86::VMOVDQA32Z128rm: 196 return StOpcode == X86::VMOVDQU32Z128mr || StOpcode == X86::VMOVDQA32Z128mr; 197 case X86::VMOVDQU64Z256rm: 198 case X86::VMOVDQA64Z256rm: 199 return StOpcode == X86::VMOVDQU64Z256mr || StOpcode == X86::VMOVDQA64Z256mr; 200 case X86::VMOVDQU32Z256rm: 201 case X86::VMOVDQA32Z256rm: 202 return StOpcode == X86::VMOVDQU32Z256mr || StOpcode == X86::VMOVDQA32Z256mr; 203 default: 204 return false; 205 } 206 } 207 208 static bool isPotentialBlockingStoreInst(int Opcode, int LoadOpcode) { 209 bool PBlock = false; 210 PBlock |= Opcode == X86::MOV64mr || Opcode == X86::MOV64mi32 || 211 Opcode == X86::MOV32mr || Opcode == X86::MOV32mi || 212 Opcode == X86::MOV16mr || Opcode == X86::MOV16mi || 213 Opcode == X86::MOV8mr || Opcode == X86::MOV8mi; 214 if (isYMMLoadOpcode(LoadOpcode)) 215 PBlock |= Opcode == X86::VMOVUPSmr || Opcode == X86::VMOVAPSmr || 216 Opcode == X86::VMOVUPDmr || Opcode == X86::VMOVAPDmr || 217 Opcode == X86::VMOVDQUmr || Opcode == X86::VMOVDQAmr || 218 Opcode == X86::VMOVUPSZ128mr || Opcode == X86::VMOVAPSZ128mr || 219 Opcode == X86::VMOVUPDZ128mr || Opcode == X86::VMOVAPDZ128mr || 220 Opcode == X86::VMOVDQU64Z128mr || 221 Opcode == X86::VMOVDQA64Z128mr || 222 Opcode == X86::VMOVDQU32Z128mr || Opcode == X86::VMOVDQA32Z128mr; 223 return PBlock; 224 } 225 226 static const int MOV128SZ = 16; 227 static const int MOV64SZ = 8; 228 static const int MOV32SZ = 4; 229 static const int MOV16SZ = 2; 230 static const int MOV8SZ = 1; 231 232 static unsigned getYMMtoXMMLoadOpcode(unsigned LoadOpcode) { 233 switch (LoadOpcode) { 234 case X86::VMOVUPSYrm: 235 case X86::VMOVAPSYrm: 236 return X86::VMOVUPSrm; 237 case X86::VMOVUPDYrm: 238 case X86::VMOVAPDYrm: 239 return X86::VMOVUPDrm; 240 case X86::VMOVDQUYrm: 241 case X86::VMOVDQAYrm: 242 return X86::VMOVDQUrm; 243 case X86::VMOVUPSZ256rm: 244 case X86::VMOVAPSZ256rm: 245 return X86::VMOVUPSZ128rm; 246 case X86::VMOVUPDZ256rm: 247 case X86::VMOVAPDZ256rm: 248 return X86::VMOVUPDZ128rm; 249 case X86::VMOVDQU64Z256rm: 250 case X86::VMOVDQA64Z256rm: 251 return X86::VMOVDQU64Z128rm; 252 case X86::VMOVDQU32Z256rm: 253 case X86::VMOVDQA32Z256rm: 254 return X86::VMOVDQU32Z128rm; 255 default: 256 llvm_unreachable("Unexpected Load Instruction Opcode"); 257 } 258 return 0; 259 } 260 261 static unsigned getYMMtoXMMStoreOpcode(unsigned StoreOpcode) { 262 switch (StoreOpcode) { 263 case X86::VMOVUPSYmr: 264 case X86::VMOVAPSYmr: 265 return X86::VMOVUPSmr; 266 case X86::VMOVUPDYmr: 267 case X86::VMOVAPDYmr: 268 return X86::VMOVUPDmr; 269 case X86::VMOVDQUYmr: 270 case X86::VMOVDQAYmr: 271 return X86::VMOVDQUmr; 272 case X86::VMOVUPSZ256mr: 273 case X86::VMOVAPSZ256mr: 274 return X86::VMOVUPSZ128mr; 275 case X86::VMOVUPDZ256mr: 276 case X86::VMOVAPDZ256mr: 277 return X86::VMOVUPDZ128mr; 278 case X86::VMOVDQU64Z256mr: 279 case X86::VMOVDQA64Z256mr: 280 return X86::VMOVDQU64Z128mr; 281 case X86::VMOVDQU32Z256mr: 282 case X86::VMOVDQA32Z256mr: 283 return X86::VMOVDQU32Z128mr; 284 default: 285 llvm_unreachable("Unexpected Load Instruction Opcode"); 286 } 287 return 0; 288 } 289 290 static int getAddrOffset(MachineInstr *MI) { 291 const MCInstrDesc &Descl = MI->getDesc(); 292 int AddrOffset = X86II::getMemoryOperandNo(Descl.TSFlags); 293 assert(AddrOffset != -1 && "Expected Memory Operand"); 294 AddrOffset += X86II::getOperandBias(Descl); 295 return AddrOffset; 296 } 297 298 static MachineOperand &getBaseOperand(MachineInstr *MI) { 299 int AddrOffset = getAddrOffset(MI); 300 return MI->getOperand(AddrOffset + X86::AddrBaseReg); 301 } 302 303 static MachineOperand &getDispOperand(MachineInstr *MI) { 304 int AddrOffset = getAddrOffset(MI); 305 return MI->getOperand(AddrOffset + X86::AddrDisp); 306 } 307 308 // Relevant addressing modes contain only base register and immediate 309 // displacement or frameindex and immediate displacement. 310 // TODO: Consider expanding to other addressing modes in the future 311 static bool isRelevantAddressingMode(MachineInstr *MI) { 312 int AddrOffset = getAddrOffset(MI); 313 MachineOperand &Base = getBaseOperand(MI); 314 MachineOperand &Disp = getDispOperand(MI); 315 MachineOperand &Scale = MI->getOperand(AddrOffset + X86::AddrScaleAmt); 316 MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg); 317 MachineOperand &Segment = MI->getOperand(AddrOffset + X86::AddrSegmentReg); 318 319 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI())) 320 return false; 321 if (!Disp.isImm()) 322 return false; 323 if (Scale.getImm() != 1) 324 return false; 325 if (!(Index.isReg() && Index.getReg() == X86::NoRegister)) 326 return false; 327 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister)) 328 return false; 329 return true; 330 } 331 332 // Collect potentially blocking stores. 333 // Limit the number of instructions backwards we want to inspect 334 // since the effect of store block won't be visible if the store 335 // and load instructions have enough instructions in between to 336 // keep the core busy. 337 static SmallVector<MachineInstr *, 2> 338 findPotentialBlockers(MachineInstr *LoadInst) { 339 SmallVector<MachineInstr *, 2> PotentialBlockers; 340 unsigned BlockCount = 0; 341 const unsigned InspectionLimit = X86AvoidSFBInspectionLimit; 342 for (auto PBInst = std::next(MachineBasicBlock::reverse_iterator(LoadInst)), 343 E = LoadInst->getParent()->rend(); 344 PBInst != E; ++PBInst) { 345 BlockCount++; 346 if (BlockCount >= InspectionLimit) 347 break; 348 MachineInstr &MI = *PBInst; 349 if (MI.getDesc().isCall()) 350 return PotentialBlockers; 351 PotentialBlockers.push_back(&MI); 352 } 353 // If we didn't get to the instructions limit try predecessing blocks. 354 // Ideally we should traverse the predecessor blocks in depth with some 355 // coloring algorithm, but for now let's just look at the first order 356 // predecessors. 357 if (BlockCount < InspectionLimit) { 358 MachineBasicBlock *MBB = LoadInst->getParent(); 359 int LimitLeft = InspectionLimit - BlockCount; 360 for (MachineBasicBlock::pred_iterator PB = MBB->pred_begin(), 361 PE = MBB->pred_end(); 362 PB != PE; ++PB) { 363 MachineBasicBlock *PMBB = *PB; 364 int PredCount = 0; 365 for (MachineBasicBlock::reverse_iterator PBInst = PMBB->rbegin(), 366 PME = PMBB->rend(); 367 PBInst != PME; ++PBInst) { 368 PredCount++; 369 if (PredCount >= LimitLeft) 370 break; 371 if (PBInst->getDesc().isCall()) 372 break; 373 PotentialBlockers.push_back(&*PBInst); 374 } 375 } 376 } 377 return PotentialBlockers; 378 } 379 380 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, 381 int64_t LoadDisp, MachineInstr *StoreInst, 382 unsigned NStoreOpcode, int64_t StoreDisp, 383 unsigned Size, int64_t LMMOffset, 384 int64_t SMMOffset) { 385 MachineOperand &LoadBase = getBaseOperand(LoadInst); 386 MachineOperand &StoreBase = getBaseOperand(StoreInst); 387 MachineBasicBlock *MBB = LoadInst->getParent(); 388 MachineMemOperand *LMMO = *LoadInst->memoperands_begin(); 389 MachineMemOperand *SMMO = *StoreInst->memoperands_begin(); 390 391 unsigned Reg1 = MRI->createVirtualRegister( 392 TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent()))); 393 MachineInstr *NewLoad = 394 BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode), 395 Reg1) 396 .add(LoadBase) 397 .addImm(1) 398 .addReg(X86::NoRegister) 399 .addImm(LoadDisp) 400 .addReg(X86::NoRegister) 401 .addMemOperand( 402 MBB->getParent()->getMachineMemOperand(LMMO, LMMOffset, Size)); 403 if (LoadBase.isReg()) 404 getBaseOperand(NewLoad).setIsKill(false); 405 LLVM_DEBUG(NewLoad->dump()); 406 // If the load and store are consecutive, use the loadInst location to 407 // reduce register pressure. 408 MachineInstr *StInst = StoreInst; 409 auto PrevInstrIt = skipDebugInstructionsBackward( 410 std::prev(MachineBasicBlock::instr_iterator(StoreInst)), 411 MBB->instr_begin()); 412 if (PrevInstrIt.getNodePtr() == LoadInst) 413 StInst = LoadInst; 414 MachineInstr *NewStore = 415 BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode)) 416 .add(StoreBase) 417 .addImm(1) 418 .addReg(X86::NoRegister) 419 .addImm(StoreDisp) 420 .addReg(X86::NoRegister) 421 .addReg(Reg1) 422 .addMemOperand( 423 MBB->getParent()->getMachineMemOperand(SMMO, SMMOffset, Size)); 424 if (StoreBase.isReg()) 425 getBaseOperand(NewStore).setIsKill(false); 426 MachineOperand &StoreSrcVReg = StoreInst->getOperand(X86::AddrNumOperands); 427 assert(StoreSrcVReg.isReg() && "Expected virtual register"); 428 NewStore->getOperand(X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill()); 429 LLVM_DEBUG(NewStore->dump()); 430 } 431 432 void X86AvoidSFBPass::buildCopies(int Size, MachineInstr *LoadInst, 433 int64_t LdDispImm, MachineInstr *StoreInst, 434 int64_t StDispImm, int64_t LMMOffset, 435 int64_t SMMOffset) { 436 int LdDisp = LdDispImm; 437 int StDisp = StDispImm; 438 while (Size > 0) { 439 if ((Size - MOV128SZ >= 0) && isYMMLoadOpcode(LoadInst->getOpcode())) { 440 Size = Size - MOV128SZ; 441 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, 442 StoreInst, getYMMtoXMMStoreOpcode(StoreInst->getOpcode()), 443 StDisp, MOV128SZ, LMMOffset, SMMOffset); 444 LdDisp += MOV128SZ; 445 StDisp += MOV128SZ; 446 LMMOffset += MOV128SZ; 447 SMMOffset += MOV128SZ; 448 continue; 449 } 450 if (Size - MOV64SZ >= 0) { 451 Size = Size - MOV64SZ; 452 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, 453 MOV64SZ, LMMOffset, SMMOffset); 454 LdDisp += MOV64SZ; 455 StDisp += MOV64SZ; 456 LMMOffset += MOV64SZ; 457 SMMOffset += MOV64SZ; 458 continue; 459 } 460 if (Size - MOV32SZ >= 0) { 461 Size = Size - MOV32SZ; 462 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, 463 MOV32SZ, LMMOffset, SMMOffset); 464 LdDisp += MOV32SZ; 465 StDisp += MOV32SZ; 466 LMMOffset += MOV32SZ; 467 SMMOffset += MOV32SZ; 468 continue; 469 } 470 if (Size - MOV16SZ >= 0) { 471 Size = Size - MOV16SZ; 472 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, 473 MOV16SZ, LMMOffset, SMMOffset); 474 LdDisp += MOV16SZ; 475 StDisp += MOV16SZ; 476 LMMOffset += MOV16SZ; 477 SMMOffset += MOV16SZ; 478 continue; 479 } 480 if (Size - MOV8SZ >= 0) { 481 Size = Size - MOV8SZ; 482 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, 483 MOV8SZ, LMMOffset, SMMOffset); 484 LdDisp += MOV8SZ; 485 StDisp += MOV8SZ; 486 LMMOffset += MOV8SZ; 487 SMMOffset += MOV8SZ; 488 continue; 489 } 490 } 491 assert(Size == 0 && "Wrong size division"); 492 } 493 494 static void updateKillStatus(MachineInstr *LoadInst, MachineInstr *StoreInst) { 495 MachineOperand &LoadBase = getBaseOperand(LoadInst); 496 MachineOperand &StoreBase = getBaseOperand(StoreInst); 497 auto StorePrevNonDbgInstr = skipDebugInstructionsBackward( 498 std::prev(MachineBasicBlock::instr_iterator(StoreInst)), 499 LoadInst->getParent()->instr_begin()).getNodePtr(); 500 if (LoadBase.isReg()) { 501 MachineInstr *LastLoad = LoadInst->getPrevNode(); 502 // If the original load and store to xmm/ymm were consecutive 503 // then the partial copies were also created in 504 // a consecutive order to reduce register pressure, 505 // and the location of the last load is before the last store. 506 if (StorePrevNonDbgInstr == LoadInst) 507 LastLoad = LoadInst->getPrevNode()->getPrevNode(); 508 getBaseOperand(LastLoad).setIsKill(LoadBase.isKill()); 509 } 510 if (StoreBase.isReg()) { 511 MachineInstr *StInst = StoreInst; 512 if (StorePrevNonDbgInstr == LoadInst) 513 StInst = LoadInst; 514 getBaseOperand(StInst->getPrevNode()).setIsKill(StoreBase.isKill()); 515 } 516 } 517 518 bool X86AvoidSFBPass::alias(const MachineMemOperand &Op1, 519 const MachineMemOperand &Op2) const { 520 if (!Op1.getValue() || !Op2.getValue()) 521 return true; 522 523 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); 524 int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset; 525 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; 526 527 AliasResult AAResult = 528 AA->alias(MemoryLocation(Op1.getValue(), Overlapa, Op1.getAAInfo()), 529 MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo())); 530 return AAResult != NoAlias; 531 } 532 533 void X86AvoidSFBPass::findPotentiallylBlockedCopies(MachineFunction &MF) { 534 for (auto &MBB : MF) 535 for (auto &MI : MBB) { 536 if (!isPotentialBlockedMemCpyLd(MI.getOpcode())) 537 continue; 538 int DefVR = MI.getOperand(0).getReg(); 539 if (!MRI->hasOneNonDBGUse(DefVR)) 540 continue; 541 for (auto UI = MRI->use_nodbg_begin(DefVR), UE = MRI->use_nodbg_end(); 542 UI != UE;) { 543 MachineOperand &StoreMO = *UI++; 544 MachineInstr &StoreMI = *StoreMO.getParent(); 545 // Skip cases where the memcpy may overlap. 546 if (StoreMI.getParent() == MI.getParent() && 547 isPotentialBlockedMemCpyPair(MI.getOpcode(), StoreMI.getOpcode()) && 548 isRelevantAddressingMode(&MI) && 549 isRelevantAddressingMode(&StoreMI)) { 550 assert(MI.hasOneMemOperand() && 551 "Expected one memory operand for load instruction"); 552 assert(StoreMI.hasOneMemOperand() && 553 "Expected one memory operand for store instruction"); 554 if (!alias(**MI.memoperands_begin(), **StoreMI.memoperands_begin())) 555 BlockedLoadsStoresPairs.push_back(std::make_pair(&MI, &StoreMI)); 556 } 557 } 558 } 559 } 560 561 unsigned X86AvoidSFBPass::getRegSizeInBytes(MachineInstr *LoadInst) { 562 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, 563 *LoadInst->getParent()->getParent()); 564 return TRI->getRegSizeInBits(*TRC) / 8; 565 } 566 567 void X86AvoidSFBPass::breakBlockedCopies( 568 MachineInstr *LoadInst, MachineInstr *StoreInst, 569 const DisplacementSizeMap &BlockingStoresDispSizeMap) { 570 int64_t LdDispImm = getDispOperand(LoadInst).getImm(); 571 int64_t StDispImm = getDispOperand(StoreInst).getImm(); 572 int64_t LMMOffset = 0; 573 int64_t SMMOffset = 0; 574 575 int64_t LdDisp1 = LdDispImm; 576 int64_t LdDisp2 = 0; 577 int64_t StDisp1 = StDispImm; 578 int64_t StDisp2 = 0; 579 unsigned Size1 = 0; 580 unsigned Size2 = 0; 581 int64_t LdStDelta = StDispImm - LdDispImm; 582 583 for (auto DispSizePair : BlockingStoresDispSizeMap) { 584 LdDisp2 = DispSizePair.first; 585 StDisp2 = DispSizePair.first + LdStDelta; 586 Size2 = DispSizePair.second; 587 // Avoid copying overlapping areas. 588 if (LdDisp2 < LdDisp1) { 589 int OverlapDelta = LdDisp1 - LdDisp2; 590 LdDisp2 += OverlapDelta; 591 StDisp2 += OverlapDelta; 592 Size2 -= OverlapDelta; 593 } 594 Size1 = LdDisp2 - LdDisp1; 595 596 // Build a copy for the point until the current blocking store's 597 // displacement. 598 buildCopies(Size1, LoadInst, LdDisp1, StoreInst, StDisp1, LMMOffset, 599 SMMOffset); 600 // Build a copy for the current blocking store. 601 buildCopies(Size2, LoadInst, LdDisp2, StoreInst, StDisp2, LMMOffset + Size1, 602 SMMOffset + Size1); 603 LdDisp1 = LdDisp2 + Size2; 604 StDisp1 = StDisp2 + Size2; 605 LMMOffset += Size1 + Size2; 606 SMMOffset += Size1 + Size2; 607 } 608 unsigned Size3 = (LdDispImm + getRegSizeInBytes(LoadInst)) - LdDisp1; 609 buildCopies(Size3, LoadInst, LdDisp1, StoreInst, StDisp1, LMMOffset, 610 LMMOffset); 611 } 612 613 static bool hasSameBaseOpValue(MachineInstr *LoadInst, 614 MachineInstr *StoreInst) { 615 MachineOperand &LoadBase = getBaseOperand(LoadInst); 616 MachineOperand &StoreBase = getBaseOperand(StoreInst); 617 if (LoadBase.isReg() != StoreBase.isReg()) 618 return false; 619 if (LoadBase.isReg()) 620 return LoadBase.getReg() == StoreBase.getReg(); 621 return LoadBase.getIndex() == StoreBase.getIndex(); 622 } 623 624 static bool isBlockingStore(int64_t LoadDispImm, unsigned LoadSize, 625 int64_t StoreDispImm, unsigned StoreSize) { 626 return ((StoreDispImm >= LoadDispImm) && 627 (StoreDispImm <= LoadDispImm + (LoadSize - StoreSize))); 628 } 629 630 // Keep track of all stores blocking a load 631 static void 632 updateBlockingStoresDispSizeMap(DisplacementSizeMap &BlockingStoresDispSizeMap, 633 int64_t DispImm, unsigned Size) { 634 if (BlockingStoresDispSizeMap.count(DispImm)) { 635 // Choose the smallest blocking store starting at this displacement. 636 if (BlockingStoresDispSizeMap[DispImm] > Size) 637 BlockingStoresDispSizeMap[DispImm] = Size; 638 639 } else 640 BlockingStoresDispSizeMap[DispImm] = Size; 641 } 642 643 // Remove blocking stores contained in each other. 644 static void 645 removeRedundantBlockingStores(DisplacementSizeMap &BlockingStoresDispSizeMap) { 646 if (BlockingStoresDispSizeMap.size() <= 1) 647 return; 648 649 SmallVector<std::pair<int64_t, unsigned>, 0> DispSizeStack; 650 for (auto DispSizePair : BlockingStoresDispSizeMap) { 651 int64_t CurrDisp = DispSizePair.first; 652 unsigned CurrSize = DispSizePair.second; 653 while (DispSizeStack.size()) { 654 int64_t PrevDisp = DispSizeStack.back().first; 655 unsigned PrevSize = DispSizeStack.back().second; 656 if (CurrDisp + CurrSize > PrevDisp + PrevSize) 657 break; 658 DispSizeStack.pop_back(); 659 } 660 DispSizeStack.push_back(DispSizePair); 661 } 662 BlockingStoresDispSizeMap.clear(); 663 for (auto Disp : DispSizeStack) 664 BlockingStoresDispSizeMap.insert(Disp); 665 } 666 667 bool X86AvoidSFBPass::runOnMachineFunction(MachineFunction &MF) { 668 bool Changed = false; 669 670 if (DisableX86AvoidStoreForwardBlocks || skipFunction(MF.getFunction()) || 671 !MF.getSubtarget<X86Subtarget>().is64Bit()) 672 return false; 673 674 MRI = &MF.getRegInfo(); 675 assert(MRI->isSSA() && "Expected MIR to be in SSA form"); 676 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); 677 TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo(); 678 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); 679 LLVM_DEBUG(dbgs() << "Start X86AvoidStoreForwardBlocks\n";); 680 // Look for a load then a store to XMM/YMM which look like a memcpy 681 findPotentiallylBlockedCopies(MF); 682 683 for (auto LoadStoreInstPair : BlockedLoadsStoresPairs) { 684 MachineInstr *LoadInst = LoadStoreInstPair.first; 685 int64_t LdDispImm = getDispOperand(LoadInst).getImm(); 686 DisplacementSizeMap BlockingStoresDispSizeMap; 687 688 SmallVector<MachineInstr *, 2> PotentialBlockers = 689 findPotentialBlockers(LoadInst); 690 for (auto PBInst : PotentialBlockers) { 691 if (!isPotentialBlockingStoreInst(PBInst->getOpcode(), 692 LoadInst->getOpcode()) || 693 !isRelevantAddressingMode(PBInst)) 694 continue; 695 int64_t PBstDispImm = getDispOperand(PBInst).getImm(); 696 assert(PBInst->hasOneMemOperand() && "Expected One Memory Operand"); 697 unsigned PBstSize = (*PBInst->memoperands_begin())->getSize(); 698 // This check doesn't cover all cases, but it will suffice for now. 699 // TODO: take branch probability into consideration, if the blocking 700 // store is in an unreached block, breaking the memcopy could lose 701 // performance. 702 if (hasSameBaseOpValue(LoadInst, PBInst) && 703 isBlockingStore(LdDispImm, getRegSizeInBytes(LoadInst), PBstDispImm, 704 PBstSize)) 705 updateBlockingStoresDispSizeMap(BlockingStoresDispSizeMap, PBstDispImm, 706 PBstSize); 707 } 708 709 if (BlockingStoresDispSizeMap.empty()) 710 continue; 711 712 // We found a store forward block, break the memcpy's load and store 713 // into smaller copies such that each smaller store that was causing 714 // a store block would now be copied separately. 715 MachineInstr *StoreInst = LoadStoreInstPair.second; 716 LLVM_DEBUG(dbgs() << "Blocked load and store instructions: \n"); 717 LLVM_DEBUG(LoadInst->dump()); 718 LLVM_DEBUG(StoreInst->dump()); 719 LLVM_DEBUG(dbgs() << "Replaced with:\n"); 720 removeRedundantBlockingStores(BlockingStoresDispSizeMap); 721 breakBlockedCopies(LoadInst, StoreInst, BlockingStoresDispSizeMap); 722 updateKillStatus(LoadInst, StoreInst); 723 ForRemoval.push_back(LoadInst); 724 ForRemoval.push_back(StoreInst); 725 } 726 for (auto RemovedInst : ForRemoval) { 727 RemovedInst->eraseFromParent(); 728 } 729 ForRemoval.clear(); 730 BlockedLoadsStoresPairs.clear(); 731 LLVM_DEBUG(dbgs() << "End X86AvoidStoreForwardBlocks\n";); 732 733 return Changed; 734 } 735