1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86MCTargetDesc.h" 14 #include "TargetInfo/X86TargetInfo.h" 15 #include "X86ATTInstPrinter.h" 16 #include "X86BaseInfo.h" 17 #include "X86IntelInstPrinter.h" 18 #include "X86MCAsmInfo.h" 19 #include "llvm/ADT/APInt.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/DebugInfo/CodeView/CodeView.h" 22 #include "llvm/MC/MCDwarf.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCStreamer.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/MC/MachineLocation.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/Host.h" 32 33 using namespace llvm; 34 35 #define GET_REGINFO_MC_DESC 36 #include "X86GenRegisterInfo.inc" 37 38 #define GET_INSTRINFO_MC_DESC 39 #define GET_INSTRINFO_MC_HELPERS 40 #include "X86GenInstrInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "X86GenSubtargetInfo.inc" 44 45 std::string X86_MC::ParseX86Triple(const Triple &TT) { 46 std::string FS; 47 // SSE2 should default to enabled in 64-bit mode, but can be turned off 48 // explicitly. 49 if (TT.isArch64Bit()) 50 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2"; 51 else if (TT.getEnvironment() != Triple::CODE16) 52 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 53 else 54 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 55 56 return FS; 57 } 58 59 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 60 if (TT.getArch() == Triple::x86_64) 61 return DWARFFlavour::X86_64; 62 63 if (TT.isOSDarwin()) 64 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 65 if (TT.isOSCygMing()) 66 // Unsupported by now, just quick fallback 67 return DWARFFlavour::X86_32_Generic; 68 return DWARFFlavour::X86_32_Generic; 69 } 70 71 bool X86_MC::hasLockPrefix(const MCInst &MI) { 72 return MI.getFlags() & X86::IP_HAS_LOCK; 73 } 74 75 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { 76 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 77 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); 78 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; 79 80 return (Base.isReg() && Base.getReg() != 0 && RC.contains(Base.getReg())) || 81 (Index.isReg() && Index.getReg() != 0 && RC.contains(Index.getReg())); 82 } 83 84 bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op, 85 const MCSubtargetInfo &STI) { 86 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 87 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); 88 89 if (STI.hasFeature(X86::Mode16Bit) && Base.isReg() && Base.getReg() == 0 && 90 Index.isReg() && Index.getReg() == 0) 91 return true; 92 return isMemOperand(MI, Op, X86::GR16RegClassID); 93 } 94 95 bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) { 96 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 97 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); 98 if (Base.isReg() && Base.getReg() == X86::EIP) { 99 assert(Index.isReg() && Index.getReg() == 0 && "Invalid eip-based address"); 100 return true; 101 } 102 if (Index.isReg() && Index.getReg() == X86::EIZ) 103 return true; 104 return isMemOperand(MI, Op, X86::GR32RegClassID); 105 } 106 107 #ifndef NDEBUG 108 bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) { 109 return isMemOperand(MI, Op, X86::GR64RegClassID); 110 } 111 #endif 112 113 bool X86_MC::needsAddressSizeOverride(const MCInst &MI, 114 const MCSubtargetInfo &STI, 115 int MemoryOperand, uint64_t TSFlags) { 116 uint64_t AdSize = TSFlags & X86II::AdSizeMask; 117 bool Is16BitMode = STI.hasFeature(X86::Mode16Bit); 118 bool Is32BitMode = STI.hasFeature(X86::Mode32Bit); 119 bool Is64BitMode = STI.hasFeature(X86::Mode64Bit); 120 if ((Is16BitMode && AdSize == X86II::AdSize32) || 121 (Is32BitMode && AdSize == X86II::AdSize16) || 122 (Is64BitMode && AdSize == X86II::AdSize32)) 123 return true; 124 uint64_t Form = TSFlags & X86II::FormMask; 125 switch (Form) { 126 default: 127 break; 128 case X86II::RawFrmDstSrc: { 129 unsigned siReg = MI.getOperand(1).getReg(); 130 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || 131 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || 132 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && 133 "SI and DI register sizes do not match"); 134 return (!Is32BitMode && siReg == X86::ESI) || 135 (Is32BitMode && siReg == X86::SI); 136 } 137 case X86II::RawFrmSrc: { 138 unsigned siReg = MI.getOperand(0).getReg(); 139 return (!Is32BitMode && siReg == X86::ESI) || 140 (Is32BitMode && siReg == X86::SI); 141 } 142 case X86II::RawFrmDst: { 143 unsigned siReg = MI.getOperand(0).getReg(); 144 return (!Is32BitMode && siReg == X86::EDI) || 145 (Is32BitMode && siReg == X86::DI); 146 } 147 } 148 149 // Determine where the memory operand starts, if present. 150 if (MemoryOperand < 0) 151 return false; 152 153 if (STI.hasFeature(X86::Mode64Bit)) { 154 assert(!is16BitMemOperand(MI, MemoryOperand, STI)); 155 return is32BitMemOperand(MI, MemoryOperand); 156 } 157 if (STI.hasFeature(X86::Mode32Bit)) { 158 assert(!is64BitMemOperand(MI, MemoryOperand)); 159 return is16BitMemOperand(MI, MemoryOperand, STI); 160 } 161 assert(STI.hasFeature(X86::Mode16Bit)); 162 assert(!is64BitMemOperand(MI, MemoryOperand)); 163 return !is16BitMemOperand(MI, MemoryOperand, STI); 164 } 165 166 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 167 // FIXME: TableGen these. 168 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 169 unsigned SEH = MRI->getEncodingValue(Reg); 170 MRI->mapLLVMRegToSEHReg(Reg, SEH); 171 } 172 173 // Mapping from CodeView to MC register id. 174 static const struct { 175 codeview::RegisterId CVReg; 176 MCPhysReg Reg; 177 } RegMap[] = { 178 {codeview::RegisterId::AL, X86::AL}, 179 {codeview::RegisterId::CL, X86::CL}, 180 {codeview::RegisterId::DL, X86::DL}, 181 {codeview::RegisterId::BL, X86::BL}, 182 {codeview::RegisterId::AH, X86::AH}, 183 {codeview::RegisterId::CH, X86::CH}, 184 {codeview::RegisterId::DH, X86::DH}, 185 {codeview::RegisterId::BH, X86::BH}, 186 {codeview::RegisterId::AX, X86::AX}, 187 {codeview::RegisterId::CX, X86::CX}, 188 {codeview::RegisterId::DX, X86::DX}, 189 {codeview::RegisterId::BX, X86::BX}, 190 {codeview::RegisterId::SP, X86::SP}, 191 {codeview::RegisterId::BP, X86::BP}, 192 {codeview::RegisterId::SI, X86::SI}, 193 {codeview::RegisterId::DI, X86::DI}, 194 {codeview::RegisterId::EAX, X86::EAX}, 195 {codeview::RegisterId::ECX, X86::ECX}, 196 {codeview::RegisterId::EDX, X86::EDX}, 197 {codeview::RegisterId::EBX, X86::EBX}, 198 {codeview::RegisterId::ESP, X86::ESP}, 199 {codeview::RegisterId::EBP, X86::EBP}, 200 {codeview::RegisterId::ESI, X86::ESI}, 201 {codeview::RegisterId::EDI, X86::EDI}, 202 203 {codeview::RegisterId::EFLAGS, X86::EFLAGS}, 204 205 {codeview::RegisterId::ST0, X86::ST0}, 206 {codeview::RegisterId::ST1, X86::ST1}, 207 {codeview::RegisterId::ST2, X86::ST2}, 208 {codeview::RegisterId::ST3, X86::ST3}, 209 {codeview::RegisterId::ST4, X86::ST4}, 210 {codeview::RegisterId::ST5, X86::ST5}, 211 {codeview::RegisterId::ST6, X86::ST6}, 212 {codeview::RegisterId::ST7, X86::ST7}, 213 214 {codeview::RegisterId::ST0, X86::FP0}, 215 {codeview::RegisterId::ST1, X86::FP1}, 216 {codeview::RegisterId::ST2, X86::FP2}, 217 {codeview::RegisterId::ST3, X86::FP3}, 218 {codeview::RegisterId::ST4, X86::FP4}, 219 {codeview::RegisterId::ST5, X86::FP5}, 220 {codeview::RegisterId::ST6, X86::FP6}, 221 {codeview::RegisterId::ST7, X86::FP7}, 222 223 {codeview::RegisterId::MM0, X86::MM0}, 224 {codeview::RegisterId::MM1, X86::MM1}, 225 {codeview::RegisterId::MM2, X86::MM2}, 226 {codeview::RegisterId::MM3, X86::MM3}, 227 {codeview::RegisterId::MM4, X86::MM4}, 228 {codeview::RegisterId::MM5, X86::MM5}, 229 {codeview::RegisterId::MM6, X86::MM6}, 230 {codeview::RegisterId::MM7, X86::MM7}, 231 232 {codeview::RegisterId::XMM0, X86::XMM0}, 233 {codeview::RegisterId::XMM1, X86::XMM1}, 234 {codeview::RegisterId::XMM2, X86::XMM2}, 235 {codeview::RegisterId::XMM3, X86::XMM3}, 236 {codeview::RegisterId::XMM4, X86::XMM4}, 237 {codeview::RegisterId::XMM5, X86::XMM5}, 238 {codeview::RegisterId::XMM6, X86::XMM6}, 239 {codeview::RegisterId::XMM7, X86::XMM7}, 240 241 {codeview::RegisterId::XMM8, X86::XMM8}, 242 {codeview::RegisterId::XMM9, X86::XMM9}, 243 {codeview::RegisterId::XMM10, X86::XMM10}, 244 {codeview::RegisterId::XMM11, X86::XMM11}, 245 {codeview::RegisterId::XMM12, X86::XMM12}, 246 {codeview::RegisterId::XMM13, X86::XMM13}, 247 {codeview::RegisterId::XMM14, X86::XMM14}, 248 {codeview::RegisterId::XMM15, X86::XMM15}, 249 250 {codeview::RegisterId::SIL, X86::SIL}, 251 {codeview::RegisterId::DIL, X86::DIL}, 252 {codeview::RegisterId::BPL, X86::BPL}, 253 {codeview::RegisterId::SPL, X86::SPL}, 254 {codeview::RegisterId::RAX, X86::RAX}, 255 {codeview::RegisterId::RBX, X86::RBX}, 256 {codeview::RegisterId::RCX, X86::RCX}, 257 {codeview::RegisterId::RDX, X86::RDX}, 258 {codeview::RegisterId::RSI, X86::RSI}, 259 {codeview::RegisterId::RDI, X86::RDI}, 260 {codeview::RegisterId::RBP, X86::RBP}, 261 {codeview::RegisterId::RSP, X86::RSP}, 262 {codeview::RegisterId::R8, X86::R8}, 263 {codeview::RegisterId::R9, X86::R9}, 264 {codeview::RegisterId::R10, X86::R10}, 265 {codeview::RegisterId::R11, X86::R11}, 266 {codeview::RegisterId::R12, X86::R12}, 267 {codeview::RegisterId::R13, X86::R13}, 268 {codeview::RegisterId::R14, X86::R14}, 269 {codeview::RegisterId::R15, X86::R15}, 270 {codeview::RegisterId::R8B, X86::R8B}, 271 {codeview::RegisterId::R9B, X86::R9B}, 272 {codeview::RegisterId::R10B, X86::R10B}, 273 {codeview::RegisterId::R11B, X86::R11B}, 274 {codeview::RegisterId::R12B, X86::R12B}, 275 {codeview::RegisterId::R13B, X86::R13B}, 276 {codeview::RegisterId::R14B, X86::R14B}, 277 {codeview::RegisterId::R15B, X86::R15B}, 278 {codeview::RegisterId::R8W, X86::R8W}, 279 {codeview::RegisterId::R9W, X86::R9W}, 280 {codeview::RegisterId::R10W, X86::R10W}, 281 {codeview::RegisterId::R11W, X86::R11W}, 282 {codeview::RegisterId::R12W, X86::R12W}, 283 {codeview::RegisterId::R13W, X86::R13W}, 284 {codeview::RegisterId::R14W, X86::R14W}, 285 {codeview::RegisterId::R15W, X86::R15W}, 286 {codeview::RegisterId::R8D, X86::R8D}, 287 {codeview::RegisterId::R9D, X86::R9D}, 288 {codeview::RegisterId::R10D, X86::R10D}, 289 {codeview::RegisterId::R11D, X86::R11D}, 290 {codeview::RegisterId::R12D, X86::R12D}, 291 {codeview::RegisterId::R13D, X86::R13D}, 292 {codeview::RegisterId::R14D, X86::R14D}, 293 {codeview::RegisterId::R15D, X86::R15D}, 294 {codeview::RegisterId::AMD64_YMM0, X86::YMM0}, 295 {codeview::RegisterId::AMD64_YMM1, X86::YMM1}, 296 {codeview::RegisterId::AMD64_YMM2, X86::YMM2}, 297 {codeview::RegisterId::AMD64_YMM3, X86::YMM3}, 298 {codeview::RegisterId::AMD64_YMM4, X86::YMM4}, 299 {codeview::RegisterId::AMD64_YMM5, X86::YMM5}, 300 {codeview::RegisterId::AMD64_YMM6, X86::YMM6}, 301 {codeview::RegisterId::AMD64_YMM7, X86::YMM7}, 302 {codeview::RegisterId::AMD64_YMM8, X86::YMM8}, 303 {codeview::RegisterId::AMD64_YMM9, X86::YMM9}, 304 {codeview::RegisterId::AMD64_YMM10, X86::YMM10}, 305 {codeview::RegisterId::AMD64_YMM11, X86::YMM11}, 306 {codeview::RegisterId::AMD64_YMM12, X86::YMM12}, 307 {codeview::RegisterId::AMD64_YMM13, X86::YMM13}, 308 {codeview::RegisterId::AMD64_YMM14, X86::YMM14}, 309 {codeview::RegisterId::AMD64_YMM15, X86::YMM15}, 310 {codeview::RegisterId::AMD64_YMM16, X86::YMM16}, 311 {codeview::RegisterId::AMD64_YMM17, X86::YMM17}, 312 {codeview::RegisterId::AMD64_YMM18, X86::YMM18}, 313 {codeview::RegisterId::AMD64_YMM19, X86::YMM19}, 314 {codeview::RegisterId::AMD64_YMM20, X86::YMM20}, 315 {codeview::RegisterId::AMD64_YMM21, X86::YMM21}, 316 {codeview::RegisterId::AMD64_YMM22, X86::YMM22}, 317 {codeview::RegisterId::AMD64_YMM23, X86::YMM23}, 318 {codeview::RegisterId::AMD64_YMM24, X86::YMM24}, 319 {codeview::RegisterId::AMD64_YMM25, X86::YMM25}, 320 {codeview::RegisterId::AMD64_YMM26, X86::YMM26}, 321 {codeview::RegisterId::AMD64_YMM27, X86::YMM27}, 322 {codeview::RegisterId::AMD64_YMM28, X86::YMM28}, 323 {codeview::RegisterId::AMD64_YMM29, X86::YMM29}, 324 {codeview::RegisterId::AMD64_YMM30, X86::YMM30}, 325 {codeview::RegisterId::AMD64_YMM31, X86::YMM31}, 326 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0}, 327 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1}, 328 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2}, 329 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3}, 330 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4}, 331 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5}, 332 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6}, 333 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7}, 334 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8}, 335 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9}, 336 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10}, 337 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11}, 338 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12}, 339 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13}, 340 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14}, 341 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15}, 342 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16}, 343 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17}, 344 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18}, 345 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19}, 346 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20}, 347 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21}, 348 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22}, 349 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23}, 350 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24}, 351 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25}, 352 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26}, 353 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27}, 354 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28}, 355 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29}, 356 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30}, 357 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31}, 358 {codeview::RegisterId::AMD64_K0, X86::K0}, 359 {codeview::RegisterId::AMD64_K1, X86::K1}, 360 {codeview::RegisterId::AMD64_K2, X86::K2}, 361 {codeview::RegisterId::AMD64_K3, X86::K3}, 362 {codeview::RegisterId::AMD64_K4, X86::K4}, 363 {codeview::RegisterId::AMD64_K5, X86::K5}, 364 {codeview::RegisterId::AMD64_K6, X86::K6}, 365 {codeview::RegisterId::AMD64_K7, X86::K7}, 366 {codeview::RegisterId::AMD64_XMM16, X86::XMM16}, 367 {codeview::RegisterId::AMD64_XMM17, X86::XMM17}, 368 {codeview::RegisterId::AMD64_XMM18, X86::XMM18}, 369 {codeview::RegisterId::AMD64_XMM19, X86::XMM19}, 370 {codeview::RegisterId::AMD64_XMM20, X86::XMM20}, 371 {codeview::RegisterId::AMD64_XMM21, X86::XMM21}, 372 {codeview::RegisterId::AMD64_XMM22, X86::XMM22}, 373 {codeview::RegisterId::AMD64_XMM23, X86::XMM23}, 374 {codeview::RegisterId::AMD64_XMM24, X86::XMM24}, 375 {codeview::RegisterId::AMD64_XMM25, X86::XMM25}, 376 {codeview::RegisterId::AMD64_XMM26, X86::XMM26}, 377 {codeview::RegisterId::AMD64_XMM27, X86::XMM27}, 378 {codeview::RegisterId::AMD64_XMM28, X86::XMM28}, 379 {codeview::RegisterId::AMD64_XMM29, X86::XMM29}, 380 {codeview::RegisterId::AMD64_XMM30, X86::XMM30}, 381 {codeview::RegisterId::AMD64_XMM31, X86::XMM31}, 382 383 }; 384 for (const auto &I : RegMap) 385 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 386 } 387 388 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 389 StringRef CPU, StringRef FS) { 390 std::string ArchFS = X86_MC::ParseX86Triple(TT); 391 assert(!ArchFS.empty() && "Failed to parse X86 triple"); 392 if (!FS.empty()) 393 ArchFS = (Twine(ArchFS) + "," + FS).str(); 394 395 if (CPU.empty()) 396 CPU = "generic"; 397 398 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS); 399 } 400 401 static MCInstrInfo *createX86MCInstrInfo() { 402 MCInstrInfo *X = new MCInstrInfo(); 403 InitX86MCInstrInfo(X); 404 return X; 405 } 406 407 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 408 unsigned RA = (TT.getArch() == Triple::x86_64) 409 ? X86::RIP // Should have dwarf #16. 410 : X86::EIP; // Should have dwarf #8. 411 412 MCRegisterInfo *X = new MCRegisterInfo(); 413 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 414 X86_MC::getDwarfRegFlavour(TT, true), RA); 415 X86_MC::initLLVMToSEHAndCVRegMapping(X); 416 return X; 417 } 418 419 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 420 const Triple &TheTriple, 421 const MCTargetOptions &Options) { 422 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 423 424 MCAsmInfo *MAI; 425 if (TheTriple.isOSBinFormatMachO()) { 426 if (is64Bit) 427 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 428 else 429 MAI = new X86MCAsmInfoDarwin(TheTriple); 430 } else if (TheTriple.isOSBinFormatELF()) { 431 // Force the use of an ELF container. 432 MAI = new X86ELFMCAsmInfo(TheTriple); 433 } else if (TheTriple.isWindowsMSVCEnvironment() || 434 TheTriple.isWindowsCoreCLREnvironment()) { 435 if (Options.getAssemblyLanguage().equals_insensitive("masm")) 436 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple); 437 else 438 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 439 } else if (TheTriple.isOSCygMing() || 440 TheTriple.isWindowsItaniumEnvironment()) { 441 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 442 } else { 443 // The default is ELF. 444 MAI = new X86ELFMCAsmInfo(TheTriple); 445 } 446 447 // Initialize initial frame state. 448 // Calculate amount of bytes used for return address storing 449 int stackGrowth = is64Bit ? -8 : -4; 450 451 // Initial state of the frame pointer is esp+stackGrowth. 452 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 453 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( 454 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 455 MAI->addInitialFrameState(Inst); 456 457 // Add return address to move list 458 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 459 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 460 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 461 MAI->addInitialFrameState(Inst2); 462 463 return MAI; 464 } 465 466 static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 467 unsigned SyntaxVariant, 468 const MCAsmInfo &MAI, 469 const MCInstrInfo &MII, 470 const MCRegisterInfo &MRI) { 471 if (SyntaxVariant == 0) 472 return new X86ATTInstPrinter(MAI, MII, MRI); 473 if (SyntaxVariant == 1) 474 return new X86IntelInstPrinter(MAI, MII, MRI); 475 return nullptr; 476 } 477 478 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 479 MCContext &Ctx) { 480 // Default to the stock relocation info. 481 return llvm::createMCRelocationInfo(TheTriple, Ctx); 482 } 483 484 namespace llvm { 485 namespace X86_MC { 486 487 class X86MCInstrAnalysis : public MCInstrAnalysis { 488 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete; 489 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete; 490 virtual ~X86MCInstrAnalysis() = default; 491 492 public: 493 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {} 494 495 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 496 #include "X86GenSubtargetInfo.inc" 497 498 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, 499 APInt &Mask) const override; 500 std::vector<std::pair<uint64_t, uint64_t>> 501 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 502 uint64_t GotSectionVA, 503 const Triple &TargetTriple) const override; 504 505 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 506 uint64_t &Target) const override; 507 Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst, 508 const MCSubtargetInfo *STI, 509 uint64_t Addr, 510 uint64_t Size) const override; 511 Optional<uint64_t> 512 getMemoryOperandRelocationOffset(const MCInst &Inst, 513 uint64_t Size) const override; 514 }; 515 516 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 517 #include "X86GenSubtargetInfo.inc" 518 519 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, 520 const MCInst &Inst, 521 APInt &Mask) const { 522 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 523 unsigned NumDefs = Desc.getNumDefs(); 524 unsigned NumImplicitDefs = Desc.getNumImplicitDefs(); 525 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs && 526 "Unexpected number of bits in the mask!"); 527 528 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX; 529 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; 530 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP; 531 532 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); 533 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); 534 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); 535 536 auto ClearsSuperReg = [=](unsigned RegID) { 537 // On X86-64, a general purpose integer register is viewed as a 64-bit 538 // register internal to the processor. 539 // An update to the lower 32 bits of a 64 bit integer register is 540 // architecturally defined to zero extend the upper 32 bits. 541 if (GR32RC.contains(RegID)) 542 return true; 543 544 // Early exit if this instruction has no vex/evex/xop prefix. 545 if (!HasEVEX && !HasVEX && !HasXOP) 546 return false; 547 548 // All VEX and EVEX encoded instructions are defined to zero the high bits 549 // of the destination register up to VLMAX (i.e. the maximum vector register 550 // width pertaining to the instruction). 551 // We assume the same behavior for XOP instructions too. 552 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); 553 }; 554 555 Mask.clearAllBits(); 556 for (unsigned I = 0, E = NumDefs; I < E; ++I) { 557 const MCOperand &Op = Inst.getOperand(I); 558 if (ClearsSuperReg(Op.getReg())) 559 Mask.setBit(I); 560 } 561 562 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) { 563 const MCPhysReg Reg = Desc.getImplicitDefs()[I]; 564 if (ClearsSuperReg(Reg)) 565 Mask.setBit(NumDefs + I); 566 } 567 568 return Mask.getBoolValue(); 569 } 570 571 static std::vector<std::pair<uint64_t, uint64_t>> 572 findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 573 uint64_t GotPltSectionVA) { 574 // Do a lightweight parsing of PLT entries. 575 std::vector<std::pair<uint64_t, uint64_t>> Result; 576 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 577 // Recognize a jmp. 578 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) { 579 // The jmp instruction at the beginning of each PLT entry jumps to the 580 // address of the base of the .got.plt section plus the immediate. 581 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 582 Result.push_back( 583 std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm)); 584 Byte += 6; 585 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 586 // The jmp instruction at the beginning of each PLT entry jumps to the 587 // immediate. 588 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 589 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 590 Byte += 6; 591 } else 592 Byte++; 593 } 594 return Result; 595 } 596 597 static std::vector<std::pair<uint64_t, uint64_t>> 598 findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) { 599 // Do a lightweight parsing of PLT entries. 600 std::vector<std::pair<uint64_t, uint64_t>> Result; 601 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 602 // Recognize a jmp. 603 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 604 // The jmp instruction at the beginning of each PLT entry jumps to the 605 // address of the next instruction plus the immediate. 606 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 607 Result.push_back( 608 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm)); 609 Byte += 6; 610 } else 611 Byte++; 612 } 613 return Result; 614 } 615 616 std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries( 617 uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 618 uint64_t GotPltSectionVA, const Triple &TargetTriple) const { 619 switch (TargetTriple.getArch()) { 620 case Triple::x86: 621 return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA); 622 case Triple::x86_64: 623 return findX86_64PltEntries(PltSectionVA, PltContents); 624 default: 625 return {}; 626 } 627 } 628 629 bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, 630 uint64_t Size, uint64_t &Target) const { 631 if (Inst.getNumOperands() == 0 || 632 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 633 return false; 634 Target = Addr + Size + Inst.getOperand(0).getImm(); 635 return true; 636 } 637 638 Optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress( 639 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, 640 uint64_t Size) const { 641 const MCInstrDesc &MCID = Info->get(Inst.getOpcode()); 642 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags); 643 if (MemOpStart == -1) 644 return None; 645 MemOpStart += X86II::getOperandBias(MCID); 646 647 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); 648 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); 649 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); 650 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); 651 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); 652 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || 653 !Disp.isImm()) 654 return None; 655 656 // RIP-relative addressing. 657 if (BaseReg.getReg() == X86::RIP) 658 return Addr + Size + Disp.getImm(); 659 660 return None; 661 } 662 663 Optional<uint64_t> 664 X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst, 665 uint64_t Size) const { 666 if (Inst.getOpcode() != X86::LEA64r) 667 return None; 668 const MCInstrDesc &MCID = Info->get(Inst.getOpcode()); 669 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags); 670 if (MemOpStart == -1) 671 return None; 672 MemOpStart += X86II::getOperandBias(MCID); 673 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); 674 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); 675 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); 676 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); 677 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); 678 // Must be a simple rip-relative address. 679 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() != 0 || 680 IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm()) 681 return None; 682 // rip-relative ModR/M immediate is 32 bits. 683 assert(Size > 4 && "invalid instruction size for rip-relative lea"); 684 return Size - 4; 685 } 686 687 } // end of namespace X86_MC 688 689 } // end of namespace llvm 690 691 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 692 return new X86_MC::X86MCInstrAnalysis(Info); 693 } 694 695 // Force static initialization. 696 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC() { 697 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) { 698 // Register the MC asm info. 699 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 700 701 // Register the MC instruction info. 702 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 703 704 // Register the MC register info. 705 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 706 707 // Register the MC subtarget info. 708 TargetRegistry::RegisterMCSubtargetInfo(*T, 709 X86_MC::createX86MCSubtargetInfo); 710 711 // Register the MC instruction analyzer. 712 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 713 714 // Register the code emitter. 715 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 716 717 // Register the obj target streamer. 718 TargetRegistry::RegisterObjectTargetStreamer(*T, 719 createX86ObjectTargetStreamer); 720 721 // Register the asm target streamer. 722 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer); 723 724 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 725 726 // Register the MCInstPrinter. 727 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 728 729 // Register the MC relocation info. 730 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 731 } 732 733 // Register the asm backend. 734 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(), 735 createX86_32AsmBackend); 736 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(), 737 createX86_64AsmBackend); 738 } 739 740 MCRegister llvm::getX86SubSuperRegisterOrZero(MCRegister Reg, unsigned Size, 741 bool High) { 742 switch (Size) { 743 default: return X86::NoRegister; 744 case 8: 745 if (High) { 746 switch (Reg.id()) { 747 default: return getX86SubSuperRegisterOrZero(Reg, 64); 748 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 749 return X86::SI; 750 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 751 return X86::DI; 752 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 753 return X86::BP; 754 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 755 return X86::SP; 756 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 757 return X86::AH; 758 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 759 return X86::DH; 760 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 761 return X86::CH; 762 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 763 return X86::BH; 764 } 765 } else { 766 switch (Reg.id()) { 767 default: return X86::NoRegister; 768 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 769 return X86::AL; 770 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 771 return X86::DL; 772 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 773 return X86::CL; 774 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 775 return X86::BL; 776 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 777 return X86::SIL; 778 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 779 return X86::DIL; 780 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 781 return X86::BPL; 782 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 783 return X86::SPL; 784 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 785 return X86::R8B; 786 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 787 return X86::R9B; 788 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 789 return X86::R10B; 790 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 791 return X86::R11B; 792 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 793 return X86::R12B; 794 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 795 return X86::R13B; 796 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 797 return X86::R14B; 798 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 799 return X86::R15B; 800 } 801 } 802 case 16: 803 switch (Reg.id()) { 804 default: return X86::NoRegister; 805 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 806 return X86::AX; 807 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 808 return X86::DX; 809 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 810 return X86::CX; 811 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 812 return X86::BX; 813 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 814 return X86::SI; 815 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 816 return X86::DI; 817 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 818 return X86::BP; 819 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 820 return X86::SP; 821 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 822 return X86::R8W; 823 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 824 return X86::R9W; 825 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 826 return X86::R10W; 827 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 828 return X86::R11W; 829 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 830 return X86::R12W; 831 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 832 return X86::R13W; 833 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 834 return X86::R14W; 835 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 836 return X86::R15W; 837 } 838 case 32: 839 switch (Reg.id()) { 840 default: return X86::NoRegister; 841 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 842 return X86::EAX; 843 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 844 return X86::EDX; 845 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 846 return X86::ECX; 847 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 848 return X86::EBX; 849 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 850 return X86::ESI; 851 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 852 return X86::EDI; 853 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 854 return X86::EBP; 855 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 856 return X86::ESP; 857 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 858 return X86::R8D; 859 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 860 return X86::R9D; 861 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 862 return X86::R10D; 863 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 864 return X86::R11D; 865 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 866 return X86::R12D; 867 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 868 return X86::R13D; 869 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 870 return X86::R14D; 871 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 872 return X86::R15D; 873 } 874 case 64: 875 switch (Reg.id()) { 876 default: return 0; 877 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 878 return X86::RAX; 879 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 880 return X86::RDX; 881 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 882 return X86::RCX; 883 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 884 return X86::RBX; 885 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 886 return X86::RSI; 887 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 888 return X86::RDI; 889 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 890 return X86::RBP; 891 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 892 return X86::RSP; 893 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 894 return X86::R8; 895 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 896 return X86::R9; 897 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 898 return X86::R10; 899 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 900 return X86::R11; 901 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 902 return X86::R12; 903 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 904 return X86::R13; 905 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 906 return X86::R14; 907 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 908 return X86::R15; 909 } 910 } 911 } 912 913 MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High) { 914 MCRegister Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 915 assert(Res != X86::NoRegister && "Unexpected register or VT"); 916 return Res; 917 } 918 919 920