1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86MCTargetDesc.h" 15 #include "InstPrinter/X86ATTInstPrinter.h" 16 #include "InstPrinter/X86IntelInstPrinter.h" 17 #include "X86MCAsmInfo.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCCodeGenInfo.h" 20 #include "llvm/MC/MCInstrAnalysis.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCStreamer.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/MachineLocation.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/Host.h" 28 #include "llvm/Support/TargetRegistry.h" 29 30 #if _MSC_VER 31 #include <intrin.h> 32 #endif 33 34 using namespace llvm; 35 36 #define GET_REGINFO_MC_DESC 37 #include "X86GenRegisterInfo.inc" 38 39 #define GET_INSTRINFO_MC_DESC 40 #include "X86GenInstrInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "X86GenSubtargetInfo.inc" 44 45 std::string X86_MC::ParseX86Triple(const Triple &TT) { 46 std::string FS; 47 if (TT.getArch() == Triple::x86_64) 48 FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 49 else if (TT.getEnvironment() != Triple::CODE16) 50 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 51 else 52 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 53 54 return FS; 55 } 56 57 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 58 if (TT.getArch() == Triple::x86_64) 59 return DWARFFlavour::X86_64; 60 61 if (TT.isOSDarwin()) 62 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 63 if (TT.isOSCygMing()) 64 // Unsupported by now, just quick fallback 65 return DWARFFlavour::X86_32_Generic; 66 return DWARFFlavour::X86_32_Generic; 67 } 68 69 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 70 // FIXME: TableGen these. 71 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 72 unsigned SEH = MRI->getEncodingValue(Reg); 73 MRI->mapLLVMRegToSEHReg(Reg, SEH); 74 } 75 76 // These CodeView registers are numbered sequentially starting at value 1. 77 static const MCPhysReg LowCVRegs[] = { 78 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, 79 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, 80 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, 81 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, 82 }; 83 unsigned CVLowRegStart = 1; 84 for (unsigned I = 0; I < array_lengthof(LowCVRegs); ++I) 85 MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); 86 87 MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); 88 89 // The x87 registers start at 128 and are numbered sequentially. 90 unsigned FP0Start = 128; 91 for (unsigned I = 0; I < 8; ++I) 92 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); 93 94 // The low 8 XMM registers start at 154 and are numbered sequentially. 95 unsigned CVXMM0Start = 154; 96 for (unsigned I = 0; I < 8; ++I) 97 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); 98 99 // The high 8 XMM registers start at 252 and are numbered sequentially. 100 unsigned CVXMM8Start = 252; 101 for (unsigned I = 0; I < 8; ++I) 102 MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); 103 104 // FIXME: XMM16 and above from AVX512 not yet documented. 105 106 // AMD64 registers start at 324 and count up. 107 unsigned CVX64RegStart = 324; 108 static const MCPhysReg CVX64Regs[] = { 109 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, 110 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, 111 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, 112 X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, 113 X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, 114 X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, 115 X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, 116 X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, 117 X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, 118 X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 119 }; 120 for (unsigned I = 0; I < array_lengthof(CVX64Regs); ++I) 121 MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); 122 } 123 124 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 125 StringRef CPU, StringRef FS) { 126 std::string ArchFS = X86_MC::ParseX86Triple(TT); 127 if (!FS.empty()) { 128 if (!ArchFS.empty()) 129 ArchFS = (Twine(ArchFS) + "," + FS).str(); 130 else 131 ArchFS = FS; 132 } 133 134 std::string CPUName = CPU; 135 if (CPUName.empty()) 136 CPUName = "generic"; 137 138 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); 139 } 140 141 static MCInstrInfo *createX86MCInstrInfo() { 142 MCInstrInfo *X = new MCInstrInfo(); 143 InitX86MCInstrInfo(X); 144 return X; 145 } 146 147 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 148 unsigned RA = (TT.getArch() == Triple::x86_64) 149 ? X86::RIP // Should have dwarf #16. 150 : X86::EIP; // Should have dwarf #8. 151 152 MCRegisterInfo *X = new MCRegisterInfo(); 153 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 154 X86_MC::getDwarfRegFlavour(TT, true), RA); 155 X86_MC::initLLVMToSEHAndCVRegMapping(X); 156 return X; 157 } 158 159 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 160 const Triple &TheTriple) { 161 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 162 163 MCAsmInfo *MAI; 164 if (TheTriple.isOSBinFormatMachO()) { 165 if (is64Bit) 166 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 167 else 168 MAI = new X86MCAsmInfoDarwin(TheTriple); 169 } else if (TheTriple.isOSBinFormatELF()) { 170 // Force the use of an ELF container. 171 MAI = new X86ELFMCAsmInfo(TheTriple); 172 } else if (TheTriple.isWindowsMSVCEnvironment() || 173 TheTriple.isWindowsCoreCLREnvironment()) { 174 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 175 } else if (TheTriple.isOSCygMing() || 176 TheTriple.isWindowsItaniumEnvironment()) { 177 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 178 } else { 179 // The default is ELF. 180 MAI = new X86ELFMCAsmInfo(TheTriple); 181 } 182 183 // Initialize initial frame state. 184 // Calculate amount of bytes used for return address storing 185 int stackGrowth = is64Bit ? -8 : -4; 186 187 // Initial state of the frame pointer is esp+stackGrowth. 188 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 189 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( 190 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 191 MAI->addInitialFrameState(Inst); 192 193 // Add return address to move list 194 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 195 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 196 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 197 MAI->addInitialFrameState(Inst2); 198 199 return MAI; 200 } 201 202 static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, 203 CodeModel::Model CM, 204 CodeGenOpt::Level OL) { 205 MCCodeGenInfo *X = new MCCodeGenInfo(); 206 207 bool is64Bit = TT.getArch() == Triple::x86_64; 208 209 // For static codegen, if we're not already set, use Small codegen. 210 if (CM == CodeModel::Default) 211 CM = CodeModel::Small; 212 else if (CM == CodeModel::JITDefault) 213 // 64-bit JIT places everything in the same buffer except external funcs. 214 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 215 216 X->initMCCodeGenInfo(RM, CM, OL); 217 return X; 218 } 219 220 static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 221 unsigned SyntaxVariant, 222 const MCAsmInfo &MAI, 223 const MCInstrInfo &MII, 224 const MCRegisterInfo &MRI) { 225 if (SyntaxVariant == 0) 226 return new X86ATTInstPrinter(MAI, MII, MRI); 227 if (SyntaxVariant == 1) 228 return new X86IntelInstPrinter(MAI, MII, MRI); 229 return nullptr; 230 } 231 232 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 233 MCContext &Ctx) { 234 // Default to the stock relocation info. 235 return llvm::createMCRelocationInfo(TheTriple, Ctx); 236 } 237 238 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 239 return new MCInstrAnalysis(Info); 240 } 241 242 // Force static initialization. 243 extern "C" void LLVMInitializeX86TargetMC() { 244 for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { 245 // Register the MC asm info. 246 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 247 248 // Register the MC codegen info. 249 RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo); 250 251 // Register the MC instruction info. 252 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 253 254 // Register the MC register info. 255 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 256 257 // Register the MC subtarget info. 258 TargetRegistry::RegisterMCSubtargetInfo(*T, 259 X86_MC::createX86MCSubtargetInfo); 260 261 // Register the MC instruction analyzer. 262 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 263 264 // Register the code emitter. 265 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 266 267 // Register the object streamer. 268 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 269 270 // Register the MCInstPrinter. 271 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 272 273 // Register the MC relocation info. 274 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 275 } 276 277 // Register the asm backend. 278 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 279 createX86_32AsmBackend); 280 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 281 createX86_64AsmBackend); 282 } 283 284 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, 285 bool High) { 286 switch (Size) { 287 default: return 0; 288 case 8: 289 if (High) { 290 switch (Reg) { 291 default: return getX86SubSuperRegisterOrZero(Reg, 64); 292 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 293 return X86::SI; 294 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 295 return X86::DI; 296 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 297 return X86::BP; 298 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 299 return X86::SP; 300 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 301 return X86::AH; 302 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 303 return X86::DH; 304 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 305 return X86::CH; 306 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 307 return X86::BH; 308 } 309 } else { 310 switch (Reg) { 311 default: return 0; 312 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 313 return X86::AL; 314 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 315 return X86::DL; 316 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 317 return X86::CL; 318 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 319 return X86::BL; 320 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 321 return X86::SIL; 322 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 323 return X86::DIL; 324 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 325 return X86::BPL; 326 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 327 return X86::SPL; 328 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 329 return X86::R8B; 330 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 331 return X86::R9B; 332 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 333 return X86::R10B; 334 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 335 return X86::R11B; 336 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 337 return X86::R12B; 338 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 339 return X86::R13B; 340 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 341 return X86::R14B; 342 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 343 return X86::R15B; 344 } 345 } 346 case 16: 347 switch (Reg) { 348 default: return 0; 349 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 350 return X86::AX; 351 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 352 return X86::DX; 353 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 354 return X86::CX; 355 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 356 return X86::BX; 357 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 358 return X86::SI; 359 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 360 return X86::DI; 361 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 362 return X86::BP; 363 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 364 return X86::SP; 365 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 366 return X86::R8W; 367 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 368 return X86::R9W; 369 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 370 return X86::R10W; 371 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 372 return X86::R11W; 373 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 374 return X86::R12W; 375 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 376 return X86::R13W; 377 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 378 return X86::R14W; 379 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 380 return X86::R15W; 381 } 382 case 32: 383 switch (Reg) { 384 default: return 0; 385 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 386 return X86::EAX; 387 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 388 return X86::EDX; 389 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 390 return X86::ECX; 391 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 392 return X86::EBX; 393 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 394 return X86::ESI; 395 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 396 return X86::EDI; 397 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 398 return X86::EBP; 399 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 400 return X86::ESP; 401 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 402 return X86::R8D; 403 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 404 return X86::R9D; 405 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 406 return X86::R10D; 407 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 408 return X86::R11D; 409 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 410 return X86::R12D; 411 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 412 return X86::R13D; 413 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 414 return X86::R14D; 415 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 416 return X86::R15D; 417 } 418 case 64: 419 switch (Reg) { 420 default: return 0; 421 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 422 return X86::RAX; 423 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 424 return X86::RDX; 425 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 426 return X86::RCX; 427 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 428 return X86::RBX; 429 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 430 return X86::RSI; 431 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 432 return X86::RDI; 433 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 434 return X86::RBP; 435 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 436 return X86::RSP; 437 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 438 return X86::R8; 439 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 440 return X86::R9; 441 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 442 return X86::R10; 443 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 444 return X86::R11; 445 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 446 return X86::R12; 447 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 448 return X86::R13; 449 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 450 return X86::R14; 451 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 452 return X86::R15; 453 } 454 } 455 } 456 457 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { 458 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 459 assert(Res != 0 && "Unexpected register or VT"); 460 return Res; 461 } 462 463 464