1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides X86 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86MCTargetDesc.h"
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "InstPrinter/X86IntelInstPrinter.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/Host.h"
28 #include "llvm/Support/TargetRegistry.h"
29 
30 #if _MSC_VER
31 #include <intrin.h>
32 #endif
33 
34 using namespace llvm;
35 
36 #define GET_REGINFO_MC_DESC
37 #include "X86GenRegisterInfo.inc"
38 
39 #define GET_INSTRINFO_MC_DESC
40 #include "X86GenInstrInfo.inc"
41 
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
44 
45 std::string X86_MC::ParseX86Triple(const Triple &TT) {
46   std::string FS;
47   if (TT.getArch() == Triple::x86_64)
48     FS = "+64bit-mode,-32bit-mode,-16bit-mode";
49   else if (TT.getEnvironment() != Triple::CODE16)
50     FS = "-64bit-mode,+32bit-mode,-16bit-mode";
51   else
52     FS = "-64bit-mode,-32bit-mode,+16bit-mode";
53 
54   return FS;
55 }
56 
57 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
58   if (TT.getArch() == Triple::x86_64)
59     return DWARFFlavour::X86_64;
60 
61   if (TT.isOSDarwin())
62     return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
63   if (TT.isOSCygMing())
64     // Unsupported by now, just quick fallback
65     return DWARFFlavour::X86_32_Generic;
66   return DWARFFlavour::X86_32_Generic;
67 }
68 
69 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
70   // FIXME: TableGen these.
71   for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
72     unsigned SEH = MRI->getEncodingValue(Reg);
73     MRI->mapLLVMRegToSEHReg(Reg, SEH);
74   }
75 }
76 
77 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
78                                                   StringRef CPU, StringRef FS) {
79   std::string ArchFS = X86_MC::ParseX86Triple(TT);
80   if (!FS.empty()) {
81     if (!ArchFS.empty())
82       ArchFS = (Twine(ArchFS) + "," + FS).str();
83     else
84       ArchFS = FS;
85   }
86 
87   std::string CPUName = CPU;
88   if (CPUName.empty())
89     CPUName = "generic";
90 
91   MCSubtargetInfo *X = new MCSubtargetInfo();
92   InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
93   return X;
94 }
95 
96 static MCInstrInfo *createX86MCInstrInfo() {
97   MCInstrInfo *X = new MCInstrInfo();
98   InitX86MCInstrInfo(X);
99   return X;
100 }
101 
102 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
103   unsigned RA = (TT.getArch() == Triple::x86_64)
104                     ? X86::RIP  // Should have dwarf #16.
105                     : X86::EIP; // Should have dwarf #8.
106 
107   MCRegisterInfo *X = new MCRegisterInfo();
108   InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
109                         X86_MC::getDwarfRegFlavour(TT, true), RA);
110   X86_MC::InitLLVM2SEHRegisterMapping(X);
111   return X;
112 }
113 
114 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
115                                      const Triple &TheTriple) {
116   bool is64Bit = TheTriple.getArch() == Triple::x86_64;
117 
118   MCAsmInfo *MAI;
119   if (TheTriple.isOSBinFormatMachO()) {
120     if (is64Bit)
121       MAI = new X86_64MCAsmInfoDarwin(TheTriple);
122     else
123       MAI = new X86MCAsmInfoDarwin(TheTriple);
124   } else if (TheTriple.isOSBinFormatELF()) {
125     // Force the use of an ELF container.
126     MAI = new X86ELFMCAsmInfo(TheTriple);
127   } else if (TheTriple.isWindowsMSVCEnvironment()) {
128     MAI = new X86MCAsmInfoMicrosoft(TheTriple);
129   } else if (TheTriple.isOSCygMing() ||
130              TheTriple.isWindowsItaniumEnvironment()) {
131     MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
132   } else {
133     // The default is ELF.
134     MAI = new X86ELFMCAsmInfo(TheTriple);
135   }
136 
137   // Initialize initial frame state.
138   // Calculate amount of bytes used for return address storing
139   int stackGrowth = is64Bit ? -8 : -4;
140 
141   // Initial state of the frame pointer is esp+stackGrowth.
142   unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
143   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
144       nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
145   MAI->addInitialFrameState(Inst);
146 
147   // Add return address to move list
148   unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
149   MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
150       nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
151   MAI->addInitialFrameState(Inst2);
152 
153   return MAI;
154 }
155 
156 static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
157                                              CodeModel::Model CM,
158                                              CodeGenOpt::Level OL) {
159   MCCodeGenInfo *X = new MCCodeGenInfo();
160 
161   bool is64Bit = TT.getArch() == Triple::x86_64;
162 
163   if (RM == Reloc::Default) {
164     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
165     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
166     // use static relocation model by default.
167     if (TT.isOSDarwin()) {
168       if (is64Bit)
169         RM = Reloc::PIC_;
170       else
171         RM = Reloc::DynamicNoPIC;
172     } else if (TT.isOSWindows() && is64Bit)
173       RM = Reloc::PIC_;
174     else
175       RM = Reloc::Static;
176   }
177 
178   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
179   // is defined as a model for code which may be used in static or dynamic
180   // executables but not necessarily a shared library. On X86-32 we just
181   // compile in -static mode, in x86-64 we use PIC.
182   if (RM == Reloc::DynamicNoPIC) {
183     if (is64Bit)
184       RM = Reloc::PIC_;
185     else if (!TT.isOSDarwin())
186       RM = Reloc::Static;
187   }
188 
189   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
190   // the Mach-O file format doesn't support it.
191   if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
192     RM = Reloc::PIC_;
193 
194   // For static codegen, if we're not already set, use Small codegen.
195   if (CM == CodeModel::Default)
196     CM = CodeModel::Small;
197   else if (CM == CodeModel::JITDefault)
198     // 64-bit JIT places everything in the same buffer except external funcs.
199     CM = is64Bit ? CodeModel::Large : CodeModel::Small;
200 
201   X->initMCCodeGenInfo(RM, CM, OL);
202   return X;
203 }
204 
205 static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
206                                              unsigned SyntaxVariant,
207                                              const MCAsmInfo &MAI,
208                                              const MCInstrInfo &MII,
209                                              const MCRegisterInfo &MRI) {
210   if (SyntaxVariant == 0)
211     return new X86ATTInstPrinter(MAI, MII, MRI);
212   if (SyntaxVariant == 1)
213     return new X86IntelInstPrinter(MAI, MII, MRI);
214   return nullptr;
215 }
216 
217 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
218                                                    MCContext &Ctx) {
219   if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
220     return createX86_64MachORelocationInfo(Ctx);
221   else if (TheTriple.isOSBinFormatELF())
222     return createX86_64ELFRelocationInfo(Ctx);
223   // Default to the stock relocation info.
224   return llvm::createMCRelocationInfo(TheTriple, Ctx);
225 }
226 
227 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
228   return new MCInstrAnalysis(Info);
229 }
230 
231 // Force static initialization.
232 extern "C" void LLVMInitializeX86TargetMC() {
233   for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
234     // Register the MC asm info.
235     RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
236 
237     // Register the MC codegen info.
238     RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
239 
240     // Register the MC instruction info.
241     TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
242 
243     // Register the MC register info.
244     TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
245 
246     // Register the MC subtarget info.
247     TargetRegistry::RegisterMCSubtargetInfo(*T,
248                                             X86_MC::createX86MCSubtargetInfo);
249 
250     // Register the MC instruction analyzer.
251     TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
252 
253     // Register the code emitter.
254     TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
255 
256     // Register the object streamer.
257     TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
258 
259     // Register the MCInstPrinter.
260     TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
261 
262     // Register the MC relocation info.
263     TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
264   }
265 
266   // Register the asm backend.
267   TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
268                                        createX86_32AsmBackend);
269   TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
270                                        createX86_64AsmBackend);
271 }
272