1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86MCTargetDesc.h" 15 #include "InstPrinter/X86ATTInstPrinter.h" 16 #include "InstPrinter/X86IntelInstPrinter.h" 17 #include "X86MCAsmInfo.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCCodeGenInfo.h" 20 #include "llvm/MC/MCInstrAnalysis.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCStreamer.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/MachineLocation.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/Host.h" 28 #include "llvm/Support/TargetRegistry.h" 29 30 #if _MSC_VER 31 #include <intrin.h> 32 #endif 33 34 using namespace llvm; 35 36 #define GET_REGINFO_MC_DESC 37 #include "X86GenRegisterInfo.inc" 38 39 #define GET_INSTRINFO_MC_DESC 40 #include "X86GenInstrInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "X86GenSubtargetInfo.inc" 44 45 std::string X86_MC::ParseX86Triple(const Triple &TT) { 46 std::string FS; 47 if (TT.getArch() == Triple::x86_64) 48 FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 49 else if (TT.getEnvironment() != Triple::CODE16) 50 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 51 else 52 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 53 54 return FS; 55 } 56 57 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 58 if (TT.getArch() == Triple::x86_64) 59 return DWARFFlavour::X86_64; 60 61 if (TT.isOSDarwin()) 62 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 63 if (TT.isOSCygMing()) 64 // Unsupported by now, just quick fallback 65 return DWARFFlavour::X86_32_Generic; 66 return DWARFFlavour::X86_32_Generic; 67 } 68 69 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 70 // FIXME: TableGen these. 71 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 72 unsigned SEH = MRI->getEncodingValue(Reg); 73 MRI->mapLLVMRegToSEHReg(Reg, SEH); 74 } 75 76 // These CodeView registers are numbered sequentially starting at value 1. 77 static const MCPhysReg LowCVRegs[] = { 78 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, 79 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, 80 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, 81 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, 82 }; 83 unsigned CVLowRegStart = 1; 84 for (unsigned I = 0; I < array_lengthof(LowCVRegs); ++I) 85 MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); 86 87 // The x86 registers start at 128 and are numbered sequentially. 88 unsigned FP0Start = 128; 89 for (unsigned I = 0; I < 8; ++I) 90 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); 91 92 // The low 8 XMM registers start at 154 and are numbered sequentially. 93 unsigned CVXMM0Start = 154; 94 for (unsigned I = 0; I < 8; ++I) 95 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); 96 97 // The high 8 XMM registers start at 252 and are numbered sequentially. 98 unsigned CVXMM8Start = 252; 99 for (unsigned I = 0; I < 8; ++I) 100 MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); 101 102 // FIXME: XMM16 and above from AVX512 not yet documented. 103 104 // AMD64 registers start at 324 and count up. 105 unsigned CVX64RegStart = 324; 106 static const MCPhysReg CVX64Regs[] = { 107 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, 108 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, 109 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, 110 X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, 111 X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, 112 X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, 113 X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, 114 X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, 115 X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, 116 X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 117 }; 118 for (unsigned I = 0; I < array_lengthof(CVX64Regs); ++I) 119 MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); 120 } 121 122 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 123 StringRef CPU, StringRef FS) { 124 std::string ArchFS = X86_MC::ParseX86Triple(TT); 125 if (!FS.empty()) { 126 if (!ArchFS.empty()) 127 ArchFS = (Twine(ArchFS) + "," + FS).str(); 128 else 129 ArchFS = FS; 130 } 131 132 std::string CPUName = CPU; 133 if (CPUName.empty()) 134 CPUName = "generic"; 135 136 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); 137 } 138 139 static MCInstrInfo *createX86MCInstrInfo() { 140 MCInstrInfo *X = new MCInstrInfo(); 141 InitX86MCInstrInfo(X); 142 return X; 143 } 144 145 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 146 unsigned RA = (TT.getArch() == Triple::x86_64) 147 ? X86::RIP // Should have dwarf #16. 148 : X86::EIP; // Should have dwarf #8. 149 150 MCRegisterInfo *X = new MCRegisterInfo(); 151 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 152 X86_MC::getDwarfRegFlavour(TT, true), RA); 153 X86_MC::initLLVMToSEHAndCVRegMapping(X); 154 return X; 155 } 156 157 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 158 const Triple &TheTriple) { 159 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 160 161 MCAsmInfo *MAI; 162 if (TheTriple.isOSBinFormatMachO()) { 163 if (is64Bit) 164 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 165 else 166 MAI = new X86MCAsmInfoDarwin(TheTriple); 167 } else if (TheTriple.isOSBinFormatELF()) { 168 // Force the use of an ELF container. 169 MAI = new X86ELFMCAsmInfo(TheTriple); 170 } else if (TheTriple.isWindowsMSVCEnvironment() || 171 TheTriple.isWindowsCoreCLREnvironment()) { 172 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 173 } else if (TheTriple.isOSCygMing() || 174 TheTriple.isWindowsItaniumEnvironment()) { 175 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 176 } else { 177 // The default is ELF. 178 MAI = new X86ELFMCAsmInfo(TheTriple); 179 } 180 181 // Initialize initial frame state. 182 // Calculate amount of bytes used for return address storing 183 int stackGrowth = is64Bit ? -8 : -4; 184 185 // Initial state of the frame pointer is esp+stackGrowth. 186 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 187 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( 188 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 189 MAI->addInitialFrameState(Inst); 190 191 // Add return address to move list 192 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 193 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 194 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 195 MAI->addInitialFrameState(Inst2); 196 197 return MAI; 198 } 199 200 static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, 201 CodeModel::Model CM, 202 CodeGenOpt::Level OL) { 203 MCCodeGenInfo *X = new MCCodeGenInfo(); 204 205 bool is64Bit = TT.getArch() == Triple::x86_64; 206 207 if (RM == Reloc::Default) { 208 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 209 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 210 // use static relocation model by default. 211 if (TT.isOSDarwin()) { 212 if (is64Bit) 213 RM = Reloc::PIC_; 214 else 215 RM = Reloc::DynamicNoPIC; 216 } else if (TT.isOSWindows() && is64Bit) 217 RM = Reloc::PIC_; 218 else 219 RM = Reloc::Static; 220 } 221 222 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 223 // is defined as a model for code which may be used in static or dynamic 224 // executables but not necessarily a shared library. On X86-32 we just 225 // compile in -static mode, in x86-64 we use PIC. 226 if (RM == Reloc::DynamicNoPIC) { 227 if (is64Bit) 228 RM = Reloc::PIC_; 229 else if (!TT.isOSDarwin()) 230 RM = Reloc::Static; 231 } 232 233 // If we are on Darwin, disallow static relocation model in X86-64 mode, since 234 // the Mach-O file format doesn't support it. 235 if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit) 236 RM = Reloc::PIC_; 237 238 // For static codegen, if we're not already set, use Small codegen. 239 if (CM == CodeModel::Default) 240 CM = CodeModel::Small; 241 else if (CM == CodeModel::JITDefault) 242 // 64-bit JIT places everything in the same buffer except external funcs. 243 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 244 245 X->initMCCodeGenInfo(RM, CM, OL); 246 return X; 247 } 248 249 static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 250 unsigned SyntaxVariant, 251 const MCAsmInfo &MAI, 252 const MCInstrInfo &MII, 253 const MCRegisterInfo &MRI) { 254 if (SyntaxVariant == 0) 255 return new X86ATTInstPrinter(MAI, MII, MRI); 256 if (SyntaxVariant == 1) 257 return new X86IntelInstPrinter(MAI, MII, MRI); 258 return nullptr; 259 } 260 261 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 262 MCContext &Ctx) { 263 // Default to the stock relocation info. 264 return llvm::createMCRelocationInfo(TheTriple, Ctx); 265 } 266 267 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 268 return new MCInstrAnalysis(Info); 269 } 270 271 // Force static initialization. 272 extern "C" void LLVMInitializeX86TargetMC() { 273 for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { 274 // Register the MC asm info. 275 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 276 277 // Register the MC codegen info. 278 RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo); 279 280 // Register the MC instruction info. 281 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 282 283 // Register the MC register info. 284 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 285 286 // Register the MC subtarget info. 287 TargetRegistry::RegisterMCSubtargetInfo(*T, 288 X86_MC::createX86MCSubtargetInfo); 289 290 // Register the MC instruction analyzer. 291 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 292 293 // Register the code emitter. 294 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 295 296 // Register the object streamer. 297 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 298 299 // Register the MCInstPrinter. 300 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 301 302 // Register the MC relocation info. 303 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 304 } 305 306 // Register the asm backend. 307 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 308 createX86_32AsmBackend); 309 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 310 createX86_64AsmBackend); 311 } 312 313 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, 314 bool High) { 315 switch (Size) { 316 default: return 0; 317 case 8: 318 if (High) { 319 switch (Reg) { 320 default: return getX86SubSuperRegisterOrZero(Reg, 64); 321 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 322 return X86::SI; 323 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 324 return X86::DI; 325 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 326 return X86::BP; 327 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 328 return X86::SP; 329 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 330 return X86::AH; 331 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 332 return X86::DH; 333 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 334 return X86::CH; 335 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 336 return X86::BH; 337 } 338 } else { 339 switch (Reg) { 340 default: return 0; 341 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 342 return X86::AL; 343 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 344 return X86::DL; 345 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 346 return X86::CL; 347 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 348 return X86::BL; 349 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 350 return X86::SIL; 351 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 352 return X86::DIL; 353 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 354 return X86::BPL; 355 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 356 return X86::SPL; 357 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 358 return X86::R8B; 359 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 360 return X86::R9B; 361 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 362 return X86::R10B; 363 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 364 return X86::R11B; 365 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 366 return X86::R12B; 367 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 368 return X86::R13B; 369 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 370 return X86::R14B; 371 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 372 return X86::R15B; 373 } 374 } 375 case 16: 376 switch (Reg) { 377 default: return 0; 378 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 379 return X86::AX; 380 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 381 return X86::DX; 382 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 383 return X86::CX; 384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 385 return X86::BX; 386 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 387 return X86::SI; 388 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 389 return X86::DI; 390 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 391 return X86::BP; 392 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 393 return X86::SP; 394 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 395 return X86::R8W; 396 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 397 return X86::R9W; 398 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 399 return X86::R10W; 400 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 401 return X86::R11W; 402 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 403 return X86::R12W; 404 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 405 return X86::R13W; 406 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 407 return X86::R14W; 408 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 409 return X86::R15W; 410 } 411 case 32: 412 switch (Reg) { 413 default: return 0; 414 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 415 return X86::EAX; 416 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 417 return X86::EDX; 418 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 419 return X86::ECX; 420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 421 return X86::EBX; 422 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 423 return X86::ESI; 424 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 425 return X86::EDI; 426 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 427 return X86::EBP; 428 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 429 return X86::ESP; 430 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 431 return X86::R8D; 432 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 433 return X86::R9D; 434 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 435 return X86::R10D; 436 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 437 return X86::R11D; 438 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 439 return X86::R12D; 440 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 441 return X86::R13D; 442 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 443 return X86::R14D; 444 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 445 return X86::R15D; 446 } 447 case 64: 448 switch (Reg) { 449 default: return 0; 450 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 451 return X86::RAX; 452 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 453 return X86::RDX; 454 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 455 return X86::RCX; 456 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 457 return X86::RBX; 458 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 459 return X86::RSI; 460 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 461 return X86::RDI; 462 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 463 return X86::RBP; 464 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 465 return X86::RSP; 466 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 467 return X86::R8; 468 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 469 return X86::R9; 470 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 471 return X86::R10; 472 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 473 return X86::R11; 474 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 475 return X86::R12; 476 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 477 return X86::R13; 478 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 479 return X86::R14; 480 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 481 return X86::R15; 482 } 483 } 484 } 485 486 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { 487 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 488 assert(Res != 0 && "Unexpected register or VT"); 489 return Res; 490 } 491 492 493