1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86MCTargetDesc.h" 15 #include "InstPrinter/X86ATTInstPrinter.h" 16 #include "InstPrinter/X86IntelInstPrinter.h" 17 #include "X86MCAsmInfo.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCCodeGenInfo.h" 20 #include "llvm/MC/MCInstrAnalysis.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCStreamer.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/MachineLocation.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/Host.h" 28 #include "llvm/Support/TargetRegistry.h" 29 30 #define GET_REGINFO_MC_DESC 31 #include "X86GenRegisterInfo.inc" 32 33 #define GET_INSTRINFO_MC_DESC 34 #include "X86GenInstrInfo.inc" 35 36 #define GET_SUBTARGETINFO_MC_DESC 37 #include "X86GenSubtargetInfo.inc" 38 39 #if _MSC_VER 40 #include <intrin.h> 41 #endif 42 43 using namespace llvm; 44 45 46 std::string X86_MC::ParseX86Triple(StringRef TT) { 47 Triple TheTriple(TT); 48 std::string FS; 49 if (TheTriple.getArch() == Triple::x86_64) 50 FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 51 else if (TheTriple.getEnvironment() != Triple::CODE16) 52 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 53 else 54 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 55 56 return FS; 57 } 58 59 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 60 /// specified arguments. If we can't run cpuid on the host, return true. 61 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 62 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 63 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 64 #if defined(__GNUC__) 65 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 66 asm ("movq\t%%rbx, %%rsi\n\t" 67 "cpuid\n\t" 68 "xchgq\t%%rbx, %%rsi\n\t" 69 : "=a" (*rEAX), 70 "=S" (*rEBX), 71 "=c" (*rECX), 72 "=d" (*rEDX) 73 : "a" (value)); 74 return false; 75 #elif defined(_MSC_VER) 76 int registers[4]; 77 __cpuid(registers, value); 78 *rEAX = registers[0]; 79 *rEBX = registers[1]; 80 *rECX = registers[2]; 81 *rEDX = registers[3]; 82 return false; 83 #else 84 return true; 85 #endif 86 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 87 #if defined(__GNUC__) 88 asm ("movl\t%%ebx, %%esi\n\t" 89 "cpuid\n\t" 90 "xchgl\t%%ebx, %%esi\n\t" 91 : "=a" (*rEAX), 92 "=S" (*rEBX), 93 "=c" (*rECX), 94 "=d" (*rEDX) 95 : "a" (value)); 96 return false; 97 #elif defined(_MSC_VER) 98 __asm { 99 mov eax,value 100 cpuid 101 mov esi,rEAX 102 mov dword ptr [esi],eax 103 mov esi,rEBX 104 mov dword ptr [esi],ebx 105 mov esi,rECX 106 mov dword ptr [esi],ecx 107 mov esi,rEDX 108 mov dword ptr [esi],edx 109 } 110 return false; 111 #else 112 return true; 113 #endif 114 #else 115 return true; 116 #endif 117 } 118 119 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the 120 /// 4 values in the specified arguments. If we can't run cpuid on the host, 121 /// return true. 122 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 123 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { 124 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 125 #if defined(__GNUC__) 126 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually. 127 asm ("movq\t%%rbx, %%rsi\n\t" 128 "cpuid\n\t" 129 "xchgq\t%%rbx, %%rsi\n\t" 130 : "=a" (*rEAX), 131 "=S" (*rEBX), 132 "=c" (*rECX), 133 "=d" (*rEDX) 134 : "a" (value), 135 "c" (subleaf)); 136 return false; 137 #elif defined(_MSC_VER) 138 // __cpuidex was added in MSVC++ 9.0 SP1 139 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729) 140 int registers[4]; 141 __cpuidex(registers, value, subleaf); 142 *rEAX = registers[0]; 143 *rEBX = registers[1]; 144 *rECX = registers[2]; 145 *rEDX = registers[3]; 146 return false; 147 #else 148 return true; 149 #endif 150 #else 151 return true; 152 #endif 153 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 154 #if defined(__GNUC__) 155 asm ("movl\t%%ebx, %%esi\n\t" 156 "cpuid\n\t" 157 "xchgl\t%%ebx, %%esi\n\t" 158 : "=a" (*rEAX), 159 "=S" (*rEBX), 160 "=c" (*rECX), 161 "=d" (*rEDX) 162 : "a" (value), 163 "c" (subleaf)); 164 return false; 165 #elif defined(_MSC_VER) 166 __asm { 167 mov eax,value 168 mov ecx,subleaf 169 cpuid 170 mov esi,rEAX 171 mov dword ptr [esi],eax 172 mov esi,rEBX 173 mov dword ptr [esi],ebx 174 mov esi,rECX 175 mov dword ptr [esi],ecx 176 mov esi,rEDX 177 mov dword ptr [esi],edx 178 } 179 return false; 180 #else 181 return true; 182 #endif 183 #else 184 return true; 185 #endif 186 } 187 188 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family, 189 unsigned &Model) { 190 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 191 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 192 if (Family == 6 || Family == 0xf) { 193 if (Family == 0xf) 194 // Examine extended family ID if family ID is F. 195 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 196 // Examine extended model ID if family ID is 6 or F. 197 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 198 } 199 } 200 201 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) { 202 Triple TheTriple(TT); 203 if (TheTriple.getArch() == Triple::x86_64) 204 return DWARFFlavour::X86_64; 205 206 if (TheTriple.isOSDarwin()) 207 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 208 if (TheTriple.isOSCygMing()) 209 // Unsupported by now, just quick fallback 210 return DWARFFlavour::X86_32_Generic; 211 return DWARFFlavour::X86_32_Generic; 212 } 213 214 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { 215 // FIXME: TableGen these. 216 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 217 unsigned SEH = MRI->getEncodingValue(Reg); 218 MRI->mapLLVMRegToSEHReg(Reg, SEH); 219 } 220 } 221 222 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 223 StringRef FS) { 224 std::string ArchFS = X86_MC::ParseX86Triple(TT); 225 if (!FS.empty()) { 226 if (!ArchFS.empty()) 227 ArchFS = ArchFS + "," + FS.str(); 228 else 229 ArchFS = FS; 230 } 231 232 std::string CPUName = CPU; 233 if (CPUName.empty()) 234 CPUName = "generic"; 235 236 MCSubtargetInfo *X = new MCSubtargetInfo(); 237 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS); 238 return X; 239 } 240 241 static MCInstrInfo *createX86MCInstrInfo() { 242 MCInstrInfo *X = new MCInstrInfo(); 243 InitX86MCInstrInfo(X); 244 return X; 245 } 246 247 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) { 248 Triple TheTriple(TT); 249 unsigned RA = (TheTriple.getArch() == Triple::x86_64) 250 ? X86::RIP // Should have dwarf #16. 251 : X86::EIP; // Should have dwarf #8. 252 253 MCRegisterInfo *X = new MCRegisterInfo(); 254 InitX86MCRegisterInfo(X, RA, 255 X86_MC::getDwarfRegFlavour(TT, false), 256 X86_MC::getDwarfRegFlavour(TT, true), 257 RA); 258 X86_MC::InitLLVM2SEHRegisterMapping(X); 259 return X; 260 } 261 262 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { 263 Triple TheTriple(TT); 264 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 265 266 MCAsmInfo *MAI; 267 if (TheTriple.isOSBinFormatMachO()) { 268 if (is64Bit) 269 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 270 else 271 MAI = new X86MCAsmInfoDarwin(TheTriple); 272 } else if (TheTriple.isOSBinFormatELF()) { 273 // Force the use of an ELF container. 274 MAI = new X86ELFMCAsmInfo(TheTriple); 275 } else if (TheTriple.isWindowsMSVCEnvironment()) { 276 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 277 } else if (TheTriple.isOSCygMing()) { 278 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 279 } else { 280 // The default is ELF. 281 MAI = new X86ELFMCAsmInfo(TheTriple); 282 } 283 284 // Initialize initial frame state. 285 // Calculate amount of bytes used for return address storing 286 int stackGrowth = is64Bit ? -8 : -4; 287 288 // Initial state of the frame pointer is esp+stackGrowth. 289 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 290 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( 291 0, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 292 MAI->addInitialFrameState(Inst); 293 294 // Add return address to move list 295 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 296 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 297 0, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 298 MAI->addInitialFrameState(Inst2); 299 300 return MAI; 301 } 302 303 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM, 304 CodeModel::Model CM, 305 CodeGenOpt::Level OL) { 306 MCCodeGenInfo *X = new MCCodeGenInfo(); 307 308 Triple T(TT); 309 bool is64Bit = T.getArch() == Triple::x86_64; 310 311 if (RM == Reloc::Default) { 312 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 313 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 314 // use static relocation model by default. 315 if (T.isOSDarwin()) { 316 if (is64Bit) 317 RM = Reloc::PIC_; 318 else 319 RM = Reloc::DynamicNoPIC; 320 } else if (T.isOSWindows() && is64Bit) 321 RM = Reloc::PIC_; 322 else 323 RM = Reloc::Static; 324 } 325 326 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 327 // is defined as a model for code which may be used in static or dynamic 328 // executables but not necessarily a shared library. On X86-32 we just 329 // compile in -static mode, in x86-64 we use PIC. 330 if (RM == Reloc::DynamicNoPIC) { 331 if (is64Bit) 332 RM = Reloc::PIC_; 333 else if (!T.isOSDarwin()) 334 RM = Reloc::Static; 335 } 336 337 // If we are on Darwin, disallow static relocation model in X86-64 mode, since 338 // the Mach-O file format doesn't support it. 339 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit) 340 RM = Reloc::PIC_; 341 342 // For static codegen, if we're not already set, use Small codegen. 343 if (CM == CodeModel::Default) 344 CM = CodeModel::Small; 345 else if (CM == CodeModel::JITDefault) 346 // 64-bit JIT places everything in the same buffer except external funcs. 347 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 348 349 X->InitMCCodeGenInfo(RM, CM, OL); 350 return X; 351 } 352 353 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 354 MCContext &Ctx, MCAsmBackend &MAB, 355 raw_ostream &_OS, 356 MCCodeEmitter *_Emitter, 357 const MCSubtargetInfo &STI, 358 bool RelaxAll, 359 bool NoExecStack) { 360 Triple TheTriple(TT); 361 362 if (TheTriple.isOSBinFormatMachO()) 363 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll); 364 365 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) 366 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll); 367 368 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack); 369 } 370 371 static MCInstPrinter *createX86MCInstPrinter(const Target &T, 372 unsigned SyntaxVariant, 373 const MCAsmInfo &MAI, 374 const MCInstrInfo &MII, 375 const MCRegisterInfo &MRI, 376 const MCSubtargetInfo &STI) { 377 if (SyntaxVariant == 0) 378 return new X86ATTInstPrinter(MAI, MII, MRI); 379 if (SyntaxVariant == 1) 380 return new X86IntelInstPrinter(MAI, MII, MRI); 381 return 0; 382 } 383 384 static MCRelocationInfo *createX86MCRelocationInfo(StringRef TT, 385 MCContext &Ctx) { 386 Triple TheTriple(TT); 387 if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64) 388 return createX86_64MachORelocationInfo(Ctx); 389 else if (TheTriple.isOSBinFormatELF()) 390 return createX86_64ELFRelocationInfo(Ctx); 391 // Default to the stock relocation info. 392 return llvm::createMCRelocationInfo(TT, Ctx); 393 } 394 395 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 396 return new MCInstrAnalysis(Info); 397 } 398 399 // Force static initialization. 400 extern "C" void LLVMInitializeX86TargetMC() { 401 // Register the MC asm info. 402 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo); 403 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo); 404 405 // Register the MC codegen info. 406 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo); 407 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo); 408 409 // Register the MC instruction info. 410 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo); 411 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo); 412 413 // Register the MC register info. 414 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); 415 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); 416 417 // Register the MC subtarget info. 418 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, 419 X86_MC::createX86MCSubtargetInfo); 420 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, 421 X86_MC::createX86MCSubtargetInfo); 422 423 // Register the MC instruction analyzer. 424 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target, 425 createX86MCInstrAnalysis); 426 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target, 427 createX86MCInstrAnalysis); 428 429 // Register the code emitter. 430 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target, 431 createX86MCCodeEmitter); 432 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target, 433 createX86MCCodeEmitter); 434 435 // Register the asm backend. 436 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 437 createX86_32AsmBackend); 438 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 439 createX86_64AsmBackend); 440 441 // Register the object streamer. 442 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target, 443 createMCStreamer); 444 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target, 445 createMCStreamer); 446 447 // Register the MCInstPrinter. 448 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target, 449 createX86MCInstPrinter); 450 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target, 451 createX86MCInstPrinter); 452 453 // Register the MC relocation info. 454 TargetRegistry::RegisterMCRelocationInfo(TheX86_32Target, 455 createX86MCRelocationInfo); 456 TargetRegistry::RegisterMCRelocationInfo(TheX86_64Target, 457 createX86MCRelocationInfo); 458 } 459