1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/X86BaseInfo.h" 11 #include "MCTargetDesc/X86FixupKinds.h" 12 #include "llvm/ADT/StringSwitch.h" 13 #include "llvm/BinaryFormat/ELF.h" 14 #include "llvm/BinaryFormat/MachO.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCELFObjectWriter.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixupKindInfo.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCMachObjectWriter.h" 21 #include "llvm/MC/MCObjectWriter.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSectionMachO.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/raw_ostream.h" 27 using namespace llvm; 28 29 static unsigned getFixupKindLog2Size(unsigned Kind) { 30 switch (Kind) { 31 default: 32 llvm_unreachable("invalid fixup kind!"); 33 case FK_PCRel_1: 34 case FK_SecRel_1: 35 case FK_Data_1: 36 return 0; 37 case FK_PCRel_2: 38 case FK_SecRel_2: 39 case FK_Data_2: 40 return 1; 41 case FK_PCRel_4: 42 case X86::reloc_riprel_4byte: 43 case X86::reloc_riprel_4byte_relax: 44 case X86::reloc_riprel_4byte_relax_rex: 45 case X86::reloc_riprel_4byte_movq_load: 46 case X86::reloc_signed_4byte: 47 case X86::reloc_signed_4byte_relax: 48 case X86::reloc_global_offset_table: 49 case FK_SecRel_4: 50 case FK_Data_4: 51 return 2; 52 case FK_PCRel_8: 53 case FK_SecRel_8: 54 case FK_Data_8: 55 case X86::reloc_global_offset_table8: 56 return 3; 57 } 58 } 59 60 namespace { 61 62 class X86ELFObjectWriter : public MCELFObjectTargetWriter { 63 public: 64 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine, 65 bool HasRelocationAddend, bool foobar) 66 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {} 67 }; 68 69 class X86AsmBackend : public MCAsmBackend { 70 const MCSubtargetInfo &STI; 71 public: 72 X86AsmBackend(const Target &T, const MCSubtargetInfo &STI) 73 : MCAsmBackend(), STI(STI) {} 74 75 unsigned getNumFixupKinds() const override { 76 return X86::NumTargetFixupKinds; 77 } 78 79 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 80 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { 81 {"reloc_riprel_4byte", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 82 {"reloc_riprel_4byte_movq_load", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 83 {"reloc_riprel_4byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 84 {"reloc_riprel_4byte_relax_rex", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 85 {"reloc_signed_4byte", 0, 32, 0}, 86 {"reloc_signed_4byte_relax", 0, 32, 0}, 87 {"reloc_global_offset_table", 0, 32, 0}, 88 {"reloc_global_offset_table8", 0, 64, 0}, 89 }; 90 91 if (Kind < FirstTargetFixupKind) 92 return MCAsmBackend::getFixupKindInfo(Kind); 93 94 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 95 "Invalid kind!"); 96 return Infos[Kind - FirstTargetFixupKind]; 97 } 98 99 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 100 const MCValue &Target, MutableArrayRef<char> Data, 101 uint64_t Value, bool IsResolved) const override { 102 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); 103 104 assert(Fixup.getOffset() + Size <= Data.size() && "Invalid fixup offset!"); 105 106 // Check that uppper bits are either all zeros or all ones. 107 // Specifically ignore overflow/underflow as long as the leakage is 108 // limited to the lower bits. This is to remain compatible with 109 // other assemblers. 110 assert(isIntN(Size * 8 + 1, Value) && 111 "Value does not fit in the Fixup field"); 112 113 for (unsigned i = 0; i != Size; ++i) 114 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); 115 } 116 117 bool mayNeedRelaxation(const MCInst &Inst) const override; 118 119 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 120 const MCRelaxableFragment *DF, 121 const MCAsmLayout &Layout) const override; 122 123 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 124 MCInst &Res) const override; 125 126 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 127 }; 128 } // end anonymous namespace 129 130 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) { 131 unsigned Op = Inst.getOpcode(); 132 switch (Op) { 133 default: 134 return Op; 135 case X86::JAE_1: 136 return (is16BitMode) ? X86::JAE_2 : X86::JAE_4; 137 case X86::JA_1: 138 return (is16BitMode) ? X86::JA_2 : X86::JA_4; 139 case X86::JBE_1: 140 return (is16BitMode) ? X86::JBE_2 : X86::JBE_4; 141 case X86::JB_1: 142 return (is16BitMode) ? X86::JB_2 : X86::JB_4; 143 case X86::JE_1: 144 return (is16BitMode) ? X86::JE_2 : X86::JE_4; 145 case X86::JGE_1: 146 return (is16BitMode) ? X86::JGE_2 : X86::JGE_4; 147 case X86::JG_1: 148 return (is16BitMode) ? X86::JG_2 : X86::JG_4; 149 case X86::JLE_1: 150 return (is16BitMode) ? X86::JLE_2 : X86::JLE_4; 151 case X86::JL_1: 152 return (is16BitMode) ? X86::JL_2 : X86::JL_4; 153 case X86::JMP_1: 154 return (is16BitMode) ? X86::JMP_2 : X86::JMP_4; 155 case X86::JNE_1: 156 return (is16BitMode) ? X86::JNE_2 : X86::JNE_4; 157 case X86::JNO_1: 158 return (is16BitMode) ? X86::JNO_2 : X86::JNO_4; 159 case X86::JNP_1: 160 return (is16BitMode) ? X86::JNP_2 : X86::JNP_4; 161 case X86::JNS_1: 162 return (is16BitMode) ? X86::JNS_2 : X86::JNS_4; 163 case X86::JO_1: 164 return (is16BitMode) ? X86::JO_2 : X86::JO_4; 165 case X86::JP_1: 166 return (is16BitMode) ? X86::JP_2 : X86::JP_4; 167 case X86::JS_1: 168 return (is16BitMode) ? X86::JS_2 : X86::JS_4; 169 } 170 } 171 172 static unsigned getRelaxedOpcodeArith(const MCInst &Inst) { 173 unsigned Op = Inst.getOpcode(); 174 switch (Op) { 175 default: 176 return Op; 177 178 // IMUL 179 case X86::IMUL16rri8: return X86::IMUL16rri; 180 case X86::IMUL16rmi8: return X86::IMUL16rmi; 181 case X86::IMUL32rri8: return X86::IMUL32rri; 182 case X86::IMUL32rmi8: return X86::IMUL32rmi; 183 case X86::IMUL64rri8: return X86::IMUL64rri32; 184 case X86::IMUL64rmi8: return X86::IMUL64rmi32; 185 186 // AND 187 case X86::AND16ri8: return X86::AND16ri; 188 case X86::AND16mi8: return X86::AND16mi; 189 case X86::AND32ri8: return X86::AND32ri; 190 case X86::AND32mi8: return X86::AND32mi; 191 case X86::AND64ri8: return X86::AND64ri32; 192 case X86::AND64mi8: return X86::AND64mi32; 193 194 // OR 195 case X86::OR16ri8: return X86::OR16ri; 196 case X86::OR16mi8: return X86::OR16mi; 197 case X86::OR32ri8: return X86::OR32ri; 198 case X86::OR32mi8: return X86::OR32mi; 199 case X86::OR64ri8: return X86::OR64ri32; 200 case X86::OR64mi8: return X86::OR64mi32; 201 202 // XOR 203 case X86::XOR16ri8: return X86::XOR16ri; 204 case X86::XOR16mi8: return X86::XOR16mi; 205 case X86::XOR32ri8: return X86::XOR32ri; 206 case X86::XOR32mi8: return X86::XOR32mi; 207 case X86::XOR64ri8: return X86::XOR64ri32; 208 case X86::XOR64mi8: return X86::XOR64mi32; 209 210 // ADD 211 case X86::ADD16ri8: return X86::ADD16ri; 212 case X86::ADD16mi8: return X86::ADD16mi; 213 case X86::ADD32ri8: return X86::ADD32ri; 214 case X86::ADD32mi8: return X86::ADD32mi; 215 case X86::ADD64ri8: return X86::ADD64ri32; 216 case X86::ADD64mi8: return X86::ADD64mi32; 217 218 // ADC 219 case X86::ADC16ri8: return X86::ADC16ri; 220 case X86::ADC16mi8: return X86::ADC16mi; 221 case X86::ADC32ri8: return X86::ADC32ri; 222 case X86::ADC32mi8: return X86::ADC32mi; 223 case X86::ADC64ri8: return X86::ADC64ri32; 224 case X86::ADC64mi8: return X86::ADC64mi32; 225 226 // SUB 227 case X86::SUB16ri8: return X86::SUB16ri; 228 case X86::SUB16mi8: return X86::SUB16mi; 229 case X86::SUB32ri8: return X86::SUB32ri; 230 case X86::SUB32mi8: return X86::SUB32mi; 231 case X86::SUB64ri8: return X86::SUB64ri32; 232 case X86::SUB64mi8: return X86::SUB64mi32; 233 234 // SBB 235 case X86::SBB16ri8: return X86::SBB16ri; 236 case X86::SBB16mi8: return X86::SBB16mi; 237 case X86::SBB32ri8: return X86::SBB32ri; 238 case X86::SBB32mi8: return X86::SBB32mi; 239 case X86::SBB64ri8: return X86::SBB64ri32; 240 case X86::SBB64mi8: return X86::SBB64mi32; 241 242 // CMP 243 case X86::CMP16ri8: return X86::CMP16ri; 244 case X86::CMP16mi8: return X86::CMP16mi; 245 case X86::CMP32ri8: return X86::CMP32ri; 246 case X86::CMP32mi8: return X86::CMP32mi; 247 case X86::CMP64ri8: return X86::CMP64ri32; 248 case X86::CMP64mi8: return X86::CMP64mi32; 249 250 // PUSH 251 case X86::PUSH32i8: return X86::PUSHi32; 252 case X86::PUSH16i8: return X86::PUSHi16; 253 case X86::PUSH64i8: return X86::PUSH64i32; 254 } 255 } 256 257 static unsigned getRelaxedOpcode(const MCInst &Inst, bool is16BitMode) { 258 unsigned R = getRelaxedOpcodeArith(Inst); 259 if (R != Inst.getOpcode()) 260 return R; 261 return getRelaxedOpcodeBranch(Inst, is16BitMode); 262 } 263 264 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 265 // Branches can always be relaxed in either mode. 266 if (getRelaxedOpcodeBranch(Inst, false) != Inst.getOpcode()) 267 return true; 268 269 // Check if this instruction is ever relaxable. 270 if (getRelaxedOpcodeArith(Inst) == Inst.getOpcode()) 271 return false; 272 273 274 // Check if the relaxable operand has an expression. For the current set of 275 // relaxable instructions, the relaxable operand is always the last operand. 276 unsigned RelaxableOp = Inst.getNumOperands() - 1; 277 if (Inst.getOperand(RelaxableOp).isExpr()) 278 return true; 279 280 return false; 281 } 282 283 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 284 uint64_t Value, 285 const MCRelaxableFragment *DF, 286 const MCAsmLayout &Layout) const { 287 // Relax if the value is too big for a (signed) i8. 288 return int64_t(Value) != int64_t(int8_t(Value)); 289 } 290 291 // FIXME: Can tblgen help at all here to verify there aren't other instructions 292 // we can relax? 293 void X86AsmBackend::relaxInstruction(const MCInst &Inst, 294 const MCSubtargetInfo &STI, 295 MCInst &Res) const { 296 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. 297 bool is16BitMode = STI.getFeatureBits()[X86::Mode16Bit]; 298 unsigned RelaxedOp = getRelaxedOpcode(Inst, is16BitMode); 299 300 if (RelaxedOp == Inst.getOpcode()) { 301 SmallString<256> Tmp; 302 raw_svector_ostream OS(Tmp); 303 Inst.dump_pretty(OS); 304 OS << "\n"; 305 report_fatal_error("unexpected instruction to relax: " + OS.str()); 306 } 307 308 Res = Inst; 309 Res.setOpcode(RelaxedOp); 310 } 311 312 /// \brief Write a sequence of optimal nops to the output, covering \p Count 313 /// bytes. 314 /// \return - true on success, false on failure 315 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 316 static const uint8_t Nops[10][10] = { 317 // nop 318 {0x90}, 319 // xchg %ax,%ax 320 {0x66, 0x90}, 321 // nopl (%[re]ax) 322 {0x0f, 0x1f, 0x00}, 323 // nopl 0(%[re]ax) 324 {0x0f, 0x1f, 0x40, 0x00}, 325 // nopl 0(%[re]ax,%[re]ax,1) 326 {0x0f, 0x1f, 0x44, 0x00, 0x00}, 327 // nopw 0(%[re]ax,%[re]ax,1) 328 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00}, 329 // nopl 0L(%[re]ax) 330 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00}, 331 // nopl 0L(%[re]ax,%[re]ax,1) 332 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 333 // nopw 0L(%[re]ax,%[re]ax,1) 334 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 335 // nopw %cs:0L(%[re]ax,%[re]ax,1) 336 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 337 }; 338 339 // This CPU doesn't support long nops. If needed add more. 340 // FIXME: We could generated something better than plain 0x90. 341 if (!STI.getFeatureBits()[X86::FeatureNOPL]) { 342 for (uint64_t i = 0; i < Count; ++i) 343 OW->write8(0x90); 344 return true; 345 } 346 347 uint64_t MaxNopLength = STI.getFeatureBits()[X86::ProcIntelSLM] ? 7 : 15; 348 349 // 15 is the longest single nop instruction. Emit as many 15-byte nops as 350 // needed, then emit a nop of the remaining length. 351 do { 352 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength); 353 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10; 354 for (uint8_t i = 0; i < Prefixes; i++) 355 OW->write8(0x66); 356 const uint8_t Rest = ThisNopLength - Prefixes; 357 for (uint8_t i = 0; i < Rest; i++) 358 OW->write8(Nops[Rest - 1][i]); 359 Count -= ThisNopLength; 360 } while (Count != 0); 361 362 return true; 363 } 364 365 /* *** */ 366 367 namespace { 368 369 class ELFX86AsmBackend : public X86AsmBackend { 370 public: 371 uint8_t OSABI; 372 ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI) 373 : X86AsmBackend(T, STI), OSABI(OSABI) {} 374 }; 375 376 class ELFX86_32AsmBackend : public ELFX86AsmBackend { 377 public: 378 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, 379 const MCSubtargetInfo &STI) 380 : ELFX86AsmBackend(T, OSABI, STI) {} 381 382 std::unique_ptr<MCObjectWriter> 383 createObjectWriter(raw_pwrite_stream &OS) const override { 384 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386); 385 } 386 }; 387 388 class ELFX86_X32AsmBackend : public ELFX86AsmBackend { 389 public: 390 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, 391 const MCSubtargetInfo &STI) 392 : ELFX86AsmBackend(T, OSABI, STI) {} 393 394 std::unique_ptr<MCObjectWriter> 395 createObjectWriter(raw_pwrite_stream &OS) const override { 396 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, 397 ELF::EM_X86_64); 398 } 399 }; 400 401 class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend { 402 public: 403 ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, 404 const MCSubtargetInfo &STI) 405 : ELFX86AsmBackend(T, OSABI, STI) {} 406 407 std::unique_ptr<MCObjectWriter> 408 createObjectWriter(raw_pwrite_stream &OS) const override { 409 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, 410 ELF::EM_IAMCU); 411 } 412 }; 413 414 class ELFX86_64AsmBackend : public ELFX86AsmBackend { 415 public: 416 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, 417 const MCSubtargetInfo &STI) 418 : ELFX86AsmBackend(T, OSABI, STI) {} 419 420 std::unique_ptr<MCObjectWriter> 421 createObjectWriter(raw_pwrite_stream &OS) const override { 422 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64); 423 } 424 }; 425 426 class WindowsX86AsmBackend : public X86AsmBackend { 427 bool Is64Bit; 428 429 public: 430 WindowsX86AsmBackend(const Target &T, bool is64Bit, 431 const MCSubtargetInfo &STI) 432 : X86AsmBackend(T, STI) 433 , Is64Bit(is64Bit) { 434 } 435 436 Optional<MCFixupKind> getFixupKind(StringRef Name) const override { 437 return StringSwitch<Optional<MCFixupKind>>(Name) 438 .Case("dir32", FK_Data_4) 439 .Case("secrel32", FK_SecRel_4) 440 .Case("secidx", FK_SecRel_2) 441 .Default(MCAsmBackend::getFixupKind(Name)); 442 } 443 444 std::unique_ptr<MCObjectWriter> 445 createObjectWriter(raw_pwrite_stream &OS) const override { 446 return createX86WinCOFFObjectWriter(OS, Is64Bit); 447 } 448 }; 449 450 namespace CU { 451 452 /// Compact unwind encoding values. 453 enum CompactUnwindEncodings { 454 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after 455 /// the return address, then [RE]SP is moved to [RE]BP. 456 UNWIND_MODE_BP_FRAME = 0x01000000, 457 458 /// A frameless function with a small constant stack size. 459 UNWIND_MODE_STACK_IMMD = 0x02000000, 460 461 /// A frameless function with a large constant stack size. 462 UNWIND_MODE_STACK_IND = 0x03000000, 463 464 /// No compact unwind encoding is available. 465 UNWIND_MODE_DWARF = 0x04000000, 466 467 /// Mask for encoding the frame registers. 468 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF, 469 470 /// Mask for encoding the frameless registers. 471 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF 472 }; 473 474 } // end CU namespace 475 476 class DarwinX86AsmBackend : public X86AsmBackend { 477 const MCRegisterInfo &MRI; 478 479 /// \brief Number of registers that can be saved in a compact unwind encoding. 480 enum { CU_NUM_SAVED_REGS = 6 }; 481 482 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS]; 483 bool Is64Bit; 484 485 unsigned OffsetSize; ///< Offset of a "push" instruction. 486 unsigned MoveInstrSize; ///< Size of a "move" instruction. 487 unsigned StackDivide; ///< Amount to adjust stack size by. 488 protected: 489 /// \brief Size of a "push" instruction for the given register. 490 unsigned PushInstrSize(unsigned Reg) const { 491 switch (Reg) { 492 case X86::EBX: 493 case X86::ECX: 494 case X86::EDX: 495 case X86::EDI: 496 case X86::ESI: 497 case X86::EBP: 498 case X86::RBX: 499 case X86::RBP: 500 return 1; 501 case X86::R12: 502 case X86::R13: 503 case X86::R14: 504 case X86::R15: 505 return 2; 506 } 507 return 1; 508 } 509 510 /// \brief Implementation of algorithm to generate the compact unwind encoding 511 /// for the CFI instructions. 512 uint32_t 513 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const { 514 if (Instrs.empty()) return 0; 515 516 // Reset the saved registers. 517 unsigned SavedRegIdx = 0; 518 memset(SavedRegs, 0, sizeof(SavedRegs)); 519 520 bool HasFP = false; 521 522 // Encode that we are using EBP/RBP as the frame pointer. 523 uint32_t CompactUnwindEncoding = 0; 524 525 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2; 526 unsigned InstrOffset = 0; 527 unsigned StackAdjust = 0; 528 unsigned StackSize = 0; 529 unsigned PrevStackSize = 0; 530 unsigned NumDefCFAOffsets = 0; 531 532 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) { 533 const MCCFIInstruction &Inst = Instrs[i]; 534 535 switch (Inst.getOperation()) { 536 default: 537 // Any other CFI directives indicate a frame that we aren't prepared 538 // to represent via compact unwind, so just bail out. 539 return 0; 540 case MCCFIInstruction::OpDefCfaRegister: { 541 // Defines a frame pointer. E.g. 542 // 543 // movq %rsp, %rbp 544 // L0: 545 // .cfi_def_cfa_register %rbp 546 // 547 HasFP = true; 548 549 // If the frame pointer is other than esp/rsp, we do not have a way to 550 // generate a compact unwinding representation, so bail out. 551 if (MRI.getLLVMRegNum(Inst.getRegister(), true) != 552 (Is64Bit ? X86::RBP : X86::EBP)) 553 return 0; 554 555 // Reset the counts. 556 memset(SavedRegs, 0, sizeof(SavedRegs)); 557 StackAdjust = 0; 558 SavedRegIdx = 0; 559 InstrOffset += MoveInstrSize; 560 break; 561 } 562 case MCCFIInstruction::OpDefCfaOffset: { 563 // Defines a new offset for the CFA. E.g. 564 // 565 // With frame: 566 // 567 // pushq %rbp 568 // L0: 569 // .cfi_def_cfa_offset 16 570 // 571 // Without frame: 572 // 573 // subq $72, %rsp 574 // L0: 575 // .cfi_def_cfa_offset 80 576 // 577 PrevStackSize = StackSize; 578 StackSize = std::abs(Inst.getOffset()) / StackDivide; 579 ++NumDefCFAOffsets; 580 break; 581 } 582 case MCCFIInstruction::OpOffset: { 583 // Defines a "push" of a callee-saved register. E.g. 584 // 585 // pushq %r15 586 // pushq %r14 587 // pushq %rbx 588 // L0: 589 // subq $120, %rsp 590 // L1: 591 // .cfi_offset %rbx, -40 592 // .cfi_offset %r14, -32 593 // .cfi_offset %r15, -24 594 // 595 if (SavedRegIdx == CU_NUM_SAVED_REGS) 596 // If there are too many saved registers, we cannot use a compact 597 // unwind encoding. 598 return CU::UNWIND_MODE_DWARF; 599 600 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 601 SavedRegs[SavedRegIdx++] = Reg; 602 StackAdjust += OffsetSize; 603 InstrOffset += PushInstrSize(Reg); 604 break; 605 } 606 } 607 } 608 609 StackAdjust /= StackDivide; 610 611 if (HasFP) { 612 if ((StackAdjust & 0xFF) != StackAdjust) 613 // Offset was too big for a compact unwind encoding. 614 return CU::UNWIND_MODE_DWARF; 615 616 // Get the encoding of the saved registers when we have a frame pointer. 617 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(); 618 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 619 620 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME; 621 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16; 622 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS; 623 } else { 624 // If the amount of the stack allocation is the size of a register, then 625 // we "push" the RAX/EAX register onto the stack instead of adjusting the 626 // stack pointer with a SUB instruction. We don't support the push of the 627 // RAX/EAX register with compact unwind. So we check for that situation 628 // here. 629 if ((NumDefCFAOffsets == SavedRegIdx + 1 && 630 StackSize - PrevStackSize == 1) || 631 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2)) 632 return CU::UNWIND_MODE_DWARF; 633 634 SubtractInstrIdx += InstrOffset; 635 ++StackAdjust; 636 637 if ((StackSize & 0xFF) == StackSize) { 638 // Frameless stack with a small stack size. 639 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD; 640 641 // Encode the stack size. 642 CompactUnwindEncoding |= (StackSize & 0xFF) << 16; 643 } else { 644 if ((StackAdjust & 0x7) != StackAdjust) 645 // The extra stack adjustments are too big for us to handle. 646 return CU::UNWIND_MODE_DWARF; 647 648 // Frameless stack with an offset too large for us to encode compactly. 649 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND; 650 651 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' 652 // instruction. 653 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; 654 655 // Encode any extra stack stack adjustments (done via push 656 // instructions). 657 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13; 658 } 659 660 // Encode the number of registers saved. (Reverse the list first.) 661 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]); 662 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10; 663 664 // Get the encoding of the saved registers when we don't have a frame 665 // pointer. 666 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx); 667 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 668 669 // Encode the register encoding. 670 CompactUnwindEncoding |= 671 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION; 672 } 673 674 return CompactUnwindEncoding; 675 } 676 677 private: 678 /// \brief Get the compact unwind number for a given register. The number 679 /// corresponds to the enum lists in compact_unwind_encoding.h. 680 int getCompactUnwindRegNum(unsigned Reg) const { 681 static const MCPhysReg CU32BitRegs[7] = { 682 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 683 }; 684 static const MCPhysReg CU64BitRegs[] = { 685 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 686 }; 687 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs; 688 for (int Idx = 1; *CURegs; ++CURegs, ++Idx) 689 if (*CURegs == Reg) 690 return Idx; 691 692 return -1; 693 } 694 695 /// \brief Return the registers encoded for a compact encoding with a frame 696 /// pointer. 697 uint32_t encodeCompactUnwindRegistersWithFrame() const { 698 // Encode the registers in the order they were saved --- 3-bits per 699 // register. The list of saved registers is assumed to be in reverse 700 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS. 701 uint32_t RegEnc = 0; 702 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) { 703 unsigned Reg = SavedRegs[i]; 704 if (Reg == 0) break; 705 706 int CURegNum = getCompactUnwindRegNum(Reg); 707 if (CURegNum == -1) return ~0U; 708 709 // Encode the 3-bit register number in order, skipping over 3-bits for 710 // each register. 711 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3); 712 } 713 714 assert((RegEnc & 0x3FFFF) == RegEnc && 715 "Invalid compact register encoding!"); 716 return RegEnc; 717 } 718 719 /// \brief Create the permutation encoding used with frameless stacks. It is 720 /// passed the number of registers to be saved and an array of the registers 721 /// saved. 722 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const { 723 // The saved registers are numbered from 1 to 6. In order to encode the 724 // order in which they were saved, we re-number them according to their 725 // place in the register order. The re-numbering is relative to the last 726 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in 727 // that order: 728 // 729 // Orig Re-Num 730 // ---- ------ 731 // 6 6 732 // 2 2 733 // 4 3 734 // 5 3 735 // 736 for (unsigned i = 0; i < RegCount; ++i) { 737 int CUReg = getCompactUnwindRegNum(SavedRegs[i]); 738 if (CUReg == -1) return ~0U; 739 SavedRegs[i] = CUReg; 740 } 741 742 // Reverse the list. 743 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]); 744 745 uint32_t RenumRegs[CU_NUM_SAVED_REGS]; 746 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){ 747 unsigned Countless = 0; 748 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j) 749 if (SavedRegs[j] < SavedRegs[i]) 750 ++Countless; 751 752 RenumRegs[i] = SavedRegs[i] - Countless - 1; 753 } 754 755 // Take the renumbered values and encode them into a 10-bit number. 756 uint32_t permutationEncoding = 0; 757 switch (RegCount) { 758 case 6: 759 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] 760 + 6 * RenumRegs[2] + 2 * RenumRegs[3] 761 + RenumRegs[4]; 762 break; 763 case 5: 764 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] 765 + 6 * RenumRegs[3] + 2 * RenumRegs[4] 766 + RenumRegs[5]; 767 break; 768 case 4: 769 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] 770 + 3 * RenumRegs[4] + RenumRegs[5]; 771 break; 772 case 3: 773 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] 774 + RenumRegs[5]; 775 break; 776 case 2: 777 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; 778 break; 779 case 1: 780 permutationEncoding |= RenumRegs[5]; 781 break; 782 } 783 784 assert((permutationEncoding & 0x3FF) == permutationEncoding && 785 "Invalid compact register encoding!"); 786 return permutationEncoding; 787 } 788 789 public: 790 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, 791 const MCSubtargetInfo &STI, bool Is64Bit) 792 : X86AsmBackend(T, STI), MRI(MRI), Is64Bit(Is64Bit) { 793 memset(SavedRegs, 0, sizeof(SavedRegs)); 794 OffsetSize = Is64Bit ? 8 : 4; 795 MoveInstrSize = Is64Bit ? 3 : 2; 796 StackDivide = Is64Bit ? 8 : 4; 797 } 798 }; 799 800 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { 801 public: 802 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, 803 const MCSubtargetInfo &STI) 804 : DarwinX86AsmBackend(T, MRI, STI, false) {} 805 806 std::unique_ptr<MCObjectWriter> 807 createObjectWriter(raw_pwrite_stream &OS) const override { 808 return createX86MachObjectWriter(OS, /*Is64Bit=*/false, 809 MachO::CPU_TYPE_I386, 810 MachO::CPU_SUBTYPE_I386_ALL); 811 } 812 813 /// \brief Generate the compact unwind encoding for the CFI instructions. 814 uint32_t generateCompactUnwindEncoding( 815 ArrayRef<MCCFIInstruction> Instrs) const override { 816 return generateCompactUnwindEncodingImpl(Instrs); 817 } 818 }; 819 820 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { 821 const MachO::CPUSubTypeX86 Subtype; 822 public: 823 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, 824 const MCSubtargetInfo &STI, MachO::CPUSubTypeX86 st) 825 : DarwinX86AsmBackend(T, MRI, STI, true), Subtype(st) {} 826 827 std::unique_ptr<MCObjectWriter> 828 createObjectWriter(raw_pwrite_stream &OS) const override { 829 return createX86MachObjectWriter(OS, /*Is64Bit=*/true, 830 MachO::CPU_TYPE_X86_64, Subtype); 831 } 832 833 /// \brief Generate the compact unwind encoding for the CFI instructions. 834 uint32_t generateCompactUnwindEncoding( 835 ArrayRef<MCCFIInstruction> Instrs) const override { 836 return generateCompactUnwindEncodingImpl(Instrs); 837 } 838 }; 839 840 } // end anonymous namespace 841 842 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, 843 const MCSubtargetInfo &STI, 844 const MCRegisterInfo &MRI, 845 const MCTargetOptions &Options) { 846 const Triple &TheTriple = STI.getTargetTriple(); 847 if (TheTriple.isOSBinFormatMachO()) 848 return new DarwinX86_32AsmBackend(T, MRI, STI); 849 850 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) 851 return new WindowsX86AsmBackend(T, false, STI); 852 853 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 854 855 if (TheTriple.isOSIAMCU()) 856 return new ELFX86_IAMCUAsmBackend(T, OSABI, STI); 857 858 return new ELFX86_32AsmBackend(T, OSABI, STI); 859 } 860 861 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, 862 const MCSubtargetInfo &STI, 863 const MCRegisterInfo &MRI, 864 const MCTargetOptions &Options) { 865 const Triple &TheTriple = STI.getTargetTriple(); 866 if (TheTriple.isOSBinFormatMachO()) { 867 MachO::CPUSubTypeX86 CS = 868 StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) 869 .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H) 870 .Default(MachO::CPU_SUBTYPE_X86_64_ALL); 871 return new DarwinX86_64AsmBackend(T, MRI, STI, CS); 872 } 873 874 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) 875 return new WindowsX86AsmBackend(T, true, STI); 876 877 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 878 879 if (TheTriple.getEnvironment() == Triple::GNUX32) 880 return new ELFX86_X32AsmBackend(T, OSABI, STI); 881 return new ELFX86_64AsmBackend(T, OSABI, STI); 882 } 883