1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/X86BaseInfo.h" 11 #include "MCTargetDesc/X86FixupKinds.h" 12 #include "llvm/ADT/StringSwitch.h" 13 #include "llvm/MC/MCAsmBackend.h" 14 #include "llvm/MC/MCELFObjectWriter.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCFixupKindInfo.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCMachObjectWriter.h" 19 #include "llvm/MC/MCObjectWriter.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/MC/MCSectionCOFF.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/MC/MCSectionMachO.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/ELF.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/MachO.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 using namespace llvm; 31 32 static unsigned getFixupKindLog2Size(unsigned Kind) { 33 switch (Kind) { 34 default: 35 llvm_unreachable("invalid fixup kind!"); 36 case FK_PCRel_1: 37 case FK_SecRel_1: 38 case FK_Data_1: 39 return 0; 40 case FK_PCRel_2: 41 case FK_SecRel_2: 42 case FK_Data_2: 43 return 1; 44 case FK_PCRel_4: 45 case X86::reloc_riprel_4byte: 46 case X86::reloc_riprel_4byte_movq_load: 47 case X86::reloc_signed_4byte: 48 case X86::reloc_global_offset_table: 49 case FK_SecRel_4: 50 case FK_Data_4: 51 return 2; 52 case FK_PCRel_8: 53 case FK_SecRel_8: 54 case FK_Data_8: 55 case X86::reloc_global_offset_table8: 56 return 3; 57 } 58 } 59 60 namespace { 61 62 class X86ELFObjectWriter : public MCELFObjectTargetWriter { 63 public: 64 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine, 65 bool HasRelocationAddend, bool foobar) 66 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {} 67 }; 68 69 class X86AsmBackend : public MCAsmBackend { 70 const StringRef CPU; 71 bool HasNopl; 72 uint64_t MaxNopLength; 73 public: 74 X86AsmBackend(const Target &T, StringRef CPU) : MCAsmBackend(), CPU(CPU) { 75 HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && 76 CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && 77 CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" && 78 CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" && 79 CPU != "c3" && CPU != "c3-2"; 80 // Max length of true long nop instruction is 15 bytes. 81 // Max length of long nop replacement instruction is 7 bytes. 82 // Taking into account SilverMont architecture features max length of nops 83 // is reduced for it to achieve better performance. 84 MaxNopLength = (!HasNopl || CPU == "slm") ? 7 : 15; 85 } 86 87 unsigned getNumFixupKinds() const override { 88 return X86::NumTargetFixupKinds; 89 } 90 91 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 92 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { 93 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }, 94 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel}, 95 { "reloc_signed_4byte", 0, 4 * 8, 0}, 96 { "reloc_global_offset_table", 0, 4 * 8, 0} 97 }; 98 99 if (Kind < FirstTargetFixupKind) 100 return MCAsmBackend::getFixupKindInfo(Kind); 101 102 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 103 "Invalid kind!"); 104 return Infos[Kind - FirstTargetFixupKind]; 105 } 106 107 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 108 uint64_t Value, bool IsPCRel) const override { 109 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); 110 111 assert(Fixup.getOffset() + Size <= DataSize && 112 "Invalid fixup offset!"); 113 114 // Check that uppper bits are either all zeros or all ones. 115 // Specifically ignore overflow/underflow as long as the leakage is 116 // limited to the lower bits. This is to remain compatible with 117 // other assemblers. 118 assert(isIntN(Size * 8 + 1, Value) && 119 "Value does not fit in the Fixup field"); 120 121 for (unsigned i = 0; i != Size; ++i) 122 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); 123 } 124 125 bool mayNeedRelaxation(const MCInst &Inst) const override; 126 127 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 128 const MCRelaxableFragment *DF, 129 const MCAsmLayout &Layout) const override; 130 131 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override; 132 133 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 134 }; 135 } // end anonymous namespace 136 137 static unsigned getRelaxedOpcodeBranch(unsigned Op) { 138 switch (Op) { 139 default: 140 return Op; 141 142 case X86::JAE_1: return X86::JAE_4; 143 case X86::JA_1: return X86::JA_4; 144 case X86::JBE_1: return X86::JBE_4; 145 case X86::JB_1: return X86::JB_4; 146 case X86::JE_1: return X86::JE_4; 147 case X86::JGE_1: return X86::JGE_4; 148 case X86::JG_1: return X86::JG_4; 149 case X86::JLE_1: return X86::JLE_4; 150 case X86::JL_1: return X86::JL_4; 151 case X86::JMP_1: return X86::JMP_4; 152 case X86::JNE_1: return X86::JNE_4; 153 case X86::JNO_1: return X86::JNO_4; 154 case X86::JNP_1: return X86::JNP_4; 155 case X86::JNS_1: return X86::JNS_4; 156 case X86::JO_1: return X86::JO_4; 157 case X86::JP_1: return X86::JP_4; 158 case X86::JS_1: return X86::JS_4; 159 } 160 } 161 162 static unsigned getRelaxedOpcodeArith(unsigned Op) { 163 switch (Op) { 164 default: 165 return Op; 166 167 // IMUL 168 case X86::IMUL16rri8: return X86::IMUL16rri; 169 case X86::IMUL16rmi8: return X86::IMUL16rmi; 170 case X86::IMUL32rri8: return X86::IMUL32rri; 171 case X86::IMUL32rmi8: return X86::IMUL32rmi; 172 case X86::IMUL64rri8: return X86::IMUL64rri32; 173 case X86::IMUL64rmi8: return X86::IMUL64rmi32; 174 175 // AND 176 case X86::AND16ri8: return X86::AND16ri; 177 case X86::AND16mi8: return X86::AND16mi; 178 case X86::AND32ri8: return X86::AND32ri; 179 case X86::AND32mi8: return X86::AND32mi; 180 case X86::AND64ri8: return X86::AND64ri32; 181 case X86::AND64mi8: return X86::AND64mi32; 182 183 // OR 184 case X86::OR16ri8: return X86::OR16ri; 185 case X86::OR16mi8: return X86::OR16mi; 186 case X86::OR32ri8: return X86::OR32ri; 187 case X86::OR32mi8: return X86::OR32mi; 188 case X86::OR64ri8: return X86::OR64ri32; 189 case X86::OR64mi8: return X86::OR64mi32; 190 191 // XOR 192 case X86::XOR16ri8: return X86::XOR16ri; 193 case X86::XOR16mi8: return X86::XOR16mi; 194 case X86::XOR32ri8: return X86::XOR32ri; 195 case X86::XOR32mi8: return X86::XOR32mi; 196 case X86::XOR64ri8: return X86::XOR64ri32; 197 case X86::XOR64mi8: return X86::XOR64mi32; 198 199 // ADD 200 case X86::ADD16ri8: return X86::ADD16ri; 201 case X86::ADD16mi8: return X86::ADD16mi; 202 case X86::ADD32ri8: return X86::ADD32ri; 203 case X86::ADD32mi8: return X86::ADD32mi; 204 case X86::ADD64ri8: return X86::ADD64ri32; 205 case X86::ADD64mi8: return X86::ADD64mi32; 206 207 // SUB 208 case X86::SUB16ri8: return X86::SUB16ri; 209 case X86::SUB16mi8: return X86::SUB16mi; 210 case X86::SUB32ri8: return X86::SUB32ri; 211 case X86::SUB32mi8: return X86::SUB32mi; 212 case X86::SUB64ri8: return X86::SUB64ri32; 213 case X86::SUB64mi8: return X86::SUB64mi32; 214 215 // CMP 216 case X86::CMP16ri8: return X86::CMP16ri; 217 case X86::CMP16mi8: return X86::CMP16mi; 218 case X86::CMP32ri8: return X86::CMP32ri; 219 case X86::CMP32mi8: return X86::CMP32mi; 220 case X86::CMP64ri8: return X86::CMP64ri32; 221 case X86::CMP64mi8: return X86::CMP64mi32; 222 223 // PUSH 224 case X86::PUSH32i8: return X86::PUSHi32; 225 case X86::PUSH16i8: return X86::PUSHi16; 226 case X86::PUSH64i8: return X86::PUSH64i32; 227 } 228 } 229 230 static unsigned getRelaxedOpcode(unsigned Op) { 231 unsigned R = getRelaxedOpcodeArith(Op); 232 if (R != Op) 233 return R; 234 return getRelaxedOpcodeBranch(Op); 235 } 236 237 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 238 // Branches can always be relaxed. 239 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode()) 240 return true; 241 242 // Check if this instruction is ever relaxable. 243 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode()) 244 return false; 245 246 247 // Check if the relaxable operand has an expression. For the current set of 248 // relaxable instructions, the relaxable operand is always the last operand. 249 unsigned RelaxableOp = Inst.getNumOperands() - 1; 250 if (Inst.getOperand(RelaxableOp).isExpr()) 251 return true; 252 253 return false; 254 } 255 256 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 257 uint64_t Value, 258 const MCRelaxableFragment *DF, 259 const MCAsmLayout &Layout) const { 260 // Relax if the value is too big for a (signed) i8. 261 return int64_t(Value) != int64_t(int8_t(Value)); 262 } 263 264 // FIXME: Can tblgen help at all here to verify there aren't other instructions 265 // we can relax? 266 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 267 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. 268 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 269 270 if (RelaxedOp == Inst.getOpcode()) { 271 SmallString<256> Tmp; 272 raw_svector_ostream OS(Tmp); 273 Inst.dump_pretty(OS); 274 OS << "\n"; 275 report_fatal_error("unexpected instruction to relax: " + OS.str()); 276 } 277 278 Res = Inst; 279 Res.setOpcode(RelaxedOp); 280 } 281 282 /// \brief Write a sequence of optimal nops to the output, covering \p Count 283 /// bytes. 284 /// \return - true on success, false on failure 285 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 286 static const uint8_t TrueNops[10][10] = { 287 // nop 288 {0x90}, 289 // xchg %ax,%ax 290 {0x66, 0x90}, 291 // nopl (%[re]ax) 292 {0x0f, 0x1f, 0x00}, 293 // nopl 0(%[re]ax) 294 {0x0f, 0x1f, 0x40, 0x00}, 295 // nopl 0(%[re]ax,%[re]ax,1) 296 {0x0f, 0x1f, 0x44, 0x00, 0x00}, 297 // nopw 0(%[re]ax,%[re]ax,1) 298 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00}, 299 // nopl 0L(%[re]ax) 300 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00}, 301 // nopl 0L(%[re]ax,%[re]ax,1) 302 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 303 // nopw 0L(%[re]ax,%[re]ax,1) 304 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 305 // nopw %cs:0L(%[re]ax,%[re]ax,1) 306 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 307 }; 308 309 // Alternative nop instructions for CPUs which don't support long nops. 310 static const uint8_t AltNops[7][10] = { 311 // nop 312 {0x90}, 313 // xchg %ax,%ax 314 {0x66, 0x90}, 315 // lea 0x0(%esi),%esi 316 {0x8d, 0x76, 0x00}, 317 // lea 0x0(%esi),%esi 318 {0x8d, 0x74, 0x26, 0x00}, 319 // nop + lea 0x0(%esi),%esi 320 {0x90, 0x8d, 0x74, 0x26, 0x00}, 321 // lea 0x0(%esi),%esi 322 {0x8d, 0xb6, 0x00, 0x00, 0x00, 0x00 }, 323 // lea 0x0(%esi),%esi 324 {0x8d, 0xb4, 0x26, 0x00, 0x00, 0x00, 0x00}, 325 }; 326 327 // Select the right NOP table. 328 // FIXME: Can we get if CPU supports long nops from the subtarget somehow? 329 const uint8_t (*Nops)[10] = HasNopl ? TrueNops : AltNops; 330 assert(HasNopl || MaxNopLength <= 7); 331 332 // Emit as many largest nops as needed, then emit a nop of the remaining 333 // length. 334 do { 335 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength); 336 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10; 337 for (uint8_t i = 0; i < Prefixes; i++) 338 OW->write8(0x66); 339 const uint8_t Rest = ThisNopLength - Prefixes; 340 for (uint8_t i = 0; i < Rest; i++) 341 OW->write8(Nops[Rest - 1][i]); 342 Count -= ThisNopLength; 343 } while (Count != 0); 344 345 return true; 346 } 347 348 /* *** */ 349 350 namespace { 351 352 class ELFX86AsmBackend : public X86AsmBackend { 353 public: 354 uint8_t OSABI; 355 ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 356 : X86AsmBackend(T, CPU), OSABI(OSABI) {} 357 }; 358 359 class ELFX86_32AsmBackend : public ELFX86AsmBackend { 360 public: 361 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 362 : ELFX86AsmBackend(T, OSABI, CPU) {} 363 364 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 365 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386); 366 } 367 }; 368 369 class ELFX86_X32AsmBackend : public ELFX86AsmBackend { 370 public: 371 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 372 : ELFX86AsmBackend(T, OSABI, CPU) {} 373 374 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 375 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, 376 ELF::EM_X86_64); 377 } 378 }; 379 380 class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend { 381 public: 382 ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 383 : ELFX86AsmBackend(T, OSABI, CPU) {} 384 385 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 386 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, 387 ELF::EM_IAMCU); 388 } 389 }; 390 391 class ELFX86_64AsmBackend : public ELFX86AsmBackend { 392 public: 393 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 394 : ELFX86AsmBackend(T, OSABI, CPU) {} 395 396 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 397 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64); 398 } 399 }; 400 401 class WindowsX86AsmBackend : public X86AsmBackend { 402 bool Is64Bit; 403 404 public: 405 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU) 406 : X86AsmBackend(T, CPU) 407 , Is64Bit(is64Bit) { 408 } 409 410 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 411 return createX86WinCOFFObjectWriter(OS, Is64Bit); 412 } 413 }; 414 415 namespace CU { 416 417 /// Compact unwind encoding values. 418 enum CompactUnwindEncodings { 419 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after 420 /// the return address, then [RE]SP is moved to [RE]BP. 421 UNWIND_MODE_BP_FRAME = 0x01000000, 422 423 /// A frameless function with a small constant stack size. 424 UNWIND_MODE_STACK_IMMD = 0x02000000, 425 426 /// A frameless function with a large constant stack size. 427 UNWIND_MODE_STACK_IND = 0x03000000, 428 429 /// No compact unwind encoding is available. 430 UNWIND_MODE_DWARF = 0x04000000, 431 432 /// Mask for encoding the frame registers. 433 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF, 434 435 /// Mask for encoding the frameless registers. 436 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF 437 }; 438 439 } // end CU namespace 440 441 class DarwinX86AsmBackend : public X86AsmBackend { 442 const MCRegisterInfo &MRI; 443 444 /// \brief Number of registers that can be saved in a compact unwind encoding. 445 enum { CU_NUM_SAVED_REGS = 6 }; 446 447 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS]; 448 bool Is64Bit; 449 450 unsigned OffsetSize; ///< Offset of a "push" instruction. 451 unsigned MoveInstrSize; ///< Size of a "move" instruction. 452 unsigned StackDivide; ///< Amount to adjust stack size by. 453 protected: 454 /// \brief Size of a "push" instruction for the given register. 455 unsigned PushInstrSize(unsigned Reg) const { 456 switch (Reg) { 457 case X86::EBX: 458 case X86::ECX: 459 case X86::EDX: 460 case X86::EDI: 461 case X86::ESI: 462 case X86::EBP: 463 case X86::RBX: 464 case X86::RBP: 465 return 1; 466 case X86::R12: 467 case X86::R13: 468 case X86::R14: 469 case X86::R15: 470 return 2; 471 } 472 return 1; 473 } 474 475 /// \brief Implementation of algorithm to generate the compact unwind encoding 476 /// for the CFI instructions. 477 uint32_t 478 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const { 479 if (Instrs.empty()) return 0; 480 481 // Reset the saved registers. 482 unsigned SavedRegIdx = 0; 483 memset(SavedRegs, 0, sizeof(SavedRegs)); 484 485 bool HasFP = false; 486 487 // Encode that we are using EBP/RBP as the frame pointer. 488 uint32_t CompactUnwindEncoding = 0; 489 490 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2; 491 unsigned InstrOffset = 0; 492 unsigned StackAdjust = 0; 493 unsigned StackSize = 0; 494 unsigned PrevStackSize = 0; 495 unsigned NumDefCFAOffsets = 0; 496 497 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) { 498 const MCCFIInstruction &Inst = Instrs[i]; 499 500 switch (Inst.getOperation()) { 501 default: 502 // Any other CFI directives indicate a frame that we aren't prepared 503 // to represent via compact unwind, so just bail out. 504 return 0; 505 case MCCFIInstruction::OpDefCfaRegister: { 506 // Defines a frame pointer. E.g. 507 // 508 // movq %rsp, %rbp 509 // L0: 510 // .cfi_def_cfa_register %rbp 511 // 512 HasFP = true; 513 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) == 514 (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!"); 515 516 // Reset the counts. 517 memset(SavedRegs, 0, sizeof(SavedRegs)); 518 StackAdjust = 0; 519 SavedRegIdx = 0; 520 InstrOffset += MoveInstrSize; 521 break; 522 } 523 case MCCFIInstruction::OpDefCfaOffset: { 524 // Defines a new offset for the CFA. E.g. 525 // 526 // With frame: 527 // 528 // pushq %rbp 529 // L0: 530 // .cfi_def_cfa_offset 16 531 // 532 // Without frame: 533 // 534 // subq $72, %rsp 535 // L0: 536 // .cfi_def_cfa_offset 80 537 // 538 PrevStackSize = StackSize; 539 StackSize = std::abs(Inst.getOffset()) / StackDivide; 540 ++NumDefCFAOffsets; 541 break; 542 } 543 case MCCFIInstruction::OpOffset: { 544 // Defines a "push" of a callee-saved register. E.g. 545 // 546 // pushq %r15 547 // pushq %r14 548 // pushq %rbx 549 // L0: 550 // subq $120, %rsp 551 // L1: 552 // .cfi_offset %rbx, -40 553 // .cfi_offset %r14, -32 554 // .cfi_offset %r15, -24 555 // 556 if (SavedRegIdx == CU_NUM_SAVED_REGS) 557 // If there are too many saved registers, we cannot use a compact 558 // unwind encoding. 559 return CU::UNWIND_MODE_DWARF; 560 561 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 562 SavedRegs[SavedRegIdx++] = Reg; 563 StackAdjust += OffsetSize; 564 InstrOffset += PushInstrSize(Reg); 565 break; 566 } 567 } 568 } 569 570 StackAdjust /= StackDivide; 571 572 if (HasFP) { 573 if ((StackAdjust & 0xFF) != StackAdjust) 574 // Offset was too big for a compact unwind encoding. 575 return CU::UNWIND_MODE_DWARF; 576 577 // Get the encoding of the saved registers when we have a frame pointer. 578 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(); 579 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 580 581 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME; 582 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16; 583 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS; 584 } else { 585 // If the amount of the stack allocation is the size of a register, then 586 // we "push" the RAX/EAX register onto the stack instead of adjusting the 587 // stack pointer with a SUB instruction. We don't support the push of the 588 // RAX/EAX register with compact unwind. So we check for that situation 589 // here. 590 if ((NumDefCFAOffsets == SavedRegIdx + 1 && 591 StackSize - PrevStackSize == 1) || 592 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2)) 593 return CU::UNWIND_MODE_DWARF; 594 595 SubtractInstrIdx += InstrOffset; 596 ++StackAdjust; 597 598 if ((StackSize & 0xFF) == StackSize) { 599 // Frameless stack with a small stack size. 600 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD; 601 602 // Encode the stack size. 603 CompactUnwindEncoding |= (StackSize & 0xFF) << 16; 604 } else { 605 if ((StackAdjust & 0x7) != StackAdjust) 606 // The extra stack adjustments are too big for us to handle. 607 return CU::UNWIND_MODE_DWARF; 608 609 // Frameless stack with an offset too large for us to encode compactly. 610 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND; 611 612 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' 613 // instruction. 614 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; 615 616 // Encode any extra stack stack adjustments (done via push 617 // instructions). 618 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13; 619 } 620 621 // Encode the number of registers saved. (Reverse the list first.) 622 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]); 623 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10; 624 625 // Get the encoding of the saved registers when we don't have a frame 626 // pointer. 627 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx); 628 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 629 630 // Encode the register encoding. 631 CompactUnwindEncoding |= 632 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION; 633 } 634 635 return CompactUnwindEncoding; 636 } 637 638 private: 639 /// \brief Get the compact unwind number for a given register. The number 640 /// corresponds to the enum lists in compact_unwind_encoding.h. 641 int getCompactUnwindRegNum(unsigned Reg) const { 642 static const MCPhysReg CU32BitRegs[7] = { 643 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 644 }; 645 static const MCPhysReg CU64BitRegs[] = { 646 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 647 }; 648 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs; 649 for (int Idx = 1; *CURegs; ++CURegs, ++Idx) 650 if (*CURegs == Reg) 651 return Idx; 652 653 return -1; 654 } 655 656 /// \brief Return the registers encoded for a compact encoding with a frame 657 /// pointer. 658 uint32_t encodeCompactUnwindRegistersWithFrame() const { 659 // Encode the registers in the order they were saved --- 3-bits per 660 // register. The list of saved registers is assumed to be in reverse 661 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS. 662 uint32_t RegEnc = 0; 663 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) { 664 unsigned Reg = SavedRegs[i]; 665 if (Reg == 0) break; 666 667 int CURegNum = getCompactUnwindRegNum(Reg); 668 if (CURegNum == -1) return ~0U; 669 670 // Encode the 3-bit register number in order, skipping over 3-bits for 671 // each register. 672 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3); 673 } 674 675 assert((RegEnc & 0x3FFFF) == RegEnc && 676 "Invalid compact register encoding!"); 677 return RegEnc; 678 } 679 680 /// \brief Create the permutation encoding used with frameless stacks. It is 681 /// passed the number of registers to be saved and an array of the registers 682 /// saved. 683 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const { 684 // The saved registers are numbered from 1 to 6. In order to encode the 685 // order in which they were saved, we re-number them according to their 686 // place in the register order. The re-numbering is relative to the last 687 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in 688 // that order: 689 // 690 // Orig Re-Num 691 // ---- ------ 692 // 6 6 693 // 2 2 694 // 4 3 695 // 5 3 696 // 697 for (unsigned i = 0; i < RegCount; ++i) { 698 int CUReg = getCompactUnwindRegNum(SavedRegs[i]); 699 if (CUReg == -1) return ~0U; 700 SavedRegs[i] = CUReg; 701 } 702 703 // Reverse the list. 704 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]); 705 706 uint32_t RenumRegs[CU_NUM_SAVED_REGS]; 707 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){ 708 unsigned Countless = 0; 709 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j) 710 if (SavedRegs[j] < SavedRegs[i]) 711 ++Countless; 712 713 RenumRegs[i] = SavedRegs[i] - Countless - 1; 714 } 715 716 // Take the renumbered values and encode them into a 10-bit number. 717 uint32_t permutationEncoding = 0; 718 switch (RegCount) { 719 case 6: 720 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] 721 + 6 * RenumRegs[2] + 2 * RenumRegs[3] 722 + RenumRegs[4]; 723 break; 724 case 5: 725 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] 726 + 6 * RenumRegs[3] + 2 * RenumRegs[4] 727 + RenumRegs[5]; 728 break; 729 case 4: 730 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] 731 + 3 * RenumRegs[4] + RenumRegs[5]; 732 break; 733 case 3: 734 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] 735 + RenumRegs[5]; 736 break; 737 case 2: 738 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; 739 break; 740 case 1: 741 permutationEncoding |= RenumRegs[5]; 742 break; 743 } 744 745 assert((permutationEncoding & 0x3FF) == permutationEncoding && 746 "Invalid compact register encoding!"); 747 return permutationEncoding; 748 } 749 750 public: 751 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, 752 bool Is64Bit) 753 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) { 754 memset(SavedRegs, 0, sizeof(SavedRegs)); 755 OffsetSize = Is64Bit ? 8 : 4; 756 MoveInstrSize = Is64Bit ? 3 : 2; 757 StackDivide = Is64Bit ? 8 : 4; 758 } 759 }; 760 761 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { 762 public: 763 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, 764 StringRef CPU) 765 : DarwinX86AsmBackend(T, MRI, CPU, false) {} 766 767 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 768 return createX86MachObjectWriter(OS, /*Is64Bit=*/false, 769 MachO::CPU_TYPE_I386, 770 MachO::CPU_SUBTYPE_I386_ALL); 771 } 772 773 /// \brief Generate the compact unwind encoding for the CFI instructions. 774 uint32_t generateCompactUnwindEncoding( 775 ArrayRef<MCCFIInstruction> Instrs) const override { 776 return generateCompactUnwindEncodingImpl(Instrs); 777 } 778 }; 779 780 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { 781 const MachO::CPUSubTypeX86 Subtype; 782 public: 783 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, 784 StringRef CPU, MachO::CPUSubTypeX86 st) 785 : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {} 786 787 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 788 return createX86MachObjectWriter(OS, /*Is64Bit=*/true, 789 MachO::CPU_TYPE_X86_64, Subtype); 790 } 791 792 /// \brief Generate the compact unwind encoding for the CFI instructions. 793 uint32_t generateCompactUnwindEncoding( 794 ArrayRef<MCCFIInstruction> Instrs) const override { 795 return generateCompactUnwindEncodingImpl(Instrs); 796 } 797 }; 798 799 } // end anonymous namespace 800 801 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, 802 const MCRegisterInfo &MRI, 803 const Triple &TheTriple, 804 StringRef CPU) { 805 if (TheTriple.isOSBinFormatMachO()) 806 return new DarwinX86_32AsmBackend(T, MRI, CPU); 807 808 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) 809 return new WindowsX86AsmBackend(T, false, CPU); 810 811 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 812 813 if (TheTriple.isOSIAMCU()) 814 return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU); 815 816 return new ELFX86_32AsmBackend(T, OSABI, CPU); 817 } 818 819 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, 820 const MCRegisterInfo &MRI, 821 const Triple &TheTriple, 822 StringRef CPU) { 823 if (TheTriple.isOSBinFormatMachO()) { 824 MachO::CPUSubTypeX86 CS = 825 StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) 826 .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H) 827 .Default(MachO::CPU_SUBTYPE_X86_64_ALL); 828 return new DarwinX86_64AsmBackend(T, MRI, CPU, CS); 829 } 830 831 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) 832 return new WindowsX86AsmBackend(T, true, CPU); 833 834 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 835 836 if (TheTriple.getEnvironment() == Triple::GNUX32) 837 return new ELFX86_X32AsmBackend(T, OSABI, CPU); 838 return new ELFX86_64AsmBackend(T, OSABI, CPU); 839 } 840