1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/X86BaseInfo.h" 11 #include "MCTargetDesc/X86FixupKinds.h" 12 #include "llvm/ADT/StringSwitch.h" 13 #include "llvm/BinaryFormat/ELF.h" 14 #include "llvm/BinaryFormat/MachO.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCELFObjectWriter.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixupKindInfo.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCMachObjectWriter.h" 21 #include "llvm/MC/MCObjectWriter.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSectionMachO.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/raw_ostream.h" 27 using namespace llvm; 28 29 static unsigned getFixupKindLog2Size(unsigned Kind) { 30 switch (Kind) { 31 default: 32 llvm_unreachable("invalid fixup kind!"); 33 case FK_PCRel_1: 34 case FK_SecRel_1: 35 case FK_Data_1: 36 return 0; 37 case FK_PCRel_2: 38 case FK_SecRel_2: 39 case FK_Data_2: 40 return 1; 41 case FK_PCRel_4: 42 case X86::reloc_riprel_4byte: 43 case X86::reloc_riprel_4byte_relax: 44 case X86::reloc_riprel_4byte_relax_rex: 45 case X86::reloc_riprel_4byte_movq_load: 46 case X86::reloc_signed_4byte: 47 case X86::reloc_signed_4byte_relax: 48 case X86::reloc_global_offset_table: 49 case FK_SecRel_4: 50 case FK_Data_4: 51 return 2; 52 case FK_PCRel_8: 53 case FK_SecRel_8: 54 case FK_Data_8: 55 case X86::reloc_global_offset_table8: 56 return 3; 57 } 58 } 59 60 namespace { 61 62 class X86ELFObjectWriter : public MCELFObjectTargetWriter { 63 public: 64 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine, 65 bool HasRelocationAddend, bool foobar) 66 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {} 67 }; 68 69 class X86AsmBackend : public MCAsmBackend { 70 const MCSubtargetInfo &STI; 71 public: 72 X86AsmBackend(const Target &T, const MCSubtargetInfo &STI) 73 : MCAsmBackend(), STI(STI) {} 74 75 unsigned getNumFixupKinds() const override { 76 return X86::NumTargetFixupKinds; 77 } 78 79 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 80 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { 81 {"reloc_riprel_4byte", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 82 {"reloc_riprel_4byte_movq_load", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 83 {"reloc_riprel_4byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 84 {"reloc_riprel_4byte_relax_rex", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 85 {"reloc_signed_4byte", 0, 32, 0}, 86 {"reloc_signed_4byte_relax", 0, 32, 0}, 87 {"reloc_global_offset_table", 0, 32, 0}, 88 {"reloc_global_offset_table8", 0, 64, 0}, 89 }; 90 91 if (Kind < FirstTargetFixupKind) 92 return MCAsmBackend::getFixupKindInfo(Kind); 93 94 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 95 "Invalid kind!"); 96 return Infos[Kind - FirstTargetFixupKind]; 97 } 98 99 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 100 const MCValue &Target, MutableArrayRef<char> Data, 101 uint64_t Value, bool IsResolved) const override { 102 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); 103 104 assert(Fixup.getOffset() + Size <= Data.size() && "Invalid fixup offset!"); 105 106 // Check that uppper bits are either all zeros or all ones. 107 // Specifically ignore overflow/underflow as long as the leakage is 108 // limited to the lower bits. This is to remain compatible with 109 // other assemblers. 110 assert(isIntN(Size * 8 + 1, Value) && 111 "Value does not fit in the Fixup field"); 112 113 for (unsigned i = 0; i != Size; ++i) 114 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); 115 } 116 117 bool mayNeedRelaxation(const MCInst &Inst) const override; 118 119 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 120 const MCRelaxableFragment *DF, 121 const MCAsmLayout &Layout) const override; 122 123 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 124 MCInst &Res) const override; 125 126 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 127 }; 128 } // end anonymous namespace 129 130 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) { 131 unsigned Op = Inst.getOpcode(); 132 switch (Op) { 133 default: 134 return Op; 135 case X86::JAE_1: 136 return (is16BitMode) ? X86::JAE_2 : X86::JAE_4; 137 case X86::JA_1: 138 return (is16BitMode) ? X86::JA_2 : X86::JA_4; 139 case X86::JBE_1: 140 return (is16BitMode) ? X86::JBE_2 : X86::JBE_4; 141 case X86::JB_1: 142 return (is16BitMode) ? X86::JB_2 : X86::JB_4; 143 case X86::JE_1: 144 return (is16BitMode) ? X86::JE_2 : X86::JE_4; 145 case X86::JGE_1: 146 return (is16BitMode) ? X86::JGE_2 : X86::JGE_4; 147 case X86::JG_1: 148 return (is16BitMode) ? X86::JG_2 : X86::JG_4; 149 case X86::JLE_1: 150 return (is16BitMode) ? X86::JLE_2 : X86::JLE_4; 151 case X86::JL_1: 152 return (is16BitMode) ? X86::JL_2 : X86::JL_4; 153 case X86::JMP_1: 154 return (is16BitMode) ? X86::JMP_2 : X86::JMP_4; 155 case X86::JNE_1: 156 return (is16BitMode) ? X86::JNE_2 : X86::JNE_4; 157 case X86::JNO_1: 158 return (is16BitMode) ? X86::JNO_2 : X86::JNO_4; 159 case X86::JNP_1: 160 return (is16BitMode) ? X86::JNP_2 : X86::JNP_4; 161 case X86::JNS_1: 162 return (is16BitMode) ? X86::JNS_2 : X86::JNS_4; 163 case X86::JO_1: 164 return (is16BitMode) ? X86::JO_2 : X86::JO_4; 165 case X86::JP_1: 166 return (is16BitMode) ? X86::JP_2 : X86::JP_4; 167 case X86::JS_1: 168 return (is16BitMode) ? X86::JS_2 : X86::JS_4; 169 } 170 } 171 172 static unsigned getRelaxedOpcodeArith(const MCInst &Inst) { 173 unsigned Op = Inst.getOpcode(); 174 switch (Op) { 175 default: 176 return Op; 177 178 // IMUL 179 case X86::IMUL16rri8: return X86::IMUL16rri; 180 case X86::IMUL16rmi8: return X86::IMUL16rmi; 181 case X86::IMUL32rri8: return X86::IMUL32rri; 182 case X86::IMUL32rmi8: return X86::IMUL32rmi; 183 case X86::IMUL64rri8: return X86::IMUL64rri32; 184 case X86::IMUL64rmi8: return X86::IMUL64rmi32; 185 186 // AND 187 case X86::AND16ri8: return X86::AND16ri; 188 case X86::AND16mi8: return X86::AND16mi; 189 case X86::AND32ri8: return X86::AND32ri; 190 case X86::AND32mi8: return X86::AND32mi; 191 case X86::AND64ri8: return X86::AND64ri32; 192 case X86::AND64mi8: return X86::AND64mi32; 193 194 // OR 195 case X86::OR16ri8: return X86::OR16ri; 196 case X86::OR16mi8: return X86::OR16mi; 197 case X86::OR32ri8: return X86::OR32ri; 198 case X86::OR32mi8: return X86::OR32mi; 199 case X86::OR64ri8: return X86::OR64ri32; 200 case X86::OR64mi8: return X86::OR64mi32; 201 202 // XOR 203 case X86::XOR16ri8: return X86::XOR16ri; 204 case X86::XOR16mi8: return X86::XOR16mi; 205 case X86::XOR32ri8: return X86::XOR32ri; 206 case X86::XOR32mi8: return X86::XOR32mi; 207 case X86::XOR64ri8: return X86::XOR64ri32; 208 case X86::XOR64mi8: return X86::XOR64mi32; 209 210 // ADD 211 case X86::ADD16ri8: return X86::ADD16ri; 212 case X86::ADD16mi8: return X86::ADD16mi; 213 case X86::ADD32ri8: return X86::ADD32ri; 214 case X86::ADD32mi8: return X86::ADD32mi; 215 case X86::ADD64ri8: return X86::ADD64ri32; 216 case X86::ADD64mi8: return X86::ADD64mi32; 217 218 // ADC 219 case X86::ADC16ri8: return X86::ADC16ri; 220 case X86::ADC16mi8: return X86::ADC16mi; 221 case X86::ADC32ri8: return X86::ADC32ri; 222 case X86::ADC32mi8: return X86::ADC32mi; 223 case X86::ADC64ri8: return X86::ADC64ri32; 224 case X86::ADC64mi8: return X86::ADC64mi32; 225 226 // SUB 227 case X86::SUB16ri8: return X86::SUB16ri; 228 case X86::SUB16mi8: return X86::SUB16mi; 229 case X86::SUB32ri8: return X86::SUB32ri; 230 case X86::SUB32mi8: return X86::SUB32mi; 231 case X86::SUB64ri8: return X86::SUB64ri32; 232 case X86::SUB64mi8: return X86::SUB64mi32; 233 234 // SBB 235 case X86::SBB16ri8: return X86::SBB16ri; 236 case X86::SBB16mi8: return X86::SBB16mi; 237 case X86::SBB32ri8: return X86::SBB32ri; 238 case X86::SBB32mi8: return X86::SBB32mi; 239 case X86::SBB64ri8: return X86::SBB64ri32; 240 case X86::SBB64mi8: return X86::SBB64mi32; 241 242 // CMP 243 case X86::CMP16ri8: return X86::CMP16ri; 244 case X86::CMP16mi8: return X86::CMP16mi; 245 case X86::CMP32ri8: return X86::CMP32ri; 246 case X86::CMP32mi8: return X86::CMP32mi; 247 case X86::CMP64ri8: return X86::CMP64ri32; 248 case X86::CMP64mi8: return X86::CMP64mi32; 249 250 // PUSH 251 case X86::PUSH32i8: return X86::PUSHi32; 252 case X86::PUSH16i8: return X86::PUSHi16; 253 case X86::PUSH64i8: return X86::PUSH64i32; 254 } 255 } 256 257 static unsigned getRelaxedOpcode(const MCInst &Inst, bool is16BitMode) { 258 unsigned R = getRelaxedOpcodeArith(Inst); 259 if (R != Inst.getOpcode()) 260 return R; 261 return getRelaxedOpcodeBranch(Inst, is16BitMode); 262 } 263 264 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 265 // Branches can always be relaxed in either mode. 266 if (getRelaxedOpcodeBranch(Inst, false) != Inst.getOpcode()) 267 return true; 268 269 // Check if this instruction is ever relaxable. 270 if (getRelaxedOpcodeArith(Inst) == Inst.getOpcode()) 271 return false; 272 273 274 // Check if the relaxable operand has an expression. For the current set of 275 // relaxable instructions, the relaxable operand is always the last operand. 276 unsigned RelaxableOp = Inst.getNumOperands() - 1; 277 if (Inst.getOperand(RelaxableOp).isExpr()) 278 return true; 279 280 return false; 281 } 282 283 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 284 uint64_t Value, 285 const MCRelaxableFragment *DF, 286 const MCAsmLayout &Layout) const { 287 // Relax if the value is too big for a (signed) i8. 288 return int64_t(Value) != int64_t(int8_t(Value)); 289 } 290 291 // FIXME: Can tblgen help at all here to verify there aren't other instructions 292 // we can relax? 293 void X86AsmBackend::relaxInstruction(const MCInst &Inst, 294 const MCSubtargetInfo &STI, 295 MCInst &Res) const { 296 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. 297 bool is16BitMode = STI.getFeatureBits()[X86::Mode16Bit]; 298 unsigned RelaxedOp = getRelaxedOpcode(Inst, is16BitMode); 299 300 if (RelaxedOp == Inst.getOpcode()) { 301 SmallString<256> Tmp; 302 raw_svector_ostream OS(Tmp); 303 Inst.dump_pretty(OS); 304 OS << "\n"; 305 report_fatal_error("unexpected instruction to relax: " + OS.str()); 306 } 307 308 Res = Inst; 309 Res.setOpcode(RelaxedOp); 310 } 311 312 /// \brief Write a sequence of optimal nops to the output, covering \p Count 313 /// bytes. 314 /// \return - true on success, false on failure 315 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 316 static const uint8_t Nops[10][10] = { 317 // nop 318 {0x90}, 319 // xchg %ax,%ax 320 {0x66, 0x90}, 321 // nopl (%[re]ax) 322 {0x0f, 0x1f, 0x00}, 323 // nopl 0(%[re]ax) 324 {0x0f, 0x1f, 0x40, 0x00}, 325 // nopl 0(%[re]ax,%[re]ax,1) 326 {0x0f, 0x1f, 0x44, 0x00, 0x00}, 327 // nopw 0(%[re]ax,%[re]ax,1) 328 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00}, 329 // nopl 0L(%[re]ax) 330 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00}, 331 // nopl 0L(%[re]ax,%[re]ax,1) 332 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 333 // nopw 0L(%[re]ax,%[re]ax,1) 334 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 335 // nopw %cs:0L(%[re]ax,%[re]ax,1) 336 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 337 }; 338 339 // This CPU doesn't support long nops. If needed add more. 340 // FIXME: We could generated something better than plain 0x90. 341 if (!STI.getFeatureBits()[X86::FeatureNOPL]) { 342 for (uint64_t i = 0; i < Count; ++i) 343 OW->write8(0x90); 344 return true; 345 } 346 347 // 15-bytes is the longest single NOP instruction, but 10-bytes is 348 // commonly the longest that can be efficiently decoded. 349 uint64_t MaxNopLength = 10; 350 if (STI.getFeatureBits()[X86::ProcIntelSLM]) 351 MaxNopLength = 7; 352 else if (STI.getFeatureBits()[X86::FeatureFast15ByteNOP]) 353 MaxNopLength = 15; 354 else if (STI.getFeatureBits()[X86::FeatureFast11ByteNOP]) 355 MaxNopLength = 11; 356 357 // Emit as many MaxNopLength NOPs as needed, then emit a NOP of the remaining 358 // length. 359 do { 360 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength); 361 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10; 362 for (uint8_t i = 0; i < Prefixes; i++) 363 OW->write8(0x66); 364 const uint8_t Rest = ThisNopLength - Prefixes; 365 for (uint8_t i = 0; i < Rest; i++) 366 OW->write8(Nops[Rest - 1][i]); 367 Count -= ThisNopLength; 368 } while (Count != 0); 369 370 return true; 371 } 372 373 /* *** */ 374 375 namespace { 376 377 class ELFX86AsmBackend : public X86AsmBackend { 378 public: 379 uint8_t OSABI; 380 ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI) 381 : X86AsmBackend(T, STI), OSABI(OSABI) {} 382 }; 383 384 class ELFX86_32AsmBackend : public ELFX86AsmBackend { 385 public: 386 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, 387 const MCSubtargetInfo &STI) 388 : ELFX86AsmBackend(T, OSABI, STI) {} 389 390 std::unique_ptr<MCObjectWriter> 391 createObjectWriter(raw_pwrite_stream &OS) const override { 392 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386); 393 } 394 }; 395 396 class ELFX86_X32AsmBackend : public ELFX86AsmBackend { 397 public: 398 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, 399 const MCSubtargetInfo &STI) 400 : ELFX86AsmBackend(T, OSABI, STI) {} 401 402 std::unique_ptr<MCObjectWriter> 403 createObjectWriter(raw_pwrite_stream &OS) const override { 404 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, 405 ELF::EM_X86_64); 406 } 407 }; 408 409 class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend { 410 public: 411 ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, 412 const MCSubtargetInfo &STI) 413 : ELFX86AsmBackend(T, OSABI, STI) {} 414 415 std::unique_ptr<MCObjectWriter> 416 createObjectWriter(raw_pwrite_stream &OS) const override { 417 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, 418 ELF::EM_IAMCU); 419 } 420 }; 421 422 class ELFX86_64AsmBackend : public ELFX86AsmBackend { 423 public: 424 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, 425 const MCSubtargetInfo &STI) 426 : ELFX86AsmBackend(T, OSABI, STI) {} 427 428 std::unique_ptr<MCObjectWriter> 429 createObjectWriter(raw_pwrite_stream &OS) const override { 430 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64); 431 } 432 }; 433 434 class WindowsX86AsmBackend : public X86AsmBackend { 435 bool Is64Bit; 436 437 public: 438 WindowsX86AsmBackend(const Target &T, bool is64Bit, 439 const MCSubtargetInfo &STI) 440 : X86AsmBackend(T, STI) 441 , Is64Bit(is64Bit) { 442 } 443 444 Optional<MCFixupKind> getFixupKind(StringRef Name) const override { 445 return StringSwitch<Optional<MCFixupKind>>(Name) 446 .Case("dir32", FK_Data_4) 447 .Case("secrel32", FK_SecRel_4) 448 .Case("secidx", FK_SecRel_2) 449 .Default(MCAsmBackend::getFixupKind(Name)); 450 } 451 452 std::unique_ptr<MCObjectWriter> 453 createObjectWriter(raw_pwrite_stream &OS) const override { 454 return createX86WinCOFFObjectWriter(OS, Is64Bit); 455 } 456 }; 457 458 namespace CU { 459 460 /// Compact unwind encoding values. 461 enum CompactUnwindEncodings { 462 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after 463 /// the return address, then [RE]SP is moved to [RE]BP. 464 UNWIND_MODE_BP_FRAME = 0x01000000, 465 466 /// A frameless function with a small constant stack size. 467 UNWIND_MODE_STACK_IMMD = 0x02000000, 468 469 /// A frameless function with a large constant stack size. 470 UNWIND_MODE_STACK_IND = 0x03000000, 471 472 /// No compact unwind encoding is available. 473 UNWIND_MODE_DWARF = 0x04000000, 474 475 /// Mask for encoding the frame registers. 476 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF, 477 478 /// Mask for encoding the frameless registers. 479 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF 480 }; 481 482 } // end CU namespace 483 484 class DarwinX86AsmBackend : public X86AsmBackend { 485 const MCRegisterInfo &MRI; 486 487 /// \brief Number of registers that can be saved in a compact unwind encoding. 488 enum { CU_NUM_SAVED_REGS = 6 }; 489 490 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS]; 491 bool Is64Bit; 492 493 unsigned OffsetSize; ///< Offset of a "push" instruction. 494 unsigned MoveInstrSize; ///< Size of a "move" instruction. 495 unsigned StackDivide; ///< Amount to adjust stack size by. 496 protected: 497 /// \brief Size of a "push" instruction for the given register. 498 unsigned PushInstrSize(unsigned Reg) const { 499 switch (Reg) { 500 case X86::EBX: 501 case X86::ECX: 502 case X86::EDX: 503 case X86::EDI: 504 case X86::ESI: 505 case X86::EBP: 506 case X86::RBX: 507 case X86::RBP: 508 return 1; 509 case X86::R12: 510 case X86::R13: 511 case X86::R14: 512 case X86::R15: 513 return 2; 514 } 515 return 1; 516 } 517 518 /// \brief Implementation of algorithm to generate the compact unwind encoding 519 /// for the CFI instructions. 520 uint32_t 521 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const { 522 if (Instrs.empty()) return 0; 523 524 // Reset the saved registers. 525 unsigned SavedRegIdx = 0; 526 memset(SavedRegs, 0, sizeof(SavedRegs)); 527 528 bool HasFP = false; 529 530 // Encode that we are using EBP/RBP as the frame pointer. 531 uint32_t CompactUnwindEncoding = 0; 532 533 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2; 534 unsigned InstrOffset = 0; 535 unsigned StackAdjust = 0; 536 unsigned StackSize = 0; 537 unsigned PrevStackSize = 0; 538 unsigned NumDefCFAOffsets = 0; 539 540 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) { 541 const MCCFIInstruction &Inst = Instrs[i]; 542 543 switch (Inst.getOperation()) { 544 default: 545 // Any other CFI directives indicate a frame that we aren't prepared 546 // to represent via compact unwind, so just bail out. 547 return 0; 548 case MCCFIInstruction::OpDefCfaRegister: { 549 // Defines a frame pointer. E.g. 550 // 551 // movq %rsp, %rbp 552 // L0: 553 // .cfi_def_cfa_register %rbp 554 // 555 HasFP = true; 556 557 // If the frame pointer is other than esp/rsp, we do not have a way to 558 // generate a compact unwinding representation, so bail out. 559 if (MRI.getLLVMRegNum(Inst.getRegister(), true) != 560 (Is64Bit ? X86::RBP : X86::EBP)) 561 return 0; 562 563 // Reset the counts. 564 memset(SavedRegs, 0, sizeof(SavedRegs)); 565 StackAdjust = 0; 566 SavedRegIdx = 0; 567 InstrOffset += MoveInstrSize; 568 break; 569 } 570 case MCCFIInstruction::OpDefCfaOffset: { 571 // Defines a new offset for the CFA. E.g. 572 // 573 // With frame: 574 // 575 // pushq %rbp 576 // L0: 577 // .cfi_def_cfa_offset 16 578 // 579 // Without frame: 580 // 581 // subq $72, %rsp 582 // L0: 583 // .cfi_def_cfa_offset 80 584 // 585 PrevStackSize = StackSize; 586 StackSize = std::abs(Inst.getOffset()) / StackDivide; 587 ++NumDefCFAOffsets; 588 break; 589 } 590 case MCCFIInstruction::OpOffset: { 591 // Defines a "push" of a callee-saved register. E.g. 592 // 593 // pushq %r15 594 // pushq %r14 595 // pushq %rbx 596 // L0: 597 // subq $120, %rsp 598 // L1: 599 // .cfi_offset %rbx, -40 600 // .cfi_offset %r14, -32 601 // .cfi_offset %r15, -24 602 // 603 if (SavedRegIdx == CU_NUM_SAVED_REGS) 604 // If there are too many saved registers, we cannot use a compact 605 // unwind encoding. 606 return CU::UNWIND_MODE_DWARF; 607 608 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 609 SavedRegs[SavedRegIdx++] = Reg; 610 StackAdjust += OffsetSize; 611 InstrOffset += PushInstrSize(Reg); 612 break; 613 } 614 } 615 } 616 617 StackAdjust /= StackDivide; 618 619 if (HasFP) { 620 if ((StackAdjust & 0xFF) != StackAdjust) 621 // Offset was too big for a compact unwind encoding. 622 return CU::UNWIND_MODE_DWARF; 623 624 // Get the encoding of the saved registers when we have a frame pointer. 625 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(); 626 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 627 628 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME; 629 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16; 630 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS; 631 } else { 632 // If the amount of the stack allocation is the size of a register, then 633 // we "push" the RAX/EAX register onto the stack instead of adjusting the 634 // stack pointer with a SUB instruction. We don't support the push of the 635 // RAX/EAX register with compact unwind. So we check for that situation 636 // here. 637 if ((NumDefCFAOffsets == SavedRegIdx + 1 && 638 StackSize - PrevStackSize == 1) || 639 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2)) 640 return CU::UNWIND_MODE_DWARF; 641 642 SubtractInstrIdx += InstrOffset; 643 ++StackAdjust; 644 645 if ((StackSize & 0xFF) == StackSize) { 646 // Frameless stack with a small stack size. 647 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD; 648 649 // Encode the stack size. 650 CompactUnwindEncoding |= (StackSize & 0xFF) << 16; 651 } else { 652 if ((StackAdjust & 0x7) != StackAdjust) 653 // The extra stack adjustments are too big for us to handle. 654 return CU::UNWIND_MODE_DWARF; 655 656 // Frameless stack with an offset too large for us to encode compactly. 657 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND; 658 659 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' 660 // instruction. 661 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; 662 663 // Encode any extra stack stack adjustments (done via push 664 // instructions). 665 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13; 666 } 667 668 // Encode the number of registers saved. (Reverse the list first.) 669 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]); 670 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10; 671 672 // Get the encoding of the saved registers when we don't have a frame 673 // pointer. 674 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx); 675 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 676 677 // Encode the register encoding. 678 CompactUnwindEncoding |= 679 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION; 680 } 681 682 return CompactUnwindEncoding; 683 } 684 685 private: 686 /// \brief Get the compact unwind number for a given register. The number 687 /// corresponds to the enum lists in compact_unwind_encoding.h. 688 int getCompactUnwindRegNum(unsigned Reg) const { 689 static const MCPhysReg CU32BitRegs[7] = { 690 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 691 }; 692 static const MCPhysReg CU64BitRegs[] = { 693 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 694 }; 695 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs; 696 for (int Idx = 1; *CURegs; ++CURegs, ++Idx) 697 if (*CURegs == Reg) 698 return Idx; 699 700 return -1; 701 } 702 703 /// \brief Return the registers encoded for a compact encoding with a frame 704 /// pointer. 705 uint32_t encodeCompactUnwindRegistersWithFrame() const { 706 // Encode the registers in the order they were saved --- 3-bits per 707 // register. The list of saved registers is assumed to be in reverse 708 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS. 709 uint32_t RegEnc = 0; 710 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) { 711 unsigned Reg = SavedRegs[i]; 712 if (Reg == 0) break; 713 714 int CURegNum = getCompactUnwindRegNum(Reg); 715 if (CURegNum == -1) return ~0U; 716 717 // Encode the 3-bit register number in order, skipping over 3-bits for 718 // each register. 719 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3); 720 } 721 722 assert((RegEnc & 0x3FFFF) == RegEnc && 723 "Invalid compact register encoding!"); 724 return RegEnc; 725 } 726 727 /// \brief Create the permutation encoding used with frameless stacks. It is 728 /// passed the number of registers to be saved and an array of the registers 729 /// saved. 730 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const { 731 // The saved registers are numbered from 1 to 6. In order to encode the 732 // order in which they were saved, we re-number them according to their 733 // place in the register order. The re-numbering is relative to the last 734 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in 735 // that order: 736 // 737 // Orig Re-Num 738 // ---- ------ 739 // 6 6 740 // 2 2 741 // 4 3 742 // 5 3 743 // 744 for (unsigned i = 0; i < RegCount; ++i) { 745 int CUReg = getCompactUnwindRegNum(SavedRegs[i]); 746 if (CUReg == -1) return ~0U; 747 SavedRegs[i] = CUReg; 748 } 749 750 // Reverse the list. 751 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]); 752 753 uint32_t RenumRegs[CU_NUM_SAVED_REGS]; 754 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){ 755 unsigned Countless = 0; 756 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j) 757 if (SavedRegs[j] < SavedRegs[i]) 758 ++Countless; 759 760 RenumRegs[i] = SavedRegs[i] - Countless - 1; 761 } 762 763 // Take the renumbered values and encode them into a 10-bit number. 764 uint32_t permutationEncoding = 0; 765 switch (RegCount) { 766 case 6: 767 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] 768 + 6 * RenumRegs[2] + 2 * RenumRegs[3] 769 + RenumRegs[4]; 770 break; 771 case 5: 772 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] 773 + 6 * RenumRegs[3] + 2 * RenumRegs[4] 774 + RenumRegs[5]; 775 break; 776 case 4: 777 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] 778 + 3 * RenumRegs[4] + RenumRegs[5]; 779 break; 780 case 3: 781 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] 782 + RenumRegs[5]; 783 break; 784 case 2: 785 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; 786 break; 787 case 1: 788 permutationEncoding |= RenumRegs[5]; 789 break; 790 } 791 792 assert((permutationEncoding & 0x3FF) == permutationEncoding && 793 "Invalid compact register encoding!"); 794 return permutationEncoding; 795 } 796 797 public: 798 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, 799 const MCSubtargetInfo &STI, bool Is64Bit) 800 : X86AsmBackend(T, STI), MRI(MRI), Is64Bit(Is64Bit) { 801 memset(SavedRegs, 0, sizeof(SavedRegs)); 802 OffsetSize = Is64Bit ? 8 : 4; 803 MoveInstrSize = Is64Bit ? 3 : 2; 804 StackDivide = Is64Bit ? 8 : 4; 805 } 806 }; 807 808 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { 809 public: 810 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, 811 const MCSubtargetInfo &STI) 812 : DarwinX86AsmBackend(T, MRI, STI, false) {} 813 814 std::unique_ptr<MCObjectWriter> 815 createObjectWriter(raw_pwrite_stream &OS) const override { 816 return createX86MachObjectWriter(OS, /*Is64Bit=*/false, 817 MachO::CPU_TYPE_I386, 818 MachO::CPU_SUBTYPE_I386_ALL); 819 } 820 821 /// \brief Generate the compact unwind encoding for the CFI instructions. 822 uint32_t generateCompactUnwindEncoding( 823 ArrayRef<MCCFIInstruction> Instrs) const override { 824 return generateCompactUnwindEncodingImpl(Instrs); 825 } 826 }; 827 828 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { 829 const MachO::CPUSubTypeX86 Subtype; 830 public: 831 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, 832 const MCSubtargetInfo &STI, MachO::CPUSubTypeX86 st) 833 : DarwinX86AsmBackend(T, MRI, STI, true), Subtype(st) {} 834 835 std::unique_ptr<MCObjectWriter> 836 createObjectWriter(raw_pwrite_stream &OS) const override { 837 return createX86MachObjectWriter(OS, /*Is64Bit=*/true, 838 MachO::CPU_TYPE_X86_64, Subtype); 839 } 840 841 /// \brief Generate the compact unwind encoding for the CFI instructions. 842 uint32_t generateCompactUnwindEncoding( 843 ArrayRef<MCCFIInstruction> Instrs) const override { 844 return generateCompactUnwindEncodingImpl(Instrs); 845 } 846 }; 847 848 } // end anonymous namespace 849 850 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, 851 const MCSubtargetInfo &STI, 852 const MCRegisterInfo &MRI, 853 const MCTargetOptions &Options) { 854 const Triple &TheTriple = STI.getTargetTriple(); 855 if (TheTriple.isOSBinFormatMachO()) 856 return new DarwinX86_32AsmBackend(T, MRI, STI); 857 858 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) 859 return new WindowsX86AsmBackend(T, false, STI); 860 861 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 862 863 if (TheTriple.isOSIAMCU()) 864 return new ELFX86_IAMCUAsmBackend(T, OSABI, STI); 865 866 return new ELFX86_32AsmBackend(T, OSABI, STI); 867 } 868 869 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, 870 const MCSubtargetInfo &STI, 871 const MCRegisterInfo &MRI, 872 const MCTargetOptions &Options) { 873 const Triple &TheTriple = STI.getTargetTriple(); 874 if (TheTriple.isOSBinFormatMachO()) { 875 MachO::CPUSubTypeX86 CS = 876 StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) 877 .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H) 878 .Default(MachO::CPU_SUBTYPE_X86_64_ALL); 879 return new DarwinX86_64AsmBackend(T, MRI, STI, CS); 880 } 881 882 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) 883 return new WindowsX86AsmBackend(T, true, STI); 884 885 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 886 887 if (TheTriple.getEnvironment() == Triple::GNUX32) 888 return new ELFX86_X32AsmBackend(T, OSABI, STI); 889 return new ELFX86_64AsmBackend(T, OSABI, STI); 890 } 891