1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "MCTargetDesc/X86BaseInfo.h"
12 #include "MCTargetDesc/X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCELFObjectWriter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCFixupKindInfo.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionCOFF.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/Object/MachOFormat.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ELF.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 using namespace llvm;
30 
31 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
32 // is useful when running bitwise comparison experiments on Darwin. We should be
33 // able to remove this once PR9807 is resolved.
34 static cl::opt<bool>
35 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
36          cl::desc("Disable relaxation of arithmetic instruction for X86"));
37 
38 static unsigned getFixupKindLog2Size(unsigned Kind) {
39   switch (Kind) {
40   default: assert(0 && "invalid fixup kind!");
41   case FK_PCRel_1:
42   case FK_Data_1: return 0;
43   case FK_PCRel_2:
44   case FK_Data_2: return 1;
45   case FK_PCRel_4:
46   case X86::reloc_riprel_4byte:
47   case X86::reloc_riprel_4byte_movq_load:
48   case X86::reloc_signed_4byte:
49   case X86::reloc_global_offset_table:
50   case FK_Data_4: return 2;
51   case FK_PCRel_8:
52   case FK_Data_8: return 3;
53   }
54 }
55 
56 namespace {
57 
58 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
59 public:
60   X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
61                      bool HasRelocationAddend)
62     : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
63 };
64 
65 class X86AsmBackend : public MCAsmBackend {
66 public:
67   X86AsmBackend(const Target &T)
68     : MCAsmBackend() {}
69 
70   unsigned getNumFixupKinds() const {
71     return X86::NumTargetFixupKinds;
72   }
73 
74   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
75     const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
76       { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
77       { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
78       { "reloc_signed_4byte", 0, 4 * 8, 0},
79       { "reloc_global_offset_table", 0, 4 * 8, 0}
80     };
81 
82     if (Kind < FirstTargetFixupKind)
83       return MCAsmBackend::getFixupKindInfo(Kind);
84 
85     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
86            "Invalid kind!");
87     return Infos[Kind - FirstTargetFixupKind];
88   }
89 
90   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
91                   uint64_t Value) const {
92     unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
93 
94     assert(Fixup.getOffset() + Size <= DataSize &&
95            "Invalid fixup offset!");
96 
97     // Check that uppper bits are either all zeros or all ones.
98     // Specifically ignore overflow/underflow as long as the leakage is
99     // limited to the lower bits. This is to remain compatible with
100     // other assemblers.
101     assert(isIntN(Size * 8 + 1, Value) &&
102            "Value does not fit in the Fixup field");
103 
104     for (unsigned i = 0; i != Size; ++i)
105       Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
106   }
107 
108   bool MayNeedRelaxation(const MCInst &Inst) const;
109 
110   bool fixupNeedsRelaxation(const MCFixup &Fixup,
111                             uint64_t Value,
112                             const MCInstFragment *DF,
113                             const MCAsmLayout &Layout) const;
114 
115   void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
116 
117   bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
118 };
119 } // end anonymous namespace
120 
121 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
122   switch (Op) {
123   default:
124     return Op;
125 
126   case X86::JAE_1: return X86::JAE_4;
127   case X86::JA_1:  return X86::JA_4;
128   case X86::JBE_1: return X86::JBE_4;
129   case X86::JB_1:  return X86::JB_4;
130   case X86::JE_1:  return X86::JE_4;
131   case X86::JGE_1: return X86::JGE_4;
132   case X86::JG_1:  return X86::JG_4;
133   case X86::JLE_1: return X86::JLE_4;
134   case X86::JL_1:  return X86::JL_4;
135   case X86::JMP_1: return X86::JMP_4;
136   case X86::JNE_1: return X86::JNE_4;
137   case X86::JNO_1: return X86::JNO_4;
138   case X86::JNP_1: return X86::JNP_4;
139   case X86::JNS_1: return X86::JNS_4;
140   case X86::JO_1:  return X86::JO_4;
141   case X86::JP_1:  return X86::JP_4;
142   case X86::JS_1:  return X86::JS_4;
143   }
144 }
145 
146 static unsigned getRelaxedOpcodeArith(unsigned Op) {
147   switch (Op) {
148   default:
149     return Op;
150 
151     // IMUL
152   case X86::IMUL16rri8: return X86::IMUL16rri;
153   case X86::IMUL16rmi8: return X86::IMUL16rmi;
154   case X86::IMUL32rri8: return X86::IMUL32rri;
155   case X86::IMUL32rmi8: return X86::IMUL32rmi;
156   case X86::IMUL64rri8: return X86::IMUL64rri32;
157   case X86::IMUL64rmi8: return X86::IMUL64rmi32;
158 
159     // AND
160   case X86::AND16ri8: return X86::AND16ri;
161   case X86::AND16mi8: return X86::AND16mi;
162   case X86::AND32ri8: return X86::AND32ri;
163   case X86::AND32mi8: return X86::AND32mi;
164   case X86::AND64ri8: return X86::AND64ri32;
165   case X86::AND64mi8: return X86::AND64mi32;
166 
167     // OR
168   case X86::OR16ri8: return X86::OR16ri;
169   case X86::OR16mi8: return X86::OR16mi;
170   case X86::OR32ri8: return X86::OR32ri;
171   case X86::OR32mi8: return X86::OR32mi;
172   case X86::OR64ri8: return X86::OR64ri32;
173   case X86::OR64mi8: return X86::OR64mi32;
174 
175     // XOR
176   case X86::XOR16ri8: return X86::XOR16ri;
177   case X86::XOR16mi8: return X86::XOR16mi;
178   case X86::XOR32ri8: return X86::XOR32ri;
179   case X86::XOR32mi8: return X86::XOR32mi;
180   case X86::XOR64ri8: return X86::XOR64ri32;
181   case X86::XOR64mi8: return X86::XOR64mi32;
182 
183     // ADD
184   case X86::ADD16ri8: return X86::ADD16ri;
185   case X86::ADD16mi8: return X86::ADD16mi;
186   case X86::ADD32ri8: return X86::ADD32ri;
187   case X86::ADD32mi8: return X86::ADD32mi;
188   case X86::ADD64ri8: return X86::ADD64ri32;
189   case X86::ADD64mi8: return X86::ADD64mi32;
190 
191     // SUB
192   case X86::SUB16ri8: return X86::SUB16ri;
193   case X86::SUB16mi8: return X86::SUB16mi;
194   case X86::SUB32ri8: return X86::SUB32ri;
195   case X86::SUB32mi8: return X86::SUB32mi;
196   case X86::SUB64ri8: return X86::SUB64ri32;
197   case X86::SUB64mi8: return X86::SUB64mi32;
198 
199     // CMP
200   case X86::CMP16ri8: return X86::CMP16ri;
201   case X86::CMP16mi8: return X86::CMP16mi;
202   case X86::CMP32ri8: return X86::CMP32ri;
203   case X86::CMP32mi8: return X86::CMP32mi;
204   case X86::CMP64ri8: return X86::CMP64ri32;
205   case X86::CMP64mi8: return X86::CMP64mi32;
206 
207     // PUSH
208   case X86::PUSHi8: return X86::PUSHi32;
209   case X86::PUSHi16: return X86::PUSHi32;
210   case X86::PUSH64i8: return X86::PUSH64i32;
211   case X86::PUSH64i16: return X86::PUSH64i32;
212   }
213 }
214 
215 static unsigned getRelaxedOpcode(unsigned Op) {
216   unsigned R = getRelaxedOpcodeArith(Op);
217   if (R != Op)
218     return R;
219   return getRelaxedOpcodeBranch(Op);
220 }
221 
222 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
223   // Branches can always be relaxed.
224   if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
225     return true;
226 
227   if (MCDisableArithRelaxation)
228     return false;
229 
230   // Check if this instruction is ever relaxable.
231   if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
232     return false;
233 
234 
235   // Check if it has an expression and is not RIP relative.
236   bool hasExp = false;
237   bool hasRIP = false;
238   for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
239     const MCOperand &Op = Inst.getOperand(i);
240     if (Op.isExpr())
241       hasExp = true;
242 
243     if (Op.isReg() && Op.getReg() == X86::RIP)
244       hasRIP = true;
245   }
246 
247   // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
248   // how we do relaxations?
249   return hasExp && !hasRIP;
250 }
251 
252 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
253                                          uint64_t Value,
254                                          const MCInstFragment *DF,
255                                          const MCAsmLayout &Layout) const {
256   // Relax if the value is too big for a (signed) i8.
257   return int64_t(Value) != int64_t(int8_t(Value));
258 }
259 
260 // FIXME: Can tblgen help at all here to verify there aren't other instructions
261 // we can relax?
262 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
263   // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
264   unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
265 
266   if (RelaxedOp == Inst.getOpcode()) {
267     SmallString<256> Tmp;
268     raw_svector_ostream OS(Tmp);
269     Inst.dump_pretty(OS);
270     OS << "\n";
271     report_fatal_error("unexpected instruction to relax: " + OS.str());
272   }
273 
274   Res = Inst;
275   Res.setOpcode(RelaxedOp);
276 }
277 
278 /// WriteNopData - Write optimal nops to the output file for the \arg Count
279 /// bytes.  This returns the number of bytes written.  It may return 0 if
280 /// the \arg Count is more than the maximum optimal nops.
281 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
282   static const uint8_t Nops[10][10] = {
283     // nop
284     {0x90},
285     // xchg %ax,%ax
286     {0x66, 0x90},
287     // nopl (%[re]ax)
288     {0x0f, 0x1f, 0x00},
289     // nopl 0(%[re]ax)
290     {0x0f, 0x1f, 0x40, 0x00},
291     // nopl 0(%[re]ax,%[re]ax,1)
292     {0x0f, 0x1f, 0x44, 0x00, 0x00},
293     // nopw 0(%[re]ax,%[re]ax,1)
294     {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
295     // nopl 0L(%[re]ax)
296     {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
297     // nopl 0L(%[re]ax,%[re]ax,1)
298     {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
299     // nopw 0L(%[re]ax,%[re]ax,1)
300     {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
301     // nopw %cs:0L(%[re]ax,%[re]ax,1)
302     {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
303   };
304 
305   // Write an optimal sequence for the first 15 bytes.
306   const uint64_t OptimalCount = (Count < 16) ? Count : 15;
307   const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
308   for (uint64_t i = 0, e = Prefixes; i != e; i++)
309     OW->Write8(0x66);
310   const uint64_t Rest = OptimalCount - Prefixes;
311   for (uint64_t i = 0, e = Rest; i != e; i++)
312     OW->Write8(Nops[Rest - 1][i]);
313 
314   // Finish with single byte nops.
315   for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
316    OW->Write8(0x90);
317 
318   return true;
319 }
320 
321 /* *** */
322 
323 namespace {
324 class ELFX86AsmBackend : public X86AsmBackend {
325 public:
326   Triple::OSType OSType;
327   ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
328     : X86AsmBackend(T), OSType(_OSType) {
329     HasReliableSymbolDifference = true;
330   }
331 
332   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
333     const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
334     return ES.getFlags() & ELF::SHF_MERGE;
335   }
336 };
337 
338 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
339 public:
340   ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
341     : ELFX86AsmBackend(T, OSType) {}
342 
343   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
344     return createELFObjectWriter(createELFObjectTargetWriter(),
345                                  OS, /*IsLittleEndian*/ true);
346   }
347 
348   MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
349     return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
350   }
351 };
352 
353 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
354 public:
355   ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
356     : ELFX86AsmBackend(T, OSType) {}
357 
358   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
359     return createELFObjectWriter(createELFObjectTargetWriter(),
360                                  OS, /*IsLittleEndian*/ true);
361   }
362 
363   MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
364     return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
365   }
366 };
367 
368 class WindowsX86AsmBackend : public X86AsmBackend {
369   bool Is64Bit;
370 
371 public:
372   WindowsX86AsmBackend(const Target &T, bool is64Bit)
373     : X86AsmBackend(T)
374     , Is64Bit(is64Bit) {
375   }
376 
377   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
378     return createWinCOFFObjectWriter(OS, Is64Bit);
379   }
380 };
381 
382 class DarwinX86AsmBackend : public X86AsmBackend {
383 public:
384   DarwinX86AsmBackend(const Target &T)
385     : X86AsmBackend(T) { }
386 };
387 
388 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
389 public:
390   DarwinX86_32AsmBackend(const Target &T)
391     : DarwinX86AsmBackend(T) {}
392 
393   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
394     return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
395                                      object::mach::CTM_i386,
396                                      object::mach::CSX86_ALL);
397   }
398 };
399 
400 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
401 public:
402   DarwinX86_64AsmBackend(const Target &T)
403     : DarwinX86AsmBackend(T) {
404     HasReliableSymbolDifference = true;
405   }
406 
407   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
408     return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
409                                      object::mach::CTM_x86_64,
410                                      object::mach::CSX86_ALL);
411   }
412 
413   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
414     // Temporary labels in the string literals sections require symbols. The
415     // issue is that the x86_64 relocation format does not allow symbol +
416     // offset, and so the linker does not have enough information to resolve the
417     // access to the appropriate atom unless an external relocation is used. For
418     // non-cstring sections, we expect the compiler to use a non-temporary label
419     // for anything that could have an addend pointing outside the symbol.
420     //
421     // See <rdar://problem/4765733>.
422     const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
423     return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
424   }
425 
426   virtual bool isSectionAtomizable(const MCSection &Section) const {
427     const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
428     // Fixed sized data sections are uniqued, they cannot be diced into atoms.
429     switch (SMO.getType()) {
430     default:
431       return true;
432 
433     case MCSectionMachO::S_4BYTE_LITERALS:
434     case MCSectionMachO::S_8BYTE_LITERALS:
435     case MCSectionMachO::S_16BYTE_LITERALS:
436     case MCSectionMachO::S_LITERAL_POINTERS:
437     case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
438     case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
439     case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
440     case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
441     case MCSectionMachO::S_INTERPOSING:
442       return false;
443     }
444   }
445 };
446 
447 } // end anonymous namespace
448 
449 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT) {
450   Triple TheTriple(TT);
451 
452   if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
453     return new DarwinX86_32AsmBackend(T);
454 
455   if (TheTriple.isOSWindows())
456     return new WindowsX86AsmBackend(T, false);
457 
458   return new ELFX86_32AsmBackend(T, TheTriple.getOS());
459 }
460 
461 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT) {
462   Triple TheTriple(TT);
463 
464   if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
465     return new DarwinX86_64AsmBackend(T);
466 
467   if (TheTriple.isOSWindows())
468     return new WindowsX86AsmBackend(T, true);
469 
470   return new ELFX86_64AsmBackend(T, TheTriple.getOS());
471 }
472