1 //===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains the public interface of the instruction decoder. 12 // Documentation for the disassembler can be found in X86Disassembler.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef X86DISASSEMBLERDECODER_H 17 #define X86DISASSEMBLERDECODER_H 18 19 #include "X86DisassemblerDecoderCommon.h" 20 21 namespace llvm { 22 namespace X86Disassembler { 23 24 // Accessor functions for various fields of an Intel instruction 25 #define modFromModRM(modRM) (((modRM) & 0xc0) >> 6) 26 #define regFromModRM(modRM) (((modRM) & 0x38) >> 3) 27 #define rmFromModRM(modRM) ((modRM) & 0x7) 28 #define scaleFromSIB(sib) (((sib) & 0xc0) >> 6) 29 #define indexFromSIB(sib) (((sib) & 0x38) >> 3) 30 #define baseFromSIB(sib) ((sib) & 0x7) 31 #define wFromREX(rex) (((rex) & 0x8) >> 3) 32 #define rFromREX(rex) (((rex) & 0x4) >> 2) 33 #define xFromREX(rex) (((rex) & 0x2) >> 1) 34 #define bFromREX(rex) ((rex) & 0x1) 35 36 #define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7) 37 #define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6) 38 #define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5) 39 #define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4) 40 #define mmFromEVEX2of4(evex) ((evex) & 0x3) 41 #define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7) 42 #define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3) 43 #define ppFromEVEX3of4(evex) ((evex) & 0x3) 44 #define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7) 45 #define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6) 46 #define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5) 47 #define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4) 48 #define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3) 49 #define aaaFromEVEX4of4(evex) ((evex) & 0x7) 50 51 #define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7) 52 #define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6) 53 #define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5) 54 #define mmmmmFromVEX2of3(vex) ((vex) & 0x1f) 55 #define wFromVEX3of3(vex) (((vex) & 0x80) >> 7) 56 #define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3) 57 #define lFromVEX3of3(vex) (((vex) & 0x4) >> 2) 58 #define ppFromVEX3of3(vex) ((vex) & 0x3) 59 60 #define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7) 61 #define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3) 62 #define lFromVEX2of2(vex) (((vex) & 0x4) >> 2) 63 #define ppFromVEX2of2(vex) ((vex) & 0x3) 64 65 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) 66 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) 67 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) 68 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) 69 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) 70 #define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3) 71 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) 72 #define ppFromXOP3of3(xop) ((xop) & 0x3) 73 74 // These enums represent Intel registers for use by the decoder. 75 #define REGS_8BIT \ 76 ENTRY(AL) \ 77 ENTRY(CL) \ 78 ENTRY(DL) \ 79 ENTRY(BL) \ 80 ENTRY(AH) \ 81 ENTRY(CH) \ 82 ENTRY(DH) \ 83 ENTRY(BH) \ 84 ENTRY(R8B) \ 85 ENTRY(R9B) \ 86 ENTRY(R10B) \ 87 ENTRY(R11B) \ 88 ENTRY(R12B) \ 89 ENTRY(R13B) \ 90 ENTRY(R14B) \ 91 ENTRY(R15B) \ 92 ENTRY(SPL) \ 93 ENTRY(BPL) \ 94 ENTRY(SIL) \ 95 ENTRY(DIL) 96 97 #define EA_BASES_16BIT \ 98 ENTRY(BX_SI) \ 99 ENTRY(BX_DI) \ 100 ENTRY(BP_SI) \ 101 ENTRY(BP_DI) \ 102 ENTRY(SI) \ 103 ENTRY(DI) \ 104 ENTRY(BP) \ 105 ENTRY(BX) \ 106 ENTRY(R8W) \ 107 ENTRY(R9W) \ 108 ENTRY(R10W) \ 109 ENTRY(R11W) \ 110 ENTRY(R12W) \ 111 ENTRY(R13W) \ 112 ENTRY(R14W) \ 113 ENTRY(R15W) 114 115 #define REGS_16BIT \ 116 ENTRY(AX) \ 117 ENTRY(CX) \ 118 ENTRY(DX) \ 119 ENTRY(BX) \ 120 ENTRY(SP) \ 121 ENTRY(BP) \ 122 ENTRY(SI) \ 123 ENTRY(DI) \ 124 ENTRY(R8W) \ 125 ENTRY(R9W) \ 126 ENTRY(R10W) \ 127 ENTRY(R11W) \ 128 ENTRY(R12W) \ 129 ENTRY(R13W) \ 130 ENTRY(R14W) \ 131 ENTRY(R15W) 132 133 #define EA_BASES_32BIT \ 134 ENTRY(EAX) \ 135 ENTRY(ECX) \ 136 ENTRY(EDX) \ 137 ENTRY(EBX) \ 138 ENTRY(sib) \ 139 ENTRY(EBP) \ 140 ENTRY(ESI) \ 141 ENTRY(EDI) \ 142 ENTRY(R8D) \ 143 ENTRY(R9D) \ 144 ENTRY(R10D) \ 145 ENTRY(R11D) \ 146 ENTRY(R12D) \ 147 ENTRY(R13D) \ 148 ENTRY(R14D) \ 149 ENTRY(R15D) 150 151 #define REGS_32BIT \ 152 ENTRY(EAX) \ 153 ENTRY(ECX) \ 154 ENTRY(EDX) \ 155 ENTRY(EBX) \ 156 ENTRY(ESP) \ 157 ENTRY(EBP) \ 158 ENTRY(ESI) \ 159 ENTRY(EDI) \ 160 ENTRY(R8D) \ 161 ENTRY(R9D) \ 162 ENTRY(R10D) \ 163 ENTRY(R11D) \ 164 ENTRY(R12D) \ 165 ENTRY(R13D) \ 166 ENTRY(R14D) \ 167 ENTRY(R15D) 168 169 #define EA_BASES_64BIT \ 170 ENTRY(RAX) \ 171 ENTRY(RCX) \ 172 ENTRY(RDX) \ 173 ENTRY(RBX) \ 174 ENTRY(sib64) \ 175 ENTRY(RBP) \ 176 ENTRY(RSI) \ 177 ENTRY(RDI) \ 178 ENTRY(R8) \ 179 ENTRY(R9) \ 180 ENTRY(R10) \ 181 ENTRY(R11) \ 182 ENTRY(R12) \ 183 ENTRY(R13) \ 184 ENTRY(R14) \ 185 ENTRY(R15) 186 187 #define REGS_64BIT \ 188 ENTRY(RAX) \ 189 ENTRY(RCX) \ 190 ENTRY(RDX) \ 191 ENTRY(RBX) \ 192 ENTRY(RSP) \ 193 ENTRY(RBP) \ 194 ENTRY(RSI) \ 195 ENTRY(RDI) \ 196 ENTRY(R8) \ 197 ENTRY(R9) \ 198 ENTRY(R10) \ 199 ENTRY(R11) \ 200 ENTRY(R12) \ 201 ENTRY(R13) \ 202 ENTRY(R14) \ 203 ENTRY(R15) 204 205 #define REGS_MMX \ 206 ENTRY(MM0) \ 207 ENTRY(MM1) \ 208 ENTRY(MM2) \ 209 ENTRY(MM3) \ 210 ENTRY(MM4) \ 211 ENTRY(MM5) \ 212 ENTRY(MM6) \ 213 ENTRY(MM7) 214 215 #define REGS_XMM \ 216 ENTRY(XMM0) \ 217 ENTRY(XMM1) \ 218 ENTRY(XMM2) \ 219 ENTRY(XMM3) \ 220 ENTRY(XMM4) \ 221 ENTRY(XMM5) \ 222 ENTRY(XMM6) \ 223 ENTRY(XMM7) \ 224 ENTRY(XMM8) \ 225 ENTRY(XMM9) \ 226 ENTRY(XMM10) \ 227 ENTRY(XMM11) \ 228 ENTRY(XMM12) \ 229 ENTRY(XMM13) \ 230 ENTRY(XMM14) \ 231 ENTRY(XMM15) \ 232 ENTRY(XMM16) \ 233 ENTRY(XMM17) \ 234 ENTRY(XMM18) \ 235 ENTRY(XMM19) \ 236 ENTRY(XMM20) \ 237 ENTRY(XMM21) \ 238 ENTRY(XMM22) \ 239 ENTRY(XMM23) \ 240 ENTRY(XMM24) \ 241 ENTRY(XMM25) \ 242 ENTRY(XMM26) \ 243 ENTRY(XMM27) \ 244 ENTRY(XMM28) \ 245 ENTRY(XMM29) \ 246 ENTRY(XMM30) \ 247 ENTRY(XMM31) 248 249 #define REGS_YMM \ 250 ENTRY(YMM0) \ 251 ENTRY(YMM1) \ 252 ENTRY(YMM2) \ 253 ENTRY(YMM3) \ 254 ENTRY(YMM4) \ 255 ENTRY(YMM5) \ 256 ENTRY(YMM6) \ 257 ENTRY(YMM7) \ 258 ENTRY(YMM8) \ 259 ENTRY(YMM9) \ 260 ENTRY(YMM10) \ 261 ENTRY(YMM11) \ 262 ENTRY(YMM12) \ 263 ENTRY(YMM13) \ 264 ENTRY(YMM14) \ 265 ENTRY(YMM15) \ 266 ENTRY(YMM16) \ 267 ENTRY(YMM17) \ 268 ENTRY(YMM18) \ 269 ENTRY(YMM19) \ 270 ENTRY(YMM20) \ 271 ENTRY(YMM21) \ 272 ENTRY(YMM22) \ 273 ENTRY(YMM23) \ 274 ENTRY(YMM24) \ 275 ENTRY(YMM25) \ 276 ENTRY(YMM26) \ 277 ENTRY(YMM27) \ 278 ENTRY(YMM28) \ 279 ENTRY(YMM29) \ 280 ENTRY(YMM30) \ 281 ENTRY(YMM31) 282 283 #define REGS_ZMM \ 284 ENTRY(ZMM0) \ 285 ENTRY(ZMM1) \ 286 ENTRY(ZMM2) \ 287 ENTRY(ZMM3) \ 288 ENTRY(ZMM4) \ 289 ENTRY(ZMM5) \ 290 ENTRY(ZMM6) \ 291 ENTRY(ZMM7) \ 292 ENTRY(ZMM8) \ 293 ENTRY(ZMM9) \ 294 ENTRY(ZMM10) \ 295 ENTRY(ZMM11) \ 296 ENTRY(ZMM12) \ 297 ENTRY(ZMM13) \ 298 ENTRY(ZMM14) \ 299 ENTRY(ZMM15) \ 300 ENTRY(ZMM16) \ 301 ENTRY(ZMM17) \ 302 ENTRY(ZMM18) \ 303 ENTRY(ZMM19) \ 304 ENTRY(ZMM20) \ 305 ENTRY(ZMM21) \ 306 ENTRY(ZMM22) \ 307 ENTRY(ZMM23) \ 308 ENTRY(ZMM24) \ 309 ENTRY(ZMM25) \ 310 ENTRY(ZMM26) \ 311 ENTRY(ZMM27) \ 312 ENTRY(ZMM28) \ 313 ENTRY(ZMM29) \ 314 ENTRY(ZMM30) \ 315 ENTRY(ZMM31) 316 317 #define REGS_MASKS \ 318 ENTRY(K0) \ 319 ENTRY(K1) \ 320 ENTRY(K2) \ 321 ENTRY(K3) \ 322 ENTRY(K4) \ 323 ENTRY(K5) \ 324 ENTRY(K6) \ 325 ENTRY(K7) 326 327 #define REGS_SEGMENT \ 328 ENTRY(ES) \ 329 ENTRY(CS) \ 330 ENTRY(SS) \ 331 ENTRY(DS) \ 332 ENTRY(FS) \ 333 ENTRY(GS) 334 335 #define REGS_DEBUG \ 336 ENTRY(DR0) \ 337 ENTRY(DR1) \ 338 ENTRY(DR2) \ 339 ENTRY(DR3) \ 340 ENTRY(DR4) \ 341 ENTRY(DR5) \ 342 ENTRY(DR6) \ 343 ENTRY(DR7) 344 345 #define REGS_CONTROL \ 346 ENTRY(CR0) \ 347 ENTRY(CR1) \ 348 ENTRY(CR2) \ 349 ENTRY(CR3) \ 350 ENTRY(CR4) \ 351 ENTRY(CR5) \ 352 ENTRY(CR6) \ 353 ENTRY(CR7) \ 354 ENTRY(CR8) 355 356 #define ALL_EA_BASES \ 357 EA_BASES_16BIT \ 358 EA_BASES_32BIT \ 359 EA_BASES_64BIT 360 361 #define ALL_SIB_BASES \ 362 REGS_32BIT \ 363 REGS_64BIT 364 365 #define ALL_REGS \ 366 REGS_8BIT \ 367 REGS_16BIT \ 368 REGS_32BIT \ 369 REGS_64BIT \ 370 REGS_MMX \ 371 REGS_XMM \ 372 REGS_YMM \ 373 REGS_ZMM \ 374 REGS_MASKS \ 375 REGS_SEGMENT \ 376 REGS_DEBUG \ 377 REGS_CONTROL \ 378 ENTRY(RIP) 379 380 /// \brief All possible values of the base field for effective-address 381 /// computations, a.k.a. the Mod and R/M fields of the ModR/M byte. 382 /// We distinguish between bases (EA_BASE_*) and registers that just happen 383 /// to be referred to when Mod == 0b11 (EA_REG_*). 384 enum EABase { 385 EA_BASE_NONE, 386 #define ENTRY(x) EA_BASE_##x, 387 ALL_EA_BASES 388 #undef ENTRY 389 #define ENTRY(x) EA_REG_##x, 390 ALL_REGS 391 #undef ENTRY 392 EA_max 393 }; 394 395 /// \brief All possible values of the SIB index field. 396 /// borrows entries from ALL_EA_BASES with the special case that 397 /// sib is synonymous with NONE. 398 /// Vector SIB: index can be XMM or YMM. 399 enum SIBIndex { 400 SIB_INDEX_NONE, 401 #define ENTRY(x) SIB_INDEX_##x, 402 ALL_EA_BASES 403 REGS_XMM 404 REGS_YMM 405 REGS_ZMM 406 #undef ENTRY 407 SIB_INDEX_max 408 }; 409 410 /// \brief All possible values of the SIB base field. 411 enum SIBBase { 412 SIB_BASE_NONE, 413 #define ENTRY(x) SIB_BASE_##x, 414 ALL_SIB_BASES 415 #undef ENTRY 416 SIB_BASE_max 417 }; 418 419 /// \brief Possible displacement types for effective-address computations. 420 typedef enum { 421 EA_DISP_NONE, 422 EA_DISP_8, 423 EA_DISP_16, 424 EA_DISP_32 425 } EADisplacement; 426 427 /// \brief All possible values of the reg field in the ModR/M byte. 428 enum Reg { 429 #define ENTRY(x) MODRM_REG_##x, 430 ALL_REGS 431 #undef ENTRY 432 MODRM_REG_max 433 }; 434 435 /// \brief All possible segment overrides. 436 enum SegmentOverride { 437 SEG_OVERRIDE_NONE, 438 SEG_OVERRIDE_CS, 439 SEG_OVERRIDE_SS, 440 SEG_OVERRIDE_DS, 441 SEG_OVERRIDE_ES, 442 SEG_OVERRIDE_FS, 443 SEG_OVERRIDE_GS, 444 SEG_OVERRIDE_max 445 }; 446 447 /// \brief Possible values for the VEX.m-mmmm field 448 enum VEXLeadingOpcodeByte { 449 VEX_LOB_0F = 0x1, 450 VEX_LOB_0F38 = 0x2, 451 VEX_LOB_0F3A = 0x3 452 }; 453 454 enum XOPMapSelect { 455 XOP_MAP_SELECT_8 = 0x8, 456 XOP_MAP_SELECT_9 = 0x9, 457 XOP_MAP_SELECT_A = 0xA 458 }; 459 460 /// \brief Possible values for the VEX.pp/EVEX.pp field 461 enum VEXPrefixCode { 462 VEX_PREFIX_NONE = 0x0, 463 VEX_PREFIX_66 = 0x1, 464 VEX_PREFIX_F3 = 0x2, 465 VEX_PREFIX_F2 = 0x3 466 }; 467 468 enum VectorExtensionType { 469 TYPE_NO_VEX_XOP = 0x0, 470 TYPE_VEX_2B = 0x1, 471 TYPE_VEX_3B = 0x2, 472 TYPE_EVEX = 0x3, 473 TYPE_XOP = 0x4 474 }; 475 476 /// \brief Type for the byte reader that the consumer must provide to 477 /// the decoder. Reads a single byte from the instruction's address space. 478 /// \param arg A baton that the consumer can associate with any internal 479 /// state that it needs. 480 /// \param byte A pointer to a single byte in memory that should be set to 481 /// contain the value at address. 482 /// \param address The address in the instruction's address space that should 483 /// be read from. 484 /// \return -1 if the byte cannot be read for any reason; 0 otherwise. 485 typedef int (*byteReader_t)(const void *arg, uint8_t *byte, uint64_t address); 486 487 /// \brief Type for the logging function that the consumer can provide to 488 /// get debugging output from the decoder. 489 /// \param arg A baton that the consumer can associate with any internal 490 /// state that it needs. 491 /// \param log A string that contains the message. Will be reused after 492 /// the logger returns. 493 typedef void (*dlog_t)(void *arg, const char *log); 494 495 /// The specification for how to extract and interpret a full instruction and 496 /// its operands. 497 struct InstructionSpecifier { 498 uint16_t operands; 499 }; 500 501 /// The x86 internal instruction, which is produced by the decoder. 502 struct InternalInstruction { 503 // Reader interface (C) 504 byteReader_t reader; 505 // Opaque value passed to the reader 506 const void* readerArg; 507 // The address of the next byte to read via the reader 508 uint64_t readerCursor; 509 510 // Logger interface (C) 511 dlog_t dlog; 512 // Opaque value passed to the logger 513 void* dlogArg; 514 515 // General instruction information 516 517 // The mode to disassemble for (64-bit, protected, real) 518 DisassemblerMode mode; 519 // The start of the instruction, usable with the reader 520 uint64_t startLocation; 521 // The length of the instruction, in bytes 522 size_t length; 523 524 // Prefix state 525 526 // 1 if the prefix byte corresponding to the entry is present; 0 if not 527 uint8_t prefixPresent[0x100]; 528 // contains the location (for use with the reader) of the prefix byte 529 uint64_t prefixLocations[0x100]; 530 // The value of the vector extension prefix(EVEX/VEX/XOP), if present 531 uint8_t vectorExtensionPrefix[4]; 532 // The type of the vector extension prefix 533 VectorExtensionType vectorExtensionType; 534 // The value of the REX prefix, if present 535 uint8_t rexPrefix; 536 // The location where a mandatory prefix would have to be (i.e., right before 537 // the opcode, or right before the REX prefix if one is present). 538 uint64_t necessaryPrefixLocation; 539 // The segment override type 540 SegmentOverride segmentOverride; 541 // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease 542 bool xAcquireRelease; 543 544 // Sizes of various critical pieces of data, in bytes 545 uint8_t registerSize; 546 uint8_t addressSize; 547 uint8_t displacementSize; 548 uint8_t immediateSize; 549 550 // Offsets from the start of the instruction to the pieces of data, which is 551 // needed to find relocation entries for adding symbolic operands. 552 uint8_t displacementOffset; 553 uint8_t immediateOffset; 554 555 // opcode state 556 557 // The last byte of the opcode, not counting any ModR/M extension 558 uint8_t opcode; 559 // The ModR/M byte of the instruction, if it is an opcode extension 560 uint8_t modRMExtension; 561 562 // decode state 563 564 // The type of opcode, used for indexing into the array of decode tables 565 OpcodeType opcodeType; 566 // The instruction ID, extracted from the decode table 567 uint16_t instructionID; 568 // The specifier for the instruction, from the instruction info table 569 const InstructionSpecifier *spec; 570 571 // state for additional bytes, consumed during operand decode. Pattern: 572 // consumed___ indicates that the byte was already consumed and does not 573 // need to be consumed again. 574 575 // The VEX.vvvv field, which contains a third register operand for some AVX 576 // instructions. 577 Reg vvvv; 578 579 // The writemask for AVX-512 instructions which is contained in EVEX.aaa 580 Reg writemask; 581 582 // The ModR/M byte, which contains most register operands and some portion of 583 // all memory operands. 584 bool consumedModRM; 585 uint8_t modRM; 586 587 // The SIB byte, used for more complex 32- or 64-bit memory operands 588 bool consumedSIB; 589 uint8_t sib; 590 591 // The displacement, used for memory operands 592 bool consumedDisplacement; 593 int32_t displacement; 594 595 // Immediates. There can be two in some cases 596 uint8_t numImmediatesConsumed; 597 uint8_t numImmediatesTranslated; 598 uint64_t immediates[2]; 599 600 // A register or immediate operand encoded into the opcode 601 Reg opcodeRegister; 602 603 // Portions of the ModR/M byte 604 605 // These fields determine the allowable values for the ModR/M fields, which 606 // depend on operand and address widths. 607 EABase eaBaseBase; 608 EABase eaRegBase; 609 Reg regBase; 610 611 // The Mod and R/M fields can encode a base for an effective address, or a 612 // register. These are separated into two fields here. 613 EABase eaBase; 614 EADisplacement eaDisplacement; 615 // The reg field always encodes a register 616 Reg reg; 617 618 // SIB state 619 SIBIndex sibIndex; 620 uint8_t sibScale; 621 SIBBase sibBase; 622 623 const OperandSpecifier *operands; 624 }; 625 626 /// \brief Decode one instruction and store the decoding results in 627 /// a buffer provided by the consumer. 628 /// \param insn The buffer to store the instruction in. Allocated by the 629 /// consumer. 630 /// \param reader The byteReader_t for the bytes to be read. 631 /// \param readerArg An argument to pass to the reader for storing context 632 /// specific to the consumer. May be NULL. 633 /// \param logger The dlog_t to be used in printing status messages from the 634 /// disassembler. May be NULL. 635 /// \param loggerArg An argument to pass to the logger for storing context 636 /// specific to the logger. May be NULL. 637 /// \param startLoc The address (in the reader's address space) of the first 638 /// byte in the instruction. 639 /// \param mode The mode (16-bit, 32-bit, 64-bit) to decode in. 640 /// \return Nonzero if there was an error during decode, 0 otherwise. 641 int decodeInstruction(InternalInstruction *insn, 642 byteReader_t reader, 643 const void *readerArg, 644 dlog_t logger, 645 void *loggerArg, 646 const void *miiArg, 647 uint64_t startLoc, 648 DisassemblerMode mode); 649 650 /// \brief Print a message to debugs() 651 /// \param file The name of the file printing the debug message. 652 /// \param line The line number that printed the debug message. 653 /// \param s The message to print. 654 void Debug(const char *file, unsigned line, const char *s); 655 656 const char *GetInstrName(unsigned Opcode, const void *mii); 657 658 } // namespace X86Disassembler 659 } // namespace llvm 660 661 #endif 662