1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // Documentation for the disassembler can be found in X86Disassembler.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86Disassembler.h" 18 #include "X86DisassemblerDecoder.h" 19 20 #include "llvm/MC/EDInstInfo.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCDisassembler.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/MemoryObject.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 #define GET_REGINFO_ENUM 33 #include "X86GenRegisterInfo.inc" 34 #define GET_INSTRINFO_ENUM 35 #include "X86GenInstrInfo.inc" 36 #include "X86GenEDInfo.inc" 37 38 using namespace llvm; 39 using namespace llvm::X86Disassembler; 40 41 void x86DisassemblerDebug(const char *file, 42 unsigned line, 43 const char *s) { 44 dbgs() << file << ":" << line << ": " << s; 45 } 46 47 const char *x86DisassemblerGetInstrName(unsigned Opcode, void *mii) { 48 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii); 49 return MII->getName(Opcode); 50 } 51 52 #define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s)); 53 54 namespace llvm { 55 56 // Fill-ins to make the compiler happy. These constants are never actually 57 // assigned; they are just filler to make an automatically-generated switch 58 // statement work. 59 namespace X86 { 60 enum { 61 BX_SI = 500, 62 BX_DI = 501, 63 BP_SI = 502, 64 BP_DI = 503, 65 sib = 504, 66 sib64 = 505 67 }; 68 } 69 70 extern Target TheX86_32Target, TheX86_64Target; 71 72 } 73 74 static bool translateInstruction(MCInst &target, 75 InternalInstruction &source, 76 const MCDisassembler *Dis); 77 78 X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI, 79 DisassemblerMode mode, 80 const MCInstrInfo *MII) 81 : MCDisassembler(STI), MII(MII), fMode(mode) {} 82 83 X86GenericDisassembler::~X86GenericDisassembler() { 84 delete MII; 85 } 86 87 const EDInstInfo *X86GenericDisassembler::getEDInfo() const { 88 return instInfoX86; 89 } 90 91 /// regionReader - a callback function that wraps the readByte method from 92 /// MemoryObject. 93 /// 94 /// @param arg - The generic callback parameter. In this case, this should 95 /// be a pointer to a MemoryObject. 96 /// @param byte - A pointer to the byte to be read. 97 /// @param address - The address to be read. 98 static int regionReader(void* arg, uint8_t* byte, uint64_t address) { 99 MemoryObject* region = static_cast<MemoryObject*>(arg); 100 return region->readByte(address, byte); 101 } 102 103 /// logger - a callback function that wraps the operator<< method from 104 /// raw_ostream. 105 /// 106 /// @param arg - The generic callback parameter. This should be a pointe 107 /// to a raw_ostream. 108 /// @param log - A string to be logged. logger() adds a newline. 109 static void logger(void* arg, const char* log) { 110 if (!arg) 111 return; 112 113 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 114 vStream << log << "\n"; 115 } 116 117 // 118 // Public interface for the disassembler 119 // 120 121 MCDisassembler::DecodeStatus 122 X86GenericDisassembler::getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const { 128 CommentStream = &cStream; 129 130 InternalInstruction internalInstr; 131 132 dlog_t loggerFn = logger; 133 if (&vStream == &nulls()) 134 loggerFn = 0; // Disable logging completely if it's going to nulls(). 135 136 int ret = decodeInstruction(&internalInstr, 137 regionReader, 138 (void*)®ion, 139 loggerFn, 140 (void*)&vStream, 141 (void*)MII, 142 address, 143 fMode); 144 145 if (ret) { 146 size = internalInstr.readerCursor - address; 147 return Fail; 148 } 149 else { 150 size = internalInstr.length; 151 return (!translateInstruction(instr, internalInstr, this)) ? 152 Success : Fail; 153 } 154 } 155 156 // 157 // Private code that translates from struct InternalInstructions to MCInsts. 158 // 159 160 /// translateRegister - Translates an internal register to the appropriate LLVM 161 /// register, and appends it as an operand to an MCInst. 162 /// 163 /// @param mcInst - The MCInst to append to. 164 /// @param reg - The Reg to append. 165 static void translateRegister(MCInst &mcInst, Reg reg) { 166 #define ENTRY(x) X86::x, 167 uint8_t llvmRegnums[] = { 168 ALL_REGS 169 0 170 }; 171 #undef ENTRY 172 173 uint8_t llvmRegnum = llvmRegnums[reg]; 174 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 175 } 176 177 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 178 /// immediate Value in the MCInst. 179 /// 180 /// @param Value - The immediate Value, has had any PC adjustment made by 181 /// the caller. 182 /// @param isBranch - If the instruction is a branch instruction 183 /// @param Address - The starting address of the instruction 184 /// @param Offset - The byte offset to this immediate in the instruction 185 /// @param Width - The byte width of this immediate in the instruction 186 /// 187 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was 188 /// called then that function is called to get any symbolic information for the 189 /// immediate in the instruction using the Address, Offset and Width. If that 190 /// returns non-zero then the symbolic information it returns is used to create 191 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo() 192 /// returns zero and isBranch is true then a symbol look up for immediate Value 193 /// is done and if a symbol is found an MCExpr is created with that, else 194 /// an MCExpr with the immediate Value is created. This function returns true 195 /// if it adds an operand to the MCInst and false otherwise. 196 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 197 uint64_t Address, uint64_t Offset, 198 uint64_t Width, MCInst &MI, 199 const MCDisassembler *Dis) { 200 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 201 struct LLVMOpInfo1 SymbolicOp; 202 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 203 SymbolicOp.Value = Value; 204 void *DisInfo = Dis->getDisInfoBlock(); 205 206 if (!getOpInfo || 207 !getOpInfo(DisInfo, Address, Offset, Width, 1, &SymbolicOp)) { 208 // Clear SymbolicOp.Value from above and also all other fields. 209 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 210 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 211 if (!SymbolLookUp) 212 return false; 213 uint64_t ReferenceType; 214 if (isBranch) 215 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 216 else 217 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 218 const char *ReferenceName; 219 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 220 &ReferenceName); 221 if (Name) { 222 SymbolicOp.AddSymbol.Name = Name; 223 SymbolicOp.AddSymbol.Present = true; 224 } 225 // For branches always create an MCExpr so it gets printed as hex address. 226 else if (isBranch) { 227 SymbolicOp.Value = Value; 228 } 229 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 230 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 231 if (!Name && !isBranch) 232 return false; 233 } 234 235 MCContext *Ctx = Dis->getMCContext(); 236 const MCExpr *Add = NULL; 237 if (SymbolicOp.AddSymbol.Present) { 238 if (SymbolicOp.AddSymbol.Name) { 239 StringRef Name(SymbolicOp.AddSymbol.Name); 240 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 241 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 242 } else { 243 Add = MCConstantExpr::Create((int)SymbolicOp.AddSymbol.Value, *Ctx); 244 } 245 } 246 247 const MCExpr *Sub = NULL; 248 if (SymbolicOp.SubtractSymbol.Present) { 249 if (SymbolicOp.SubtractSymbol.Name) { 250 StringRef Name(SymbolicOp.SubtractSymbol.Name); 251 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 252 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 253 } else { 254 Sub = MCConstantExpr::Create((int)SymbolicOp.SubtractSymbol.Value, *Ctx); 255 } 256 } 257 258 const MCExpr *Off = NULL; 259 if (SymbolicOp.Value != 0) 260 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 261 262 const MCExpr *Expr; 263 if (Sub) { 264 const MCExpr *LHS; 265 if (Add) 266 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 267 else 268 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 269 if (Off != 0) 270 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 271 else 272 Expr = LHS; 273 } else if (Add) { 274 if (Off != 0) 275 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 276 else 277 Expr = Add; 278 } else { 279 if (Off != 0) 280 Expr = Off; 281 else 282 Expr = MCConstantExpr::Create(0, *Ctx); 283 } 284 285 MI.addOperand(MCOperand::CreateExpr(Expr)); 286 287 return true; 288 } 289 290 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 291 /// referenced by a load instruction with the base register that is the rip. 292 /// These can often be addresses in a literal pool. The Address of the 293 /// instruction and its immediate Value are used to determine the address 294 /// being referenced in the literal pool entry. The SymbolLookUp call back will 295 /// return a pointer to a literal 'C' string if the referenced address is an 296 /// address into a section with 'C' string literals. 297 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, 298 const void *Decoder) { 299 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 300 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 301 if (SymbolLookUp) { 302 void *DisInfo = Dis->getDisInfoBlock(); 303 uint64_t ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 304 const char *ReferenceName; 305 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 306 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 307 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 308 } 309 } 310 311 /// translateImmediate - Appends an immediate operand to an MCInst. 312 /// 313 /// @param mcInst - The MCInst to append to. 314 /// @param immediate - The immediate value to append. 315 /// @param operand - The operand, as stored in the descriptor table. 316 /// @param insn - The internal instruction. 317 static void translateImmediate(MCInst &mcInst, uint64_t immediate, 318 const OperandSpecifier &operand, 319 InternalInstruction &insn, 320 const MCDisassembler *Dis) { 321 // Sign-extend the immediate if necessary. 322 323 OperandType type = (OperandType)operand.type; 324 325 if (type == TYPE_RELv) { 326 switch (insn.displacementSize) { 327 default: 328 break; 329 case 1: 330 type = TYPE_MOFFS8; 331 break; 332 case 2: 333 type = TYPE_MOFFS16; 334 break; 335 case 4: 336 type = TYPE_MOFFS32; 337 break; 338 case 8: 339 type = TYPE_MOFFS64; 340 break; 341 } 342 } 343 // By default sign-extend all X86 immediates based on their encoding. 344 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || 345 type == TYPE_IMM64) { 346 uint32_t Opcode = mcInst.getOpcode(); 347 switch (operand.encoding) { 348 default: 349 break; 350 case ENCODING_IB: 351 // Special case those X86 instructions that use the imm8 as a set of 352 // bits, bit count, etc. and are not sign-extend. 353 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri && 354 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri && 355 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri && 356 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri && 357 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri && 358 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri && 359 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri && 360 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri && 361 Opcode != X86::VINSERTPSrr) 362 type = TYPE_MOFFS8; 363 break; 364 case ENCODING_IW: 365 type = TYPE_MOFFS16; 366 break; 367 case ENCODING_ID: 368 type = TYPE_MOFFS32; 369 break; 370 case ENCODING_IO: 371 type = TYPE_MOFFS64; 372 break; 373 } 374 } 375 376 bool isBranch = false; 377 uint64_t pcrel = 0; 378 switch (type) { 379 case TYPE_XMM128: 380 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); 381 return; 382 case TYPE_XMM256: 383 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); 384 return; 385 case TYPE_REL8: 386 isBranch = true; 387 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 388 // fall through to sign extend the immediate if needed. 389 case TYPE_MOFFS8: 390 if(immediate & 0x80) 391 immediate |= ~(0xffull); 392 break; 393 case TYPE_MOFFS16: 394 if(immediate & 0x8000) 395 immediate |= ~(0xffffull); 396 break; 397 case TYPE_REL32: 398 case TYPE_REL64: 399 isBranch = true; 400 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 401 // fall through to sign extend the immediate if needed. 402 case TYPE_MOFFS32: 403 if(immediate & 0x80000000) 404 immediate |= ~(0xffffffffull); 405 break; 406 case TYPE_MOFFS64: 407 default: 408 // operand is 64 bits wide. Do nothing. 409 break; 410 } 411 412 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, 413 insn.immediateOffset, insn.immediateSize, 414 mcInst, Dis)) 415 mcInst.addOperand(MCOperand::CreateImm(immediate)); 416 } 417 418 /// translateRMRegister - Translates a register stored in the R/M field of the 419 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 420 /// @param mcInst - The MCInst to append to. 421 /// @param insn - The internal instruction to extract the R/M field 422 /// from. 423 /// @return - 0 on success; -1 otherwise 424 static bool translateRMRegister(MCInst &mcInst, 425 InternalInstruction &insn) { 426 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 427 debug("A R/M register operand may not have a SIB byte"); 428 return true; 429 } 430 431 switch (insn.eaBase) { 432 default: 433 debug("Unexpected EA base register"); 434 return true; 435 case EA_BASE_NONE: 436 debug("EA_BASE_NONE for ModR/M base"); 437 return true; 438 #define ENTRY(x) case EA_BASE_##x: 439 ALL_EA_BASES 440 #undef ENTRY 441 debug("A R/M register operand may not have a base; " 442 "the operand must be a register."); 443 return true; 444 #define ENTRY(x) \ 445 case EA_REG_##x: \ 446 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 447 ALL_REGS 448 #undef ENTRY 449 } 450 451 return false; 452 } 453 454 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 455 /// fields of an internal instruction (and possibly its SIB byte) to a memory 456 /// operand in LLVM's format, and appends it to an MCInst. 457 /// 458 /// @param mcInst - The MCInst to append to. 459 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 460 /// from. 461 /// @return - 0 on success; nonzero otherwise 462 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, 463 const MCDisassembler *Dis) { 464 // Addresses in an MCInst are represented as five operands: 465 // 1. basereg (register) The R/M base, or (if there is a SIB) the 466 // SIB base 467 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 468 // scale amount 469 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 470 // the index (which is multiplied by the 471 // scale amount) 472 // 4. displacement (immediate) 0, or the displacement if there is one 473 // 5. segmentreg (register) x86_registerNONE for now, but could be set 474 // if we have segment overrides 475 476 MCOperand baseReg; 477 MCOperand scaleAmount; 478 MCOperand indexReg; 479 MCOperand displacement; 480 MCOperand segmentReg; 481 uint64_t pcrel = 0; 482 483 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 484 if (insn.sibBase != SIB_BASE_NONE) { 485 switch (insn.sibBase) { 486 default: 487 debug("Unexpected sibBase"); 488 return true; 489 #define ENTRY(x) \ 490 case SIB_BASE_##x: \ 491 baseReg = MCOperand::CreateReg(X86::x); break; 492 ALL_SIB_BASES 493 #undef ENTRY 494 } 495 } else { 496 baseReg = MCOperand::CreateReg(0); 497 } 498 499 if (insn.sibIndex != SIB_INDEX_NONE) { 500 switch (insn.sibIndex) { 501 default: 502 debug("Unexpected sibIndex"); 503 return true; 504 #define ENTRY(x) \ 505 case SIB_INDEX_##x: \ 506 indexReg = MCOperand::CreateReg(X86::x); break; 507 EA_BASES_32BIT 508 EA_BASES_64BIT 509 #undef ENTRY 510 } 511 } else { 512 indexReg = MCOperand::CreateReg(0); 513 } 514 515 scaleAmount = MCOperand::CreateImm(insn.sibScale); 516 } else { 517 switch (insn.eaBase) { 518 case EA_BASE_NONE: 519 if (insn.eaDisplacement == EA_DISP_NONE) { 520 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 521 return true; 522 } 523 if (insn.mode == MODE_64BIT){ 524 pcrel = insn.startLocation + 525 insn.displacementOffset + insn.displacementSize; 526 tryAddingPcLoadReferenceComment(insn.startLocation + 527 insn.displacementOffset, 528 insn.displacement + pcrel, Dis); 529 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6 530 } 531 else 532 baseReg = MCOperand::CreateReg(0); 533 534 indexReg = MCOperand::CreateReg(0); 535 break; 536 case EA_BASE_BX_SI: 537 baseReg = MCOperand::CreateReg(X86::BX); 538 indexReg = MCOperand::CreateReg(X86::SI); 539 break; 540 case EA_BASE_BX_DI: 541 baseReg = MCOperand::CreateReg(X86::BX); 542 indexReg = MCOperand::CreateReg(X86::DI); 543 break; 544 case EA_BASE_BP_SI: 545 baseReg = MCOperand::CreateReg(X86::BP); 546 indexReg = MCOperand::CreateReg(X86::SI); 547 break; 548 case EA_BASE_BP_DI: 549 baseReg = MCOperand::CreateReg(X86::BP); 550 indexReg = MCOperand::CreateReg(X86::DI); 551 break; 552 default: 553 indexReg = MCOperand::CreateReg(0); 554 switch (insn.eaBase) { 555 default: 556 debug("Unexpected eaBase"); 557 return true; 558 // Here, we will use the fill-ins defined above. However, 559 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 560 // sib and sib64 were handled in the top-level if, so they're only 561 // placeholders to keep the compiler happy. 562 #define ENTRY(x) \ 563 case EA_BASE_##x: \ 564 baseReg = MCOperand::CreateReg(X86::x); break; 565 ALL_EA_BASES 566 #undef ENTRY 567 #define ENTRY(x) case EA_REG_##x: 568 ALL_REGS 569 #undef ENTRY 570 debug("A R/M memory operand may not be a register; " 571 "the base field must be a base."); 572 return true; 573 } 574 } 575 576 scaleAmount = MCOperand::CreateImm(1); 577 } 578 579 displacement = MCOperand::CreateImm(insn.displacement); 580 581 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 582 0, // SEG_OVERRIDE_NONE 583 X86::CS, 584 X86::SS, 585 X86::DS, 586 X86::ES, 587 X86::FS, 588 X86::GS 589 }; 590 591 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); 592 593 mcInst.addOperand(baseReg); 594 mcInst.addOperand(scaleAmount); 595 mcInst.addOperand(indexReg); 596 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false, 597 insn.startLocation, insn.displacementOffset, 598 insn.displacementSize, mcInst, Dis)) 599 mcInst.addOperand(displacement); 600 mcInst.addOperand(segmentReg); 601 return false; 602 } 603 604 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 605 /// byte of an instruction to LLVM form, and appends it to an MCInst. 606 /// 607 /// @param mcInst - The MCInst to append to. 608 /// @param operand - The operand, as stored in the descriptor table. 609 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 610 /// from. 611 /// @return - 0 on success; nonzero otherwise 612 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, 613 InternalInstruction &insn, const MCDisassembler *Dis) { 614 switch (operand.type) { 615 default: 616 debug("Unexpected type for a R/M operand"); 617 return true; 618 case TYPE_R8: 619 case TYPE_R16: 620 case TYPE_R32: 621 case TYPE_R64: 622 case TYPE_Rv: 623 case TYPE_MM: 624 case TYPE_MM32: 625 case TYPE_MM64: 626 case TYPE_XMM: 627 case TYPE_XMM32: 628 case TYPE_XMM64: 629 case TYPE_XMM128: 630 case TYPE_XMM256: 631 case TYPE_DEBUGREG: 632 case TYPE_CONTROLREG: 633 return translateRMRegister(mcInst, insn); 634 case TYPE_M: 635 case TYPE_M8: 636 case TYPE_M16: 637 case TYPE_M32: 638 case TYPE_M64: 639 case TYPE_M128: 640 case TYPE_M256: 641 case TYPE_M512: 642 case TYPE_Mv: 643 case TYPE_M32FP: 644 case TYPE_M64FP: 645 case TYPE_M80FP: 646 case TYPE_M16INT: 647 case TYPE_M32INT: 648 case TYPE_M64INT: 649 case TYPE_M1616: 650 case TYPE_M1632: 651 case TYPE_M1664: 652 case TYPE_LEA: 653 return translateRMMemory(mcInst, insn, Dis); 654 } 655 } 656 657 /// translateFPRegister - Translates a stack position on the FPU stack to its 658 /// LLVM form, and appends it to an MCInst. 659 /// 660 /// @param mcInst - The MCInst to append to. 661 /// @param stackPos - The stack position to translate. 662 /// @return - 0 on success; nonzero otherwise. 663 static bool translateFPRegister(MCInst &mcInst, 664 uint8_t stackPos) { 665 if (stackPos >= 8) { 666 debug("Invalid FP stack position"); 667 return true; 668 } 669 670 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos)); 671 672 return false; 673 } 674 675 /// translateOperand - Translates an operand stored in an internal instruction 676 /// to LLVM's format and appends it to an MCInst. 677 /// 678 /// @param mcInst - The MCInst to append to. 679 /// @param operand - The operand, as stored in the descriptor table. 680 /// @param insn - The internal instruction. 681 /// @return - false on success; true otherwise. 682 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, 683 InternalInstruction &insn, 684 const MCDisassembler *Dis) { 685 switch (operand.encoding) { 686 default: 687 debug("Unhandled operand encoding during translation"); 688 return true; 689 case ENCODING_REG: 690 translateRegister(mcInst, insn.reg); 691 return false; 692 case ENCODING_RM: 693 return translateRM(mcInst, operand, insn, Dis); 694 case ENCODING_CB: 695 case ENCODING_CW: 696 case ENCODING_CD: 697 case ENCODING_CP: 698 case ENCODING_CO: 699 case ENCODING_CT: 700 debug("Translation of code offsets isn't supported."); 701 return true; 702 case ENCODING_IB: 703 case ENCODING_IW: 704 case ENCODING_ID: 705 case ENCODING_IO: 706 case ENCODING_Iv: 707 case ENCODING_Ia: 708 translateImmediate(mcInst, 709 insn.immediates[insn.numImmediatesTranslated++], 710 operand, 711 insn, 712 Dis); 713 return false; 714 case ENCODING_RB: 715 case ENCODING_RW: 716 case ENCODING_RD: 717 case ENCODING_RO: 718 translateRegister(mcInst, insn.opcodeRegister); 719 return false; 720 case ENCODING_I: 721 return translateFPRegister(mcInst, insn.opcodeModifier); 722 case ENCODING_Rv: 723 translateRegister(mcInst, insn.opcodeRegister); 724 return false; 725 case ENCODING_VVVV: 726 translateRegister(mcInst, insn.vvvv); 727 return false; 728 case ENCODING_DUP: 729 return translateOperand(mcInst, 730 insn.spec->operands[operand.type - TYPE_DUP0], 731 insn, Dis); 732 } 733 } 734 735 /// translateInstruction - Translates an internal instruction and all its 736 /// operands to an MCInst. 737 /// 738 /// @param mcInst - The MCInst to populate with the instruction's data. 739 /// @param insn - The internal instruction. 740 /// @return - false on success; true otherwise. 741 static bool translateInstruction(MCInst &mcInst, 742 InternalInstruction &insn, 743 const MCDisassembler *Dis) { 744 if (!insn.spec) { 745 debug("Instruction has no specification"); 746 return true; 747 } 748 749 mcInst.setOpcode(insn.instructionID); 750 751 int index; 752 753 insn.numImmediatesTranslated = 0; 754 755 for (index = 0; index < X86_MAX_OPERANDS; ++index) { 756 if (insn.spec->operands[index].encoding != ENCODING_NONE) { 757 if (translateOperand(mcInst, insn.spec->operands[index], insn, Dis)) { 758 return true; 759 } 760 } 761 } 762 763 return false; 764 } 765 766 static MCDisassembler *createX86_32Disassembler(const Target &T, 767 const MCSubtargetInfo &STI) { 768 return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT, 769 T.createMCInstrInfo()); 770 } 771 772 static MCDisassembler *createX86_64Disassembler(const Target &T, 773 const MCSubtargetInfo &STI) { 774 return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT, 775 T.createMCInstrInfo()); 776 } 777 778 extern "C" void LLVMInitializeX86Disassembler() { 779 // Register the disassembler. 780 TargetRegistry::RegisterMCDisassembler(TheX86_32Target, 781 createX86_32Disassembler); 782 TargetRegistry::RegisterMCDisassembler(TheX86_64Target, 783 createX86_64Disassembler); 784 } 785