1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // 14 // 15 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and 16 // 64-bit X86 instruction sets. The main decode sequence for an assembly 17 // instruction in this disassembler is: 18 // 19 // 1. Read the prefix bytes and determine the attributes of the instruction. 20 // These attributes, recorded in enum attributeBits 21 // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM 22 // provides a mapping from bitmasks to contexts, which are represented by 23 // enum InstructionContext (ibid.). 24 // 25 // 2. Read the opcode, and determine what kind of opcode it is. The 26 // disassembler distinguishes four kinds of opcodes, which are enumerated in 27 // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte 28 // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a 29 // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. 30 // 31 // 3. Depending on the opcode type, look in one of four ClassDecision structures 32 // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which 33 // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get 34 // a ModRMDecision (ibid.). 35 // 36 // 4. Some instructions, such as escape opcodes or extended opcodes, or even 37 // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the 38 // ModR/M byte to complete decode. The ModRMDecision's type is an entry from 39 // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the 40 // ModR/M byte is required and how to interpret it. 41 // 42 // 5. After resolving the ModRMDecision, the disassembler has a unique ID 43 // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in 44 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and 45 // meanings of its operands. 46 // 47 // 6. For each operand, its encoding is an entry from OperandEncoding 48 // (X86DisassemblerDecoderCommon.h) and its type is an entry from 49 // OperandType (ibid.). The encoding indicates how to read it from the 50 // instruction; the type indicates how to interpret the value once it has 51 // been read. For example, a register operand could be stored in the R/M 52 // field of the ModR/M byte, the REG field of the ModR/M byte, or added to 53 // the main opcode. This is orthogonal from its meaning (an GPR or an XMM 54 // register, for instance). Given this information, the operands can be 55 // extracted and interpreted. 56 // 57 // 7. As the last step, the disassembler translates the instruction information 58 // and operands into a format understandable by the client - in this case, an 59 // MCInst for use by the MC infrastructure. 60 // 61 // The disassembler is broken broadly into two parts: the table emitter that 62 // emits the instruction decode tables discussed above during compilation, and 63 // the disassembler itself. The table emitter is documented in more detail in 64 // utils/TableGen/X86DisassemblerEmitter.h. 65 // 66 // X86Disassembler.cpp contains the code responsible for step 7, and for 67 // invoking the decoder to execute steps 1-6. 68 // X86DisassemblerDecoderCommon.h contains the definitions needed by both the 69 // table emitter and the disassembler. 70 // X86DisassemblerDecoder.h contains the public interface of the decoder, 71 // factored out into C for possible use by other projects. 72 // X86DisassemblerDecoder.c contains the source code of the decoder, which is 73 // responsible for steps 1-6. 74 // 75 //===----------------------------------------------------------------------===// 76 77 #include "X86DisassemblerDecoder.h" 78 #include "MCTargetDesc/X86MCTargetDesc.h" 79 #include "llvm/MC/MCContext.h" 80 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 81 #include "llvm/MC/MCExpr.h" 82 #include "llvm/MC/MCInst.h" 83 #include "llvm/MC/MCInstrInfo.h" 84 #include "llvm/MC/MCSubtargetInfo.h" 85 #include "llvm/Support/Debug.h" 86 #include "llvm/Support/TargetRegistry.h" 87 #include "llvm/Support/raw_ostream.h" 88 89 using namespace llvm; 90 using namespace llvm::X86Disassembler; 91 92 #define DEBUG_TYPE "x86-disassembler" 93 94 void llvm::X86Disassembler::Debug(const char *file, unsigned line, 95 const char *s) { 96 dbgs() << file << ":" << line << ": " << s; 97 } 98 99 StringRef llvm::X86Disassembler::GetInstrName(unsigned Opcode, 100 const void *mii) { 101 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii); 102 return MII->getName(Opcode); 103 } 104 105 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s)); 106 107 namespace llvm { 108 109 // Fill-ins to make the compiler happy. These constants are never actually 110 // assigned; they are just filler to make an automatically-generated switch 111 // statement work. 112 namespace X86 { 113 enum { 114 BX_SI = 500, 115 BX_DI = 501, 116 BP_SI = 502, 117 BP_DI = 503, 118 sib = 504, 119 sib64 = 505 120 }; 121 } 122 123 } 124 125 static bool translateInstruction(MCInst &target, 126 InternalInstruction &source, 127 const MCDisassembler *Dis); 128 129 namespace { 130 131 /// Generic disassembler for all X86 platforms. All each platform class should 132 /// have to do is subclass the constructor, and provide a different 133 /// disassemblerMode value. 134 class X86GenericDisassembler : public MCDisassembler { 135 std::unique_ptr<const MCInstrInfo> MII; 136 public: 137 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 138 std::unique_ptr<const MCInstrInfo> MII); 139 public: 140 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 141 ArrayRef<uint8_t> Bytes, uint64_t Address, 142 raw_ostream &vStream, 143 raw_ostream &cStream) const override; 144 145 private: 146 DisassemblerMode fMode; 147 }; 148 149 } 150 151 X86GenericDisassembler::X86GenericDisassembler( 152 const MCSubtargetInfo &STI, 153 MCContext &Ctx, 154 std::unique_ptr<const MCInstrInfo> MII) 155 : MCDisassembler(STI, Ctx), MII(std::move(MII)) { 156 const FeatureBitset &FB = STI.getFeatureBits(); 157 if (FB[X86::Mode16Bit]) { 158 fMode = MODE_16BIT; 159 return; 160 } else if (FB[X86::Mode32Bit]) { 161 fMode = MODE_32BIT; 162 return; 163 } else if (FB[X86::Mode64Bit]) { 164 fMode = MODE_64BIT; 165 return; 166 } 167 168 llvm_unreachable("Invalid CPU mode"); 169 } 170 171 namespace { 172 struct Region { 173 ArrayRef<uint8_t> Bytes; 174 uint64_t Base; 175 Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {} 176 }; 177 } // end anonymous namespace 178 179 /// A callback function that wraps the readByte method from Region. 180 /// 181 /// @param Arg - The generic callback parameter. In this case, this should 182 /// be a pointer to a Region. 183 /// @param Byte - A pointer to the byte to be read. 184 /// @param Address - The address to be read. 185 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) { 186 auto *R = static_cast<const Region *>(Arg); 187 ArrayRef<uint8_t> Bytes = R->Bytes; 188 unsigned Index = Address - R->Base; 189 if (Bytes.size() <= Index) 190 return -1; 191 *Byte = Bytes[Index]; 192 return 0; 193 } 194 195 /// logger - a callback function that wraps the operator<< method from 196 /// raw_ostream. 197 /// 198 /// @param arg - The generic callback parameter. This should be a pointe 199 /// to a raw_ostream. 200 /// @param log - A string to be logged. logger() adds a newline. 201 static void logger(void* arg, const char* log) { 202 if (!arg) 203 return; 204 205 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 206 vStream << log << "\n"; 207 } 208 209 // 210 // Public interface for the disassembler 211 // 212 213 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( 214 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, 215 raw_ostream &VStream, raw_ostream &CStream) const { 216 CommentStream = &CStream; 217 218 InternalInstruction InternalInstr; 219 220 dlog_t LoggerFn = logger; 221 if (&VStream == &nulls()) 222 LoggerFn = nullptr; // Disable logging completely if it's going to nulls(). 223 224 Region R(Bytes, Address); 225 226 int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R, 227 LoggerFn, (void *)&VStream, 228 (const void *)MII.get(), Address, fMode); 229 230 if (Ret) { 231 Size = InternalInstr.readerCursor - Address; 232 return Fail; 233 } else { 234 Size = InternalInstr.length; 235 return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail; 236 } 237 } 238 239 // 240 // Private code that translates from struct InternalInstructions to MCInsts. 241 // 242 243 /// translateRegister - Translates an internal register to the appropriate LLVM 244 /// register, and appends it as an operand to an MCInst. 245 /// 246 /// @param mcInst - The MCInst to append to. 247 /// @param reg - The Reg to append. 248 static void translateRegister(MCInst &mcInst, Reg reg) { 249 #define ENTRY(x) X86::x, 250 uint8_t llvmRegnums[] = { 251 ALL_REGS 252 0 253 }; 254 #undef ENTRY 255 256 uint8_t llvmRegnum = llvmRegnums[reg]; 257 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); 258 } 259 260 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 261 /// immediate Value in the MCInst. 262 /// 263 /// @param Value - The immediate Value, has had any PC adjustment made by 264 /// the caller. 265 /// @param isBranch - If the instruction is a branch instruction 266 /// @param Address - The starting address of the instruction 267 /// @param Offset - The byte offset to this immediate in the instruction 268 /// @param Width - The byte width of this immediate in the instruction 269 /// 270 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was 271 /// called then that function is called to get any symbolic information for the 272 /// immediate in the instruction using the Address, Offset and Width. If that 273 /// returns non-zero then the symbolic information it returns is used to create 274 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo() 275 /// returns zero and isBranch is true then a symbol look up for immediate Value 276 /// is done and if a symbol is found an MCExpr is created with that, else 277 /// an MCExpr with the immediate Value is created. This function returns true 278 /// if it adds an operand to the MCInst and false otherwise. 279 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 280 uint64_t Address, uint64_t Offset, 281 uint64_t Width, MCInst &MI, 282 const MCDisassembler *Dis) { 283 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 284 Offset, Width); 285 } 286 287 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 288 /// referenced by a load instruction with the base register that is the rip. 289 /// These can often be addresses in a literal pool. The Address of the 290 /// instruction and its immediate Value are used to determine the address 291 /// being referenced in the literal pool entry. The SymbolLookUp call back will 292 /// return a pointer to a literal 'C' string if the referenced address is an 293 /// address into a section with 'C' string literals. 294 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, 295 const void *Decoder) { 296 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 297 Dis->tryAddingPcLoadReferenceComment(Value, Address); 298 } 299 300 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 301 0, // SEG_OVERRIDE_NONE 302 X86::CS, 303 X86::SS, 304 X86::DS, 305 X86::ES, 306 X86::FS, 307 X86::GS 308 }; 309 310 /// translateSrcIndex - Appends a source index operand to an MCInst. 311 /// 312 /// @param mcInst - The MCInst to append to. 313 /// @param insn - The internal instruction. 314 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { 315 unsigned baseRegNo; 316 317 if (insn.mode == MODE_64BIT) 318 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI; 319 else if (insn.mode == MODE_32BIT) 320 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI; 321 else { 322 assert(insn.mode == MODE_16BIT); 323 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI; 324 } 325 MCOperand baseReg = MCOperand::createReg(baseRegNo); 326 mcInst.addOperand(baseReg); 327 328 MCOperand segmentReg; 329 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 330 mcInst.addOperand(segmentReg); 331 return false; 332 } 333 334 /// translateDstIndex - Appends a destination index operand to an MCInst. 335 /// 336 /// @param mcInst - The MCInst to append to. 337 /// @param insn - The internal instruction. 338 339 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { 340 unsigned baseRegNo; 341 342 if (insn.mode == MODE_64BIT) 343 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI; 344 else if (insn.mode == MODE_32BIT) 345 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI; 346 else { 347 assert(insn.mode == MODE_16BIT); 348 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI; 349 } 350 MCOperand baseReg = MCOperand::createReg(baseRegNo); 351 mcInst.addOperand(baseReg); 352 return false; 353 } 354 355 /// translateImmediate - Appends an immediate operand to an MCInst. 356 /// 357 /// @param mcInst - The MCInst to append to. 358 /// @param immediate - The immediate value to append. 359 /// @param operand - The operand, as stored in the descriptor table. 360 /// @param insn - The internal instruction. 361 static void translateImmediate(MCInst &mcInst, uint64_t immediate, 362 const OperandSpecifier &operand, 363 InternalInstruction &insn, 364 const MCDisassembler *Dis) { 365 // Sign-extend the immediate if necessary. 366 367 OperandType type = (OperandType)operand.type; 368 369 bool isBranch = false; 370 uint64_t pcrel = 0; 371 if (type == TYPE_RELv) { 372 isBranch = true; 373 pcrel = insn.startLocation + 374 insn.immediateOffset + insn.immediateSize; 375 switch (insn.displacementSize) { 376 default: 377 break; 378 case 1: 379 if(immediate & 0x80) 380 immediate |= ~(0xffull); 381 break; 382 case 2: 383 if(immediate & 0x8000) 384 immediate |= ~(0xffffull); 385 break; 386 case 4: 387 if(immediate & 0x80000000) 388 immediate |= ~(0xffffffffull); 389 break; 390 case 8: 391 break; 392 } 393 } 394 // By default sign-extend all X86 immediates based on their encoding. 395 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || 396 type == TYPE_IMM64 || type == TYPE_IMMv) { 397 switch (operand.encoding) { 398 default: 399 break; 400 case ENCODING_IB: 401 if(immediate & 0x80) 402 immediate |= ~(0xffull); 403 break; 404 case ENCODING_IW: 405 if(immediate & 0x8000) 406 immediate |= ~(0xffffull); 407 break; 408 case ENCODING_ID: 409 if(immediate & 0x80000000) 410 immediate |= ~(0xffffffffull); 411 break; 412 case ENCODING_IO: 413 break; 414 } 415 } else if (type == TYPE_IMM3) { 416 // Check for immediates that printSSECC can't handle. 417 if (immediate >= 8) { 418 unsigned NewOpc; 419 switch (mcInst.getOpcode()) { 420 default: llvm_unreachable("unexpected opcode"); 421 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; 422 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; 423 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; 424 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; 425 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; 426 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; 427 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; 428 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; 429 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; 430 case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break; 431 case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break; 432 case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break; 433 case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break; 434 case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break; 435 case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break; 436 case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break; 437 case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break; 438 case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break; 439 case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break; 440 case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break; 441 case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break; 442 case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break; 443 case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break; 444 case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break; 445 } 446 // Switch opcode to the one that doesn't get special printing. 447 mcInst.setOpcode(NewOpc); 448 } 449 } else if (type == TYPE_IMM5) { 450 // Check for immediates that printAVXCC can't handle. 451 if (immediate >= 32) { 452 unsigned NewOpc; 453 switch (mcInst.getOpcode()) { 454 default: llvm_unreachable("unexpected opcode"); 455 case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break; 456 case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break; 457 case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break; 458 case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break; 459 case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break; 460 case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break; 461 case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break; 462 case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break; 463 case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break; 464 case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break; 465 case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break; 466 case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break; 467 case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break; 468 case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break; 469 case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break; 470 case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break; 471 case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break; 472 case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break; 473 case X86::VCMPSDZrm: NewOpc = X86::VCMPSDZrmi_alt; break; 474 case X86::VCMPSDZrr: NewOpc = X86::VCMPSDZrri_alt; break; 475 case X86::VCMPSSZrm: NewOpc = X86::VCMPSSZrmi_alt; break; 476 case X86::VCMPSSZrr: NewOpc = X86::VCMPSSZrri_alt; break; 477 } 478 // Switch opcode to the one that doesn't get special printing. 479 mcInst.setOpcode(NewOpc); 480 } 481 } else if (type == TYPE_AVX512ICC) { 482 if (immediate >= 8 || ((immediate & 0x3) == 3)) { 483 unsigned NewOpc; 484 switch (mcInst.getOpcode()) { 485 default: llvm_unreachable("unexpected opcode"); 486 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break; 487 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break; 488 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break; 489 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break; 490 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break; 491 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break; 492 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break; 493 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break; 494 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break; 495 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break; 496 case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break; 497 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break; 498 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break; 499 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break; 500 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break; 501 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break; 502 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break; 503 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break; 504 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break; 505 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break; 506 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break; 507 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break; 508 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break; 509 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break; 510 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break; 511 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break; 512 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break; 513 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break; 514 case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break; 515 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break; 516 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break; 517 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break; 518 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break; 519 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break; 520 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break; 521 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break; 522 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break; 523 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break; 524 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break; 525 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break; 526 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break; 527 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break; 528 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break; 529 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break; 530 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break; 531 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break; 532 case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break; 533 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break; 534 case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break; 535 case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break; 536 case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break; 537 case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break; 538 case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break; 539 case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break; 540 case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break; 541 case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break; 542 case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break; 543 case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break; 544 case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break; 545 case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break; 546 case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break; 547 case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break; 548 case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break; 549 case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break; 550 case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break; 551 case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break; 552 case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break; 553 case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break; 554 case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break; 555 case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break; 556 case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break; 557 case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break; 558 case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break; 559 case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break; 560 case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break; 561 case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break; 562 case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break; 563 case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break; 564 case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break; 565 case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break; 566 case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break; 567 case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break; 568 case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break; 569 case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break; 570 case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break; 571 case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break; 572 case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break; 573 case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break; 574 case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break; 575 case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break; 576 case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break; 577 case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break; 578 case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break; 579 case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break; 580 case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break; 581 case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break; 582 case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break; 583 case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break; 584 case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break; 585 case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break; 586 case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break; 587 case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break; 588 case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break; 589 case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break; 590 case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break; 591 case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break; 592 case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break; 593 case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break; 594 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break; 595 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break; 596 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break; 597 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break; 598 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break; 599 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break; 600 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break; 601 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break; 602 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break; 603 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break; 604 case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break; 605 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break; 606 } 607 // Switch opcode to the one that doesn't get special printing. 608 mcInst.setOpcode(NewOpc); 609 } 610 } 611 612 switch (type) { 613 case TYPE_XMM32: 614 case TYPE_XMM64: 615 case TYPE_XMM128: 616 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); 617 return; 618 case TYPE_XMM256: 619 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); 620 return; 621 case TYPE_XMM512: 622 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); 623 return; 624 case TYPE_BNDR: 625 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); 626 case TYPE_REL8: 627 isBranch = true; 628 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 629 if (immediate & 0x80) 630 immediate |= ~(0xffull); 631 break; 632 case TYPE_REL16: 633 isBranch = true; 634 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 635 if (immediate & 0x8000) 636 immediate |= ~(0xffffull); 637 break; 638 case TYPE_REL32: 639 case TYPE_REL64: 640 isBranch = true; 641 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; 642 if(immediate & 0x80000000) 643 immediate |= ~(0xffffffffull); 644 break; 645 default: 646 // operand is 64 bits wide. Do nothing. 647 break; 648 } 649 650 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, 651 insn.immediateOffset, insn.immediateSize, 652 mcInst, Dis)) 653 mcInst.addOperand(MCOperand::createImm(immediate)); 654 655 if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || 656 type == TYPE_MOFFS32 || type == TYPE_MOFFS64) { 657 MCOperand segmentReg; 658 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 659 mcInst.addOperand(segmentReg); 660 } 661 } 662 663 /// translateRMRegister - Translates a register stored in the R/M field of the 664 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 665 /// @param mcInst - The MCInst to append to. 666 /// @param insn - The internal instruction to extract the R/M field 667 /// from. 668 /// @return - 0 on success; -1 otherwise 669 static bool translateRMRegister(MCInst &mcInst, 670 InternalInstruction &insn) { 671 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 672 debug("A R/M register operand may not have a SIB byte"); 673 return true; 674 } 675 676 switch (insn.eaBase) { 677 default: 678 debug("Unexpected EA base register"); 679 return true; 680 case EA_BASE_NONE: 681 debug("EA_BASE_NONE for ModR/M base"); 682 return true; 683 #define ENTRY(x) case EA_BASE_##x: 684 ALL_EA_BASES 685 #undef ENTRY 686 debug("A R/M register operand may not have a base; " 687 "the operand must be a register."); 688 return true; 689 #define ENTRY(x) \ 690 case EA_REG_##x: \ 691 mcInst.addOperand(MCOperand::createReg(X86::x)); break; 692 ALL_REGS 693 #undef ENTRY 694 } 695 696 return false; 697 } 698 699 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 700 /// fields of an internal instruction (and possibly its SIB byte) to a memory 701 /// operand in LLVM's format, and appends it to an MCInst. 702 /// 703 /// @param mcInst - The MCInst to append to. 704 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 705 /// from. 706 /// @return - 0 on success; nonzero otherwise 707 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, 708 const MCDisassembler *Dis) { 709 // Addresses in an MCInst are represented as five operands: 710 // 1. basereg (register) The R/M base, or (if there is a SIB) the 711 // SIB base 712 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 713 // scale amount 714 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 715 // the index (which is multiplied by the 716 // scale amount) 717 // 4. displacement (immediate) 0, or the displacement if there is one 718 // 5. segmentreg (register) x86_registerNONE for now, but could be set 719 // if we have segment overrides 720 721 MCOperand baseReg; 722 MCOperand scaleAmount; 723 MCOperand indexReg; 724 MCOperand displacement; 725 MCOperand segmentReg; 726 uint64_t pcrel = 0; 727 728 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 729 if (insn.sibBase != SIB_BASE_NONE) { 730 switch (insn.sibBase) { 731 default: 732 debug("Unexpected sibBase"); 733 return true; 734 #define ENTRY(x) \ 735 case SIB_BASE_##x: \ 736 baseReg = MCOperand::createReg(X86::x); break; 737 ALL_SIB_BASES 738 #undef ENTRY 739 } 740 } else { 741 baseReg = MCOperand::createReg(0); 742 } 743 744 // Check whether we are handling VSIB addressing mode for GATHER. 745 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and 746 // we should use SIB_INDEX_XMM4|YMM4 for VSIB. 747 // I don't see a way to get the correct IndexReg in readSIB: 748 // We can tell whether it is VSIB or SIB after instruction ID is decoded, 749 // but instruction ID may not be decoded yet when calling readSIB. 750 uint32_t Opcode = mcInst.getOpcode(); 751 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm || 752 Opcode == X86::VGATHERDPDYrm || 753 Opcode == X86::VGATHERQPDrm || 754 Opcode == X86::VGATHERDPSrm || 755 Opcode == X86::VGATHERQPSrm || 756 Opcode == X86::VPGATHERDQrm || 757 Opcode == X86::VPGATHERDQYrm || 758 Opcode == X86::VPGATHERQQrm || 759 Opcode == X86::VPGATHERDDrm || 760 Opcode == X86::VPGATHERQDrm); 761 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm || 762 Opcode == X86::VGATHERDPSYrm || 763 Opcode == X86::VGATHERQPSYrm || 764 Opcode == X86::VGATHERDPDZrm || 765 Opcode == X86::VPGATHERDQZrm || 766 Opcode == X86::VPGATHERQQYrm || 767 Opcode == X86::VPGATHERDDYrm || 768 Opcode == X86::VPGATHERQDYrm); 769 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm || 770 Opcode == X86::VGATHERDPSZrm || 771 Opcode == X86::VGATHERQPSZrm || 772 Opcode == X86::VPGATHERQQZrm || 773 Opcode == X86::VPGATHERDDZrm || 774 Opcode == X86::VPGATHERQDZrm); 775 if (IndexIs128 || IndexIs256 || IndexIs512) { 776 unsigned IndexOffset = insn.sibIndex - 777 (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX); 778 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 : 779 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0; 780 insn.sibIndex = (SIBIndex)(IndexBase + 781 (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset)); 782 } 783 784 if (insn.sibIndex != SIB_INDEX_NONE) { 785 switch (insn.sibIndex) { 786 default: 787 debug("Unexpected sibIndex"); 788 return true; 789 #define ENTRY(x) \ 790 case SIB_INDEX_##x: \ 791 indexReg = MCOperand::createReg(X86::x); break; 792 EA_BASES_32BIT 793 EA_BASES_64BIT 794 REGS_XMM 795 REGS_YMM 796 REGS_ZMM 797 #undef ENTRY 798 } 799 } else { 800 indexReg = MCOperand::createReg(0); 801 } 802 803 scaleAmount = MCOperand::createImm(insn.sibScale); 804 } else { 805 switch (insn.eaBase) { 806 case EA_BASE_NONE: 807 if (insn.eaDisplacement == EA_DISP_NONE) { 808 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 809 return true; 810 } 811 if (insn.mode == MODE_64BIT){ 812 pcrel = insn.startLocation + 813 insn.displacementOffset + insn.displacementSize; 814 tryAddingPcLoadReferenceComment(insn.startLocation + 815 insn.displacementOffset, 816 insn.displacement + pcrel, Dis); 817 baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6 818 } 819 else 820 baseReg = MCOperand::createReg(0); 821 822 indexReg = MCOperand::createReg(0); 823 break; 824 case EA_BASE_BX_SI: 825 baseReg = MCOperand::createReg(X86::BX); 826 indexReg = MCOperand::createReg(X86::SI); 827 break; 828 case EA_BASE_BX_DI: 829 baseReg = MCOperand::createReg(X86::BX); 830 indexReg = MCOperand::createReg(X86::DI); 831 break; 832 case EA_BASE_BP_SI: 833 baseReg = MCOperand::createReg(X86::BP); 834 indexReg = MCOperand::createReg(X86::SI); 835 break; 836 case EA_BASE_BP_DI: 837 baseReg = MCOperand::createReg(X86::BP); 838 indexReg = MCOperand::createReg(X86::DI); 839 break; 840 default: 841 indexReg = MCOperand::createReg(0); 842 switch (insn.eaBase) { 843 default: 844 debug("Unexpected eaBase"); 845 return true; 846 // Here, we will use the fill-ins defined above. However, 847 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 848 // sib and sib64 were handled in the top-level if, so they're only 849 // placeholders to keep the compiler happy. 850 #define ENTRY(x) \ 851 case EA_BASE_##x: \ 852 baseReg = MCOperand::createReg(X86::x); break; 853 ALL_EA_BASES 854 #undef ENTRY 855 #define ENTRY(x) case EA_REG_##x: 856 ALL_REGS 857 #undef ENTRY 858 debug("A R/M memory operand may not be a register; " 859 "the base field must be a base."); 860 return true; 861 } 862 } 863 864 scaleAmount = MCOperand::createImm(1); 865 } 866 867 displacement = MCOperand::createImm(insn.displacement); 868 869 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 870 871 mcInst.addOperand(baseReg); 872 mcInst.addOperand(scaleAmount); 873 mcInst.addOperand(indexReg); 874 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false, 875 insn.startLocation, insn.displacementOffset, 876 insn.displacementSize, mcInst, Dis)) 877 mcInst.addOperand(displacement); 878 mcInst.addOperand(segmentReg); 879 return false; 880 } 881 882 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 883 /// byte of an instruction to LLVM form, and appends it to an MCInst. 884 /// 885 /// @param mcInst - The MCInst to append to. 886 /// @param operand - The operand, as stored in the descriptor table. 887 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 888 /// from. 889 /// @return - 0 on success; nonzero otherwise 890 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, 891 InternalInstruction &insn, const MCDisassembler *Dis) { 892 switch (operand.type) { 893 default: 894 debug("Unexpected type for a R/M operand"); 895 return true; 896 case TYPE_R8: 897 case TYPE_R16: 898 case TYPE_R32: 899 case TYPE_R64: 900 case TYPE_Rv: 901 case TYPE_MM64: 902 case TYPE_XMM32: 903 case TYPE_XMM64: 904 case TYPE_XMM128: 905 case TYPE_XMM256: 906 case TYPE_XMM512: 907 case TYPE_VK1: 908 case TYPE_VK2: 909 case TYPE_VK4: 910 case TYPE_VK8: 911 case TYPE_VK16: 912 case TYPE_VK32: 913 case TYPE_VK64: 914 case TYPE_DEBUGREG: 915 case TYPE_CONTROLREG: 916 case TYPE_BNDR: 917 return translateRMRegister(mcInst, insn); 918 case TYPE_M: 919 case TYPE_M8: 920 case TYPE_M16: 921 case TYPE_M32: 922 case TYPE_M64: 923 case TYPE_M128: 924 case TYPE_M256: 925 case TYPE_M512: 926 case TYPE_Mv: 927 case TYPE_M32FP: 928 case TYPE_M64FP: 929 case TYPE_M80FP: 930 case TYPE_M1616: 931 case TYPE_M1632: 932 case TYPE_M1664: 933 case TYPE_LEA: 934 return translateRMMemory(mcInst, insn, Dis); 935 } 936 } 937 938 /// translateFPRegister - Translates a stack position on the FPU stack to its 939 /// LLVM form, and appends it to an MCInst. 940 /// 941 /// @param mcInst - The MCInst to append to. 942 /// @param stackPos - The stack position to translate. 943 static void translateFPRegister(MCInst &mcInst, 944 uint8_t stackPos) { 945 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos)); 946 } 947 948 /// translateMaskRegister - Translates a 3-bit mask register number to 949 /// LLVM form, and appends it to an MCInst. 950 /// 951 /// @param mcInst - The MCInst to append to. 952 /// @param maskRegNum - Number of mask register from 0 to 7. 953 /// @return - false on success; true otherwise. 954 static bool translateMaskRegister(MCInst &mcInst, 955 uint8_t maskRegNum) { 956 if (maskRegNum >= 8) { 957 debug("Invalid mask register number"); 958 return true; 959 } 960 961 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum)); 962 return false; 963 } 964 965 /// translateOperand - Translates an operand stored in an internal instruction 966 /// to LLVM's format and appends it to an MCInst. 967 /// 968 /// @param mcInst - The MCInst to append to. 969 /// @param operand - The operand, as stored in the descriptor table. 970 /// @param insn - The internal instruction. 971 /// @return - false on success; true otherwise. 972 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, 973 InternalInstruction &insn, 974 const MCDisassembler *Dis) { 975 switch (operand.encoding) { 976 default: 977 debug("Unhandled operand encoding during translation"); 978 return true; 979 case ENCODING_REG: 980 translateRegister(mcInst, insn.reg); 981 return false; 982 case ENCODING_WRITEMASK: 983 return translateMaskRegister(mcInst, insn.writemask); 984 CASE_ENCODING_RM: 985 return translateRM(mcInst, operand, insn, Dis); 986 case ENCODING_IB: 987 case ENCODING_IW: 988 case ENCODING_ID: 989 case ENCODING_IO: 990 case ENCODING_Iv: 991 case ENCODING_Ia: 992 translateImmediate(mcInst, 993 insn.immediates[insn.numImmediatesTranslated++], 994 operand, 995 insn, 996 Dis); 997 return false; 998 case ENCODING_SI: 999 return translateSrcIndex(mcInst, insn); 1000 case ENCODING_DI: 1001 return translateDstIndex(mcInst, insn); 1002 case ENCODING_RB: 1003 case ENCODING_RW: 1004 case ENCODING_RD: 1005 case ENCODING_RO: 1006 case ENCODING_Rv: 1007 translateRegister(mcInst, insn.opcodeRegister); 1008 return false; 1009 case ENCODING_FP: 1010 translateFPRegister(mcInst, insn.modRM & 7); 1011 return false; 1012 case ENCODING_VVVV: 1013 translateRegister(mcInst, insn.vvvv); 1014 return false; 1015 case ENCODING_DUP: 1016 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0], 1017 insn, Dis); 1018 } 1019 } 1020 1021 /// translateInstruction - Translates an internal instruction and all its 1022 /// operands to an MCInst. 1023 /// 1024 /// @param mcInst - The MCInst to populate with the instruction's data. 1025 /// @param insn - The internal instruction. 1026 /// @return - false on success; true otherwise. 1027 static bool translateInstruction(MCInst &mcInst, 1028 InternalInstruction &insn, 1029 const MCDisassembler *Dis) { 1030 if (!insn.spec) { 1031 debug("Instruction has no specification"); 1032 return true; 1033 } 1034 1035 mcInst.clear(); 1036 mcInst.setOpcode(insn.instructionID); 1037 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 1038 // prefix bytes should be disassembled as xrelease and xacquire then set the 1039 // opcode to those instead of the rep and repne opcodes. 1040 if (insn.xAcquireRelease) { 1041 if(mcInst.getOpcode() == X86::REP_PREFIX) 1042 mcInst.setOpcode(X86::XRELEASE_PREFIX); 1043 else if(mcInst.getOpcode() == X86::REPNE_PREFIX) 1044 mcInst.setOpcode(X86::XACQUIRE_PREFIX); 1045 } 1046 1047 insn.numImmediatesTranslated = 0; 1048 1049 for (const auto &Op : insn.operands) { 1050 if (Op.encoding != ENCODING_NONE) { 1051 if (translateOperand(mcInst, Op, insn, Dis)) { 1052 return true; 1053 } 1054 } 1055 } 1056 1057 return false; 1058 } 1059 1060 static MCDisassembler *createX86Disassembler(const Target &T, 1061 const MCSubtargetInfo &STI, 1062 MCContext &Ctx) { 1063 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); 1064 return new X86GenericDisassembler(STI, Ctx, std::move(MII)); 1065 } 1066 1067 extern "C" void LLVMInitializeX86Disassembler() { 1068 // Register the disassembler. 1069 TargetRegistry::RegisterMCDisassembler(getTheX86_32Target(), 1070 createX86Disassembler); 1071 TargetRegistry::RegisterMCDisassembler(getTheX86_64Target(), 1072 createX86Disassembler); 1073 } 1074