1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // Documentation for the disassembler can be found in X86Disassembler.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86Disassembler.h" 18 #include "X86DisassemblerDecoder.h" 19 20 #include "llvm/MC/EDInstInfo.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/Target/TargetRegistry.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/MemoryObject.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 #include "X86GenRegisterNames.inc" 30 #include "X86GenEDInfo.inc" 31 32 using namespace llvm; 33 using namespace llvm::X86Disassembler; 34 35 void x86DisassemblerDebug(const char *file, 36 unsigned line, 37 const char *s) { 38 dbgs() << file << ":" << line << ": " << s; 39 } 40 41 #define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s)); 42 43 namespace llvm { 44 45 // Fill-ins to make the compiler happy. These constants are never actually 46 // assigned; they are just filler to make an automatically-generated switch 47 // statement work. 48 namespace X86 { 49 enum { 50 BX_SI = 500, 51 BX_DI = 501, 52 BP_SI = 502, 53 BP_DI = 503, 54 sib = 504, 55 sib64 = 505 56 }; 57 } 58 59 extern Target TheX86_32Target, TheX86_64Target; 60 61 } 62 63 static bool translateInstruction(MCInst &target, 64 InternalInstruction &source); 65 66 X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) : 67 MCDisassembler(), 68 fMode(mode) { 69 } 70 71 X86GenericDisassembler::~X86GenericDisassembler() { 72 } 73 74 EDInstInfo *X86GenericDisassembler::getEDInfo() const { 75 return instInfoX86; 76 } 77 78 /// regionReader - a callback function that wraps the readByte method from 79 /// MemoryObject. 80 /// 81 /// @param arg - The generic callback parameter. In this case, this should 82 /// be a pointer to a MemoryObject. 83 /// @param byte - A pointer to the byte to be read. 84 /// @param address - The address to be read. 85 static int regionReader(void* arg, uint8_t* byte, uint64_t address) { 86 MemoryObject* region = static_cast<MemoryObject*>(arg); 87 return region->readByte(address, byte); 88 } 89 90 /// logger - a callback function that wraps the operator<< method from 91 /// raw_ostream. 92 /// 93 /// @param arg - The generic callback parameter. This should be a pointe 94 /// to a raw_ostream. 95 /// @param log - A string to be logged. logger() adds a newline. 96 static void logger(void* arg, const char* log) { 97 if (!arg) 98 return; 99 100 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 101 vStream << log << "\n"; 102 } 103 104 // 105 // Public interface for the disassembler 106 // 107 108 bool X86GenericDisassembler::getInstruction(MCInst &instr, 109 uint64_t &size, 110 const MemoryObject ®ion, 111 uint64_t address, 112 raw_ostream &vStream) const { 113 InternalInstruction internalInstr; 114 115 int ret = decodeInstruction(&internalInstr, 116 regionReader, 117 (void*)®ion, 118 logger, 119 (void*)&vStream, 120 address, 121 fMode); 122 123 if (ret) { 124 size = internalInstr.readerCursor - address; 125 return false; 126 } 127 else { 128 size = internalInstr.length; 129 return !translateInstruction(instr, internalInstr); 130 } 131 } 132 133 // 134 // Private code that translates from struct InternalInstructions to MCInsts. 135 // 136 137 /// translateRegister - Translates an internal register to the appropriate LLVM 138 /// register, and appends it as an operand to an MCInst. 139 /// 140 /// @param mcInst - The MCInst to append to. 141 /// @param reg - The Reg to append. 142 static void translateRegister(MCInst &mcInst, Reg reg) { 143 #define ENTRY(x) X86::x, 144 uint8_t llvmRegnums[] = { 145 ALL_REGS 146 0 147 }; 148 #undef ENTRY 149 150 uint8_t llvmRegnum = llvmRegnums[reg]; 151 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 152 } 153 154 /// translateImmediate - Appends an immediate operand to an MCInst. 155 /// 156 /// @param mcInst - The MCInst to append to. 157 /// @param immediate - The immediate value to append. 158 /// @param operand - The operand, as stored in the descriptor table. 159 /// @param insn - The internal instruction. 160 static void translateImmediate(MCInst &mcInst, 161 uint64_t immediate, 162 OperandSpecifier &operand, 163 InternalInstruction &insn) { 164 // Sign-extend the immediate if necessary. 165 166 OperandType type = operand.type; 167 168 if (type == TYPE_RELv) { 169 switch (insn.displacementSize) { 170 default: 171 break; 172 case 8: 173 type = TYPE_MOFFS8; 174 break; 175 case 16: 176 type = TYPE_MOFFS16; 177 break; 178 case 32: 179 type = TYPE_MOFFS32; 180 break; 181 case 64: 182 type = TYPE_MOFFS64; 183 break; 184 } 185 } 186 187 switch (type) { 188 case TYPE_MOFFS8: 189 case TYPE_REL8: 190 if(immediate & 0x80) 191 immediate |= ~(0xffull); 192 break; 193 case TYPE_MOFFS16: 194 if(immediate & 0x8000) 195 immediate |= ~(0xffffull); 196 break; 197 case TYPE_MOFFS32: 198 case TYPE_REL32: 199 case TYPE_REL64: 200 if(immediate & 0x80000000) 201 immediate |= ~(0xffffffffull); 202 break; 203 case TYPE_MOFFS64: 204 default: 205 // operand is 64 bits wide. Do nothing. 206 break; 207 } 208 209 mcInst.addOperand(MCOperand::CreateImm(immediate)); 210 } 211 212 /// translateRMRegister - Translates a register stored in the R/M field of the 213 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 214 /// @param mcInst - The MCInst to append to. 215 /// @param insn - The internal instruction to extract the R/M field 216 /// from. 217 /// @return - 0 on success; -1 otherwise 218 static bool translateRMRegister(MCInst &mcInst, 219 InternalInstruction &insn) { 220 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 221 debug("A R/M register operand may not have a SIB byte"); 222 return true; 223 } 224 225 switch (insn.eaBase) { 226 default: 227 debug("Unexpected EA base register"); 228 return true; 229 case EA_BASE_NONE: 230 debug("EA_BASE_NONE for ModR/M base"); 231 return true; 232 #define ENTRY(x) case EA_BASE_##x: 233 ALL_EA_BASES 234 #undef ENTRY 235 debug("A R/M register operand may not have a base; " 236 "the operand must be a register."); 237 return true; 238 #define ENTRY(x) \ 239 case EA_REG_##x: \ 240 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 241 ALL_REGS 242 #undef ENTRY 243 } 244 245 return false; 246 } 247 248 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 249 /// fields of an internal instruction (and possibly its SIB byte) to a memory 250 /// operand in LLVM's format, and appends it to an MCInst. 251 /// 252 /// @param mcInst - The MCInst to append to. 253 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 254 /// from. 255 /// @param sr - Whether or not to emit the segment register. The 256 /// LEA instruction does not expect a segment-register 257 /// operand. 258 /// @return - 0 on success; nonzero otherwise 259 static bool translateRMMemory(MCInst &mcInst, 260 InternalInstruction &insn, 261 bool sr) { 262 // Addresses in an MCInst are represented as five operands: 263 // 1. basereg (register) The R/M base, or (if there is a SIB) the 264 // SIB base 265 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 266 // scale amount 267 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 268 // the index (which is multiplied by the 269 // scale amount) 270 // 4. displacement (immediate) 0, or the displacement if there is one 271 // 5. segmentreg (register) x86_registerNONE for now, but could be set 272 // if we have segment overrides 273 274 MCOperand baseReg; 275 MCOperand scaleAmount; 276 MCOperand indexReg; 277 MCOperand displacement; 278 MCOperand segmentReg; 279 280 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 281 if (insn.sibBase != SIB_BASE_NONE) { 282 switch (insn.sibBase) { 283 default: 284 debug("Unexpected sibBase"); 285 return true; 286 #define ENTRY(x) \ 287 case SIB_BASE_##x: \ 288 baseReg = MCOperand::CreateReg(X86::x); break; 289 ALL_SIB_BASES 290 #undef ENTRY 291 } 292 } else { 293 baseReg = MCOperand::CreateReg(0); 294 } 295 296 if (insn.sibIndex != SIB_INDEX_NONE) { 297 switch (insn.sibIndex) { 298 default: 299 debug("Unexpected sibIndex"); 300 return true; 301 #define ENTRY(x) \ 302 case SIB_INDEX_##x: \ 303 indexReg = MCOperand::CreateReg(X86::x); break; 304 EA_BASES_32BIT 305 EA_BASES_64BIT 306 #undef ENTRY 307 } 308 } else { 309 indexReg = MCOperand::CreateReg(0); 310 } 311 312 scaleAmount = MCOperand::CreateImm(insn.sibScale); 313 } else { 314 switch (insn.eaBase) { 315 case EA_BASE_NONE: 316 if (insn.eaDisplacement == EA_DISP_NONE) { 317 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 318 return true; 319 } 320 if (insn.mode == MODE_64BIT) 321 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6 322 else 323 baseReg = MCOperand::CreateReg(0); 324 325 indexReg = MCOperand::CreateReg(0); 326 break; 327 case EA_BASE_BX_SI: 328 baseReg = MCOperand::CreateReg(X86::BX); 329 indexReg = MCOperand::CreateReg(X86::SI); 330 break; 331 case EA_BASE_BX_DI: 332 baseReg = MCOperand::CreateReg(X86::BX); 333 indexReg = MCOperand::CreateReg(X86::DI); 334 break; 335 case EA_BASE_BP_SI: 336 baseReg = MCOperand::CreateReg(X86::BP); 337 indexReg = MCOperand::CreateReg(X86::SI); 338 break; 339 case EA_BASE_BP_DI: 340 baseReg = MCOperand::CreateReg(X86::BP); 341 indexReg = MCOperand::CreateReg(X86::DI); 342 break; 343 default: 344 indexReg = MCOperand::CreateReg(0); 345 switch (insn.eaBase) { 346 default: 347 debug("Unexpected eaBase"); 348 return true; 349 // Here, we will use the fill-ins defined above. However, 350 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 351 // sib and sib64 were handled in the top-level if, so they're only 352 // placeholders to keep the compiler happy. 353 #define ENTRY(x) \ 354 case EA_BASE_##x: \ 355 baseReg = MCOperand::CreateReg(X86::x); break; 356 ALL_EA_BASES 357 #undef ENTRY 358 #define ENTRY(x) case EA_REG_##x: 359 ALL_REGS 360 #undef ENTRY 361 debug("A R/M memory operand may not be a register; " 362 "the base field must be a base."); 363 return true; 364 } 365 } 366 367 scaleAmount = MCOperand::CreateImm(1); 368 } 369 370 displacement = MCOperand::CreateImm(insn.displacement); 371 372 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 373 0, // SEG_OVERRIDE_NONE 374 X86::CS, 375 X86::SS, 376 X86::DS, 377 X86::ES, 378 X86::FS, 379 X86::GS 380 }; 381 382 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); 383 384 mcInst.addOperand(baseReg); 385 mcInst.addOperand(scaleAmount); 386 mcInst.addOperand(indexReg); 387 mcInst.addOperand(displacement); 388 389 if (sr) 390 mcInst.addOperand(segmentReg); 391 392 return false; 393 } 394 395 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 396 /// byte of an instruction to LLVM form, and appends it to an MCInst. 397 /// 398 /// @param mcInst - The MCInst to append to. 399 /// @param operand - The operand, as stored in the descriptor table. 400 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 401 /// from. 402 /// @return - 0 on success; nonzero otherwise 403 static bool translateRM(MCInst &mcInst, 404 OperandSpecifier &operand, 405 InternalInstruction &insn) { 406 switch (operand.type) { 407 default: 408 debug("Unexpected type for a R/M operand"); 409 return true; 410 case TYPE_R8: 411 case TYPE_R16: 412 case TYPE_R32: 413 case TYPE_R64: 414 case TYPE_Rv: 415 case TYPE_MM: 416 case TYPE_MM32: 417 case TYPE_MM64: 418 case TYPE_XMM: 419 case TYPE_XMM32: 420 case TYPE_XMM64: 421 case TYPE_XMM128: 422 case TYPE_DEBUGREG: 423 case TYPE_CONTROLREG: 424 return translateRMRegister(mcInst, insn); 425 case TYPE_M: 426 case TYPE_M8: 427 case TYPE_M16: 428 case TYPE_M32: 429 case TYPE_M64: 430 case TYPE_M128: 431 case TYPE_M512: 432 case TYPE_Mv: 433 case TYPE_M32FP: 434 case TYPE_M64FP: 435 case TYPE_M80FP: 436 case TYPE_M16INT: 437 case TYPE_M32INT: 438 case TYPE_M64INT: 439 case TYPE_M1616: 440 case TYPE_M1632: 441 case TYPE_M1664: 442 return translateRMMemory(mcInst, insn, true); 443 case TYPE_LEA: 444 return translateRMMemory(mcInst, insn, false); 445 } 446 } 447 448 /// translateFPRegister - Translates a stack position on the FPU stack to its 449 /// LLVM form, and appends it to an MCInst. 450 /// 451 /// @param mcInst - The MCInst to append to. 452 /// @param stackPos - The stack position to translate. 453 /// @return - 0 on success; nonzero otherwise. 454 static bool translateFPRegister(MCInst &mcInst, 455 uint8_t stackPos) { 456 if (stackPos >= 8) { 457 debug("Invalid FP stack position"); 458 return true; 459 } 460 461 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos)); 462 463 return false; 464 } 465 466 /// translateOperand - Translates an operand stored in an internal instruction 467 /// to LLVM's format and appends it to an MCInst. 468 /// 469 /// @param mcInst - The MCInst to append to. 470 /// @param operand - The operand, as stored in the descriptor table. 471 /// @param insn - The internal instruction. 472 /// @return - false on success; true otherwise. 473 static bool translateOperand(MCInst &mcInst, 474 OperandSpecifier &operand, 475 InternalInstruction &insn) { 476 switch (operand.encoding) { 477 default: 478 debug("Unhandled operand encoding during translation"); 479 return true; 480 case ENCODING_REG: 481 translateRegister(mcInst, insn.reg); 482 return false; 483 case ENCODING_RM: 484 return translateRM(mcInst, operand, insn); 485 case ENCODING_CB: 486 case ENCODING_CW: 487 case ENCODING_CD: 488 case ENCODING_CP: 489 case ENCODING_CO: 490 case ENCODING_CT: 491 debug("Translation of code offsets isn't supported."); 492 return true; 493 case ENCODING_IB: 494 case ENCODING_IW: 495 case ENCODING_ID: 496 case ENCODING_IO: 497 case ENCODING_Iv: 498 case ENCODING_Ia: 499 translateImmediate(mcInst, 500 insn.immediates[insn.numImmediatesTranslated++], 501 operand, 502 insn); 503 return false; 504 case ENCODING_RB: 505 case ENCODING_RW: 506 case ENCODING_RD: 507 case ENCODING_RO: 508 translateRegister(mcInst, insn.opcodeRegister); 509 return false; 510 case ENCODING_I: 511 return translateFPRegister(mcInst, insn.opcodeModifier); 512 case ENCODING_Rv: 513 translateRegister(mcInst, insn.opcodeRegister); 514 return false; 515 case ENCODING_DUP: 516 return translateOperand(mcInst, 517 insn.spec->operands[operand.type - TYPE_DUP0], 518 insn); 519 } 520 } 521 522 /// translateInstruction - Translates an internal instruction and all its 523 /// operands to an MCInst. 524 /// 525 /// @param mcInst - The MCInst to populate with the instruction's data. 526 /// @param insn - The internal instruction. 527 /// @return - false on success; true otherwise. 528 static bool translateInstruction(MCInst &mcInst, 529 InternalInstruction &insn) { 530 if (!insn.spec) { 531 debug("Instruction has no specification"); 532 return true; 533 } 534 535 mcInst.setOpcode(insn.instructionID); 536 537 int index; 538 539 insn.numImmediatesTranslated = 0; 540 541 for (index = 0; index < X86_MAX_OPERANDS; ++index) { 542 if (insn.spec->operands[index].encoding != ENCODING_NONE) { 543 if (translateOperand(mcInst, insn.spec->operands[index], insn)) { 544 return true; 545 } 546 } 547 } 548 549 return false; 550 } 551 552 static MCDisassembler *createX86_32Disassembler(const Target &T) { 553 return new X86Disassembler::X86_32Disassembler; 554 } 555 556 static MCDisassembler *createX86_64Disassembler(const Target &T) { 557 return new X86Disassembler::X86_64Disassembler; 558 } 559 560 extern "C" void LLVMInitializeX86Disassembler() { 561 // Register the disassembler. 562 TargetRegistry::RegisterMCDisassembler(TheX86_32Target, 563 createX86_32Disassembler); 564 TargetRegistry::RegisterMCDisassembler(TheX86_64Target, 565 createX86_64Disassembler); 566 } 567