1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // 14 // 15 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and 16 // 64-bit X86 instruction sets. The main decode sequence for an assembly 17 // instruction in this disassembler is: 18 // 19 // 1. Read the prefix bytes and determine the attributes of the instruction. 20 // These attributes, recorded in enum attributeBits 21 // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM 22 // provides a mapping from bitmasks to contexts, which are represented by 23 // enum InstructionContext (ibid.). 24 // 25 // 2. Read the opcode, and determine what kind of opcode it is. The 26 // disassembler distinguishes four kinds of opcodes, which are enumerated in 27 // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte 28 // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a 29 // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. 30 // 31 // 3. Depending on the opcode type, look in one of four ClassDecision structures 32 // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which 33 // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get 34 // a ModRMDecision (ibid.). 35 // 36 // 4. Some instructions, such as escape opcodes or extended opcodes, or even 37 // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the 38 // ModR/M byte to complete decode. The ModRMDecision's type is an entry from 39 // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the 40 // ModR/M byte is required and how to interpret it. 41 // 42 // 5. After resolving the ModRMDecision, the disassembler has a unique ID 43 // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in 44 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and 45 // meanings of its operands. 46 // 47 // 6. For each operand, its encoding is an entry from OperandEncoding 48 // (X86DisassemblerDecoderCommon.h) and its type is an entry from 49 // OperandType (ibid.). The encoding indicates how to read it from the 50 // instruction; the type indicates how to interpret the value once it has 51 // been read. For example, a register operand could be stored in the R/M 52 // field of the ModR/M byte, the REG field of the ModR/M byte, or added to 53 // the main opcode. This is orthogonal from its meaning (an GPR or an XMM 54 // register, for instance). Given this information, the operands can be 55 // extracted and interpreted. 56 // 57 // 7. As the last step, the disassembler translates the instruction information 58 // and operands into a format understandable by the client - in this case, an 59 // MCInst for use by the MC infrastructure. 60 // 61 // The disassembler is broken broadly into two parts: the table emitter that 62 // emits the instruction decode tables discussed above during compilation, and 63 // the disassembler itself. The table emitter is documented in more detail in 64 // utils/TableGen/X86DisassemblerEmitter.h. 65 // 66 // X86Disassembler.cpp contains the code responsible for step 7, and for 67 // invoking the decoder to execute steps 1-6. 68 // X86DisassemblerDecoderCommon.h contains the definitions needed by both the 69 // table emitter and the disassembler. 70 // X86DisassemblerDecoder.h contains the public interface of the decoder, 71 // factored out into C for possible use by other projects. 72 // X86DisassemblerDecoder.c contains the source code of the decoder, which is 73 // responsible for steps 1-6. 74 // 75 //===----------------------------------------------------------------------===// 76 77 #include "MCTargetDesc/X86MCTargetDesc.h" 78 #include "X86DisassemblerDecoder.h" 79 #include "llvm/MC/MCContext.h" 80 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 81 #include "llvm/MC/MCExpr.h" 82 #include "llvm/MC/MCInst.h" 83 #include "llvm/MC/MCInstrInfo.h" 84 #include "llvm/MC/MCSubtargetInfo.h" 85 #include "llvm/Support/Debug.h" 86 #include "llvm/Support/TargetRegistry.h" 87 #include "llvm/Support/raw_ostream.h" 88 89 using namespace llvm; 90 using namespace llvm::X86Disassembler; 91 92 #define DEBUG_TYPE "x86-disassembler" 93 94 void llvm::X86Disassembler::Debug(const char *file, unsigned line, 95 const char *s) { 96 dbgs() << file << ":" << line << ": " << s; 97 } 98 99 StringRef llvm::X86Disassembler::GetInstrName(unsigned Opcode, 100 const void *mii) { 101 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii); 102 return MII->getName(Opcode); 103 } 104 105 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s)); 106 107 namespace llvm { 108 109 // Fill-ins to make the compiler happy. These constants are never actually 110 // assigned; they are just filler to make an automatically-generated switch 111 // statement work. 112 namespace X86 { 113 enum { 114 BX_SI = 500, 115 BX_DI = 501, 116 BP_SI = 502, 117 BP_DI = 503, 118 sib = 504, 119 sib64 = 505 120 }; 121 } 122 123 } 124 125 static bool translateInstruction(MCInst &target, 126 InternalInstruction &source, 127 const MCDisassembler *Dis); 128 129 namespace { 130 131 /// Generic disassembler for all X86 platforms. All each platform class should 132 /// have to do is subclass the constructor, and provide a different 133 /// disassemblerMode value. 134 class X86GenericDisassembler : public MCDisassembler { 135 std::unique_ptr<const MCInstrInfo> MII; 136 public: 137 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 138 std::unique_ptr<const MCInstrInfo> MII); 139 public: 140 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 141 ArrayRef<uint8_t> Bytes, uint64_t Address, 142 raw_ostream &vStream, 143 raw_ostream &cStream) const override; 144 145 private: 146 DisassemblerMode fMode; 147 }; 148 149 } 150 151 X86GenericDisassembler::X86GenericDisassembler( 152 const MCSubtargetInfo &STI, 153 MCContext &Ctx, 154 std::unique_ptr<const MCInstrInfo> MII) 155 : MCDisassembler(STI, Ctx), MII(std::move(MII)) { 156 const FeatureBitset &FB = STI.getFeatureBits(); 157 if (FB[X86::Mode16Bit]) { 158 fMode = MODE_16BIT; 159 return; 160 } else if (FB[X86::Mode32Bit]) { 161 fMode = MODE_32BIT; 162 return; 163 } else if (FB[X86::Mode64Bit]) { 164 fMode = MODE_64BIT; 165 return; 166 } 167 168 llvm_unreachable("Invalid CPU mode"); 169 } 170 171 namespace { 172 struct Region { 173 ArrayRef<uint8_t> Bytes; 174 uint64_t Base; 175 Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {} 176 }; 177 } // end anonymous namespace 178 179 /// A callback function that wraps the readByte method from Region. 180 /// 181 /// @param Arg - The generic callback parameter. In this case, this should 182 /// be a pointer to a Region. 183 /// @param Byte - A pointer to the byte to be read. 184 /// @param Address - The address to be read. 185 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) { 186 auto *R = static_cast<const Region *>(Arg); 187 ArrayRef<uint8_t> Bytes = R->Bytes; 188 unsigned Index = Address - R->Base; 189 if (Bytes.size() <= Index) 190 return -1; 191 *Byte = Bytes[Index]; 192 return 0; 193 } 194 195 /// logger - a callback function that wraps the operator<< method from 196 /// raw_ostream. 197 /// 198 /// @param arg - The generic callback parameter. This should be a pointe 199 /// to a raw_ostream. 200 /// @param log - A string to be logged. logger() adds a newline. 201 static void logger(void* arg, const char* log) { 202 if (!arg) 203 return; 204 205 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 206 vStream << log << "\n"; 207 } 208 209 // 210 // Public interface for the disassembler 211 // 212 213 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( 214 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, 215 raw_ostream &VStream, raw_ostream &CStream) const { 216 CommentStream = &CStream; 217 218 InternalInstruction InternalInstr; 219 220 dlog_t LoggerFn = logger; 221 if (&VStream == &nulls()) 222 LoggerFn = nullptr; // Disable logging completely if it's going to nulls(). 223 224 Region R(Bytes, Address); 225 226 int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R, 227 LoggerFn, (void *)&VStream, 228 (const void *)MII.get(), Address, fMode); 229 230 if (Ret) { 231 Size = InternalInstr.readerCursor - Address; 232 return Fail; 233 } else { 234 Size = InternalInstr.length; 235 return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail; 236 } 237 } 238 239 // 240 // Private code that translates from struct InternalInstructions to MCInsts. 241 // 242 243 /// translateRegister - Translates an internal register to the appropriate LLVM 244 /// register, and appends it as an operand to an MCInst. 245 /// 246 /// @param mcInst - The MCInst to append to. 247 /// @param reg - The Reg to append. 248 static void translateRegister(MCInst &mcInst, Reg reg) { 249 #define ENTRY(x) X86::x, 250 uint8_t llvmRegnums[] = { 251 ALL_REGS 252 0 253 }; 254 #undef ENTRY 255 256 uint8_t llvmRegnum = llvmRegnums[reg]; 257 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); 258 } 259 260 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 261 /// immediate Value in the MCInst. 262 /// 263 /// @param Value - The immediate Value, has had any PC adjustment made by 264 /// the caller. 265 /// @param isBranch - If the instruction is a branch instruction 266 /// @param Address - The starting address of the instruction 267 /// @param Offset - The byte offset to this immediate in the instruction 268 /// @param Width - The byte width of this immediate in the instruction 269 /// 270 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was 271 /// called then that function is called to get any symbolic information for the 272 /// immediate in the instruction using the Address, Offset and Width. If that 273 /// returns non-zero then the symbolic information it returns is used to create 274 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo() 275 /// returns zero and isBranch is true then a symbol look up for immediate Value 276 /// is done and if a symbol is found an MCExpr is created with that, else 277 /// an MCExpr with the immediate Value is created. This function returns true 278 /// if it adds an operand to the MCInst and false otherwise. 279 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 280 uint64_t Address, uint64_t Offset, 281 uint64_t Width, MCInst &MI, 282 const MCDisassembler *Dis) { 283 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 284 Offset, Width); 285 } 286 287 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 288 /// referenced by a load instruction with the base register that is the rip. 289 /// These can often be addresses in a literal pool. The Address of the 290 /// instruction and its immediate Value are used to determine the address 291 /// being referenced in the literal pool entry. The SymbolLookUp call back will 292 /// return a pointer to a literal 'C' string if the referenced address is an 293 /// address into a section with 'C' string literals. 294 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, 295 const void *Decoder) { 296 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 297 Dis->tryAddingPcLoadReferenceComment(Value, Address); 298 } 299 300 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 301 0, // SEG_OVERRIDE_NONE 302 X86::CS, 303 X86::SS, 304 X86::DS, 305 X86::ES, 306 X86::FS, 307 X86::GS 308 }; 309 310 /// translateSrcIndex - Appends a source index operand to an MCInst. 311 /// 312 /// @param mcInst - The MCInst to append to. 313 /// @param insn - The internal instruction. 314 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { 315 unsigned baseRegNo; 316 317 if (insn.mode == MODE_64BIT) 318 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI; 319 else if (insn.mode == MODE_32BIT) 320 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI; 321 else { 322 assert(insn.mode == MODE_16BIT); 323 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI; 324 } 325 MCOperand baseReg = MCOperand::createReg(baseRegNo); 326 mcInst.addOperand(baseReg); 327 328 MCOperand segmentReg; 329 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 330 mcInst.addOperand(segmentReg); 331 return false; 332 } 333 334 /// translateDstIndex - Appends a destination index operand to an MCInst. 335 /// 336 /// @param mcInst - The MCInst to append to. 337 /// @param insn - The internal instruction. 338 339 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { 340 unsigned baseRegNo; 341 342 if (insn.mode == MODE_64BIT) 343 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI; 344 else if (insn.mode == MODE_32BIT) 345 baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI; 346 else { 347 assert(insn.mode == MODE_16BIT); 348 baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI; 349 } 350 MCOperand baseReg = MCOperand::createReg(baseRegNo); 351 mcInst.addOperand(baseReg); 352 return false; 353 } 354 355 /// translateImmediate - Appends an immediate operand to an MCInst. 356 /// 357 /// @param mcInst - The MCInst to append to. 358 /// @param immediate - The immediate value to append. 359 /// @param operand - The operand, as stored in the descriptor table. 360 /// @param insn - The internal instruction. 361 static void translateImmediate(MCInst &mcInst, uint64_t immediate, 362 const OperandSpecifier &operand, 363 InternalInstruction &insn, 364 const MCDisassembler *Dis) { 365 // Sign-extend the immediate if necessary. 366 367 OperandType type = (OperandType)operand.type; 368 369 bool isBranch = false; 370 uint64_t pcrel = 0; 371 if (type == TYPE_REL) { 372 isBranch = true; 373 pcrel = insn.startLocation + 374 insn.immediateOffset + insn.immediateSize; 375 switch (operand.encoding) { 376 default: 377 break; 378 case ENCODING_Iv: 379 switch (insn.displacementSize) { 380 default: 381 break; 382 case 1: 383 if(immediate & 0x80) 384 immediate |= ~(0xffull); 385 break; 386 case 2: 387 if(immediate & 0x8000) 388 immediate |= ~(0xffffull); 389 break; 390 case 4: 391 if(immediate & 0x80000000) 392 immediate |= ~(0xffffffffull); 393 break; 394 case 8: 395 break; 396 } 397 break; 398 case ENCODING_IB: 399 if(immediate & 0x80) 400 immediate |= ~(0xffull); 401 break; 402 case ENCODING_IW: 403 if(immediate & 0x8000) 404 immediate |= ~(0xffffull); 405 break; 406 case ENCODING_ID: 407 if(immediate & 0x80000000) 408 immediate |= ~(0xffffffffull); 409 break; 410 } 411 } 412 // By default sign-extend all X86 immediates based on their encoding. 413 else if (type == TYPE_IMM) { 414 switch (operand.encoding) { 415 default: 416 break; 417 case ENCODING_IB: 418 if(immediate & 0x80) 419 immediate |= ~(0xffull); 420 break; 421 case ENCODING_IW: 422 if(immediate & 0x8000) 423 immediate |= ~(0xffffull); 424 break; 425 case ENCODING_ID: 426 if(immediate & 0x80000000) 427 immediate |= ~(0xffffffffull); 428 break; 429 case ENCODING_IO: 430 break; 431 } 432 } else if (type == TYPE_IMM3) { 433 // Check for immediates that printSSECC can't handle. 434 if (immediate >= 8) { 435 unsigned NewOpc; 436 switch (mcInst.getOpcode()) { 437 default: llvm_unreachable("unexpected opcode"); 438 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; 439 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; 440 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; 441 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; 442 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; 443 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; 444 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; 445 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; 446 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; 447 case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break; 448 case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break; 449 case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break; 450 case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break; 451 case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break; 452 case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break; 453 case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break; 454 case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break; 455 case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break; 456 case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break; 457 case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break; 458 case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break; 459 case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break; 460 case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break; 461 case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break; 462 } 463 // Switch opcode to the one that doesn't get special printing. 464 mcInst.setOpcode(NewOpc); 465 } 466 } else if (type == TYPE_IMM5) { 467 // Check for immediates that printAVXCC can't handle. 468 if (immediate >= 32) { 469 unsigned NewOpc; 470 switch (mcInst.getOpcode()) { 471 default: llvm_unreachable("unexpected opcode"); 472 case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break; 473 case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break; 474 case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break; 475 case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break; 476 case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break; 477 case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break; 478 case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break; 479 case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break; 480 case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break; 481 case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break; 482 case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break; 483 case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break; 484 case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break; 485 case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break; 486 case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break; 487 case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break; 488 case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break; 489 case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break; 490 case X86::VCMPPDZ128rmi: NewOpc = X86::VCMPPDZ128rmi_alt; break; 491 case X86::VCMPPDZ128rri: NewOpc = X86::VCMPPDZ128rri_alt; break; 492 case X86::VCMPPSZ128rmi: NewOpc = X86::VCMPPSZ128rmi_alt; break; 493 case X86::VCMPPSZ128rri: NewOpc = X86::VCMPPSZ128rri_alt; break; 494 case X86::VCMPPDZ256rmi: NewOpc = X86::VCMPPDZ256rmi_alt; break; 495 case X86::VCMPPDZ256rri: NewOpc = X86::VCMPPDZ256rri_alt; break; 496 case X86::VCMPPSZ256rmi: NewOpc = X86::VCMPPSZ256rmi_alt; break; 497 case X86::VCMPPSZ256rri: NewOpc = X86::VCMPPSZ256rri_alt; break; 498 case X86::VCMPSDZrm_Int: NewOpc = X86::VCMPSDZrmi_alt; break; 499 case X86::VCMPSDZrr_Int: NewOpc = X86::VCMPSDZrri_alt; break; 500 case X86::VCMPSDZrrb_Int: NewOpc = X86::VCMPSDZrrb_alt; break; 501 case X86::VCMPSSZrm_Int: NewOpc = X86::VCMPSSZrmi_alt; break; 502 case X86::VCMPSSZrr_Int: NewOpc = X86::VCMPSSZrri_alt; break; 503 case X86::VCMPSSZrrb_Int: NewOpc = X86::VCMPSSZrrb_alt; break; 504 } 505 // Switch opcode to the one that doesn't get special printing. 506 mcInst.setOpcode(NewOpc); 507 } 508 } else if (type == TYPE_AVX512ICC) { 509 if (immediate >= 8 || ((immediate & 0x3) == 3)) { 510 unsigned NewOpc; 511 switch (mcInst.getOpcode()) { 512 default: llvm_unreachable("unexpected opcode"); 513 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break; 514 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break; 515 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break; 516 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break; 517 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break; 518 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break; 519 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break; 520 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break; 521 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break; 522 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break; 523 case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break; 524 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break; 525 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break; 526 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break; 527 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break; 528 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break; 529 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break; 530 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break; 531 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break; 532 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break; 533 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break; 534 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break; 535 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break; 536 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break; 537 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break; 538 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break; 539 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break; 540 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break; 541 case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break; 542 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break; 543 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break; 544 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break; 545 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break; 546 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break; 547 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break; 548 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break; 549 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break; 550 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break; 551 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break; 552 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break; 553 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break; 554 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break; 555 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break; 556 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break; 557 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break; 558 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break; 559 case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break; 560 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break; 561 case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break; 562 case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break; 563 case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break; 564 case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break; 565 case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break; 566 case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break; 567 case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break; 568 case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break; 569 case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break; 570 case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break; 571 case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break; 572 case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break; 573 case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break; 574 case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break; 575 case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break; 576 case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break; 577 case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break; 578 case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break; 579 case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break; 580 case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break; 581 case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break; 582 case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break; 583 case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break; 584 case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break; 585 case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break; 586 case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break; 587 case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break; 588 case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break; 589 case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break; 590 case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break; 591 case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break; 592 case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break; 593 case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break; 594 case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break; 595 case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break; 596 case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break; 597 case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break; 598 case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break; 599 case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break; 600 case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break; 601 case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break; 602 case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break; 603 case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break; 604 case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break; 605 case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break; 606 case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break; 607 case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break; 608 case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break; 609 case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break; 610 case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break; 611 case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break; 612 case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break; 613 case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break; 614 case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break; 615 case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break; 616 case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break; 617 case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break; 618 case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break; 619 case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break; 620 case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break; 621 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break; 622 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break; 623 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break; 624 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break; 625 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break; 626 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break; 627 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break; 628 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break; 629 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break; 630 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break; 631 case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break; 632 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break; 633 } 634 // Switch opcode to the one that doesn't get special printing. 635 mcInst.setOpcode(NewOpc); 636 } 637 } 638 639 switch (type) { 640 case TYPE_XMM: 641 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); 642 return; 643 case TYPE_YMM: 644 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); 645 return; 646 case TYPE_ZMM: 647 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); 648 return; 649 case TYPE_BNDR: 650 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); 651 default: 652 // operand is 64 bits wide. Do nothing. 653 break; 654 } 655 656 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, 657 insn.immediateOffset, insn.immediateSize, 658 mcInst, Dis)) 659 mcInst.addOperand(MCOperand::createImm(immediate)); 660 661 if (type == TYPE_MOFFS) { 662 MCOperand segmentReg; 663 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 664 mcInst.addOperand(segmentReg); 665 } 666 } 667 668 /// translateRMRegister - Translates a register stored in the R/M field of the 669 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 670 /// @param mcInst - The MCInst to append to. 671 /// @param insn - The internal instruction to extract the R/M field 672 /// from. 673 /// @return - 0 on success; -1 otherwise 674 static bool translateRMRegister(MCInst &mcInst, 675 InternalInstruction &insn) { 676 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 677 debug("A R/M register operand may not have a SIB byte"); 678 return true; 679 } 680 681 switch (insn.eaBase) { 682 default: 683 debug("Unexpected EA base register"); 684 return true; 685 case EA_BASE_NONE: 686 debug("EA_BASE_NONE for ModR/M base"); 687 return true; 688 #define ENTRY(x) case EA_BASE_##x: 689 ALL_EA_BASES 690 #undef ENTRY 691 debug("A R/M register operand may not have a base; " 692 "the operand must be a register."); 693 return true; 694 #define ENTRY(x) \ 695 case EA_REG_##x: \ 696 mcInst.addOperand(MCOperand::createReg(X86::x)); break; 697 ALL_REGS 698 #undef ENTRY 699 } 700 701 return false; 702 } 703 704 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 705 /// fields of an internal instruction (and possibly its SIB byte) to a memory 706 /// operand in LLVM's format, and appends it to an MCInst. 707 /// 708 /// @param mcInst - The MCInst to append to. 709 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 710 /// from. 711 /// @return - 0 on success; nonzero otherwise 712 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, 713 const MCDisassembler *Dis) { 714 // Addresses in an MCInst are represented as five operands: 715 // 1. basereg (register) The R/M base, or (if there is a SIB) the 716 // SIB base 717 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 718 // scale amount 719 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 720 // the index (which is multiplied by the 721 // scale amount) 722 // 4. displacement (immediate) 0, or the displacement if there is one 723 // 5. segmentreg (register) x86_registerNONE for now, but could be set 724 // if we have segment overrides 725 726 MCOperand baseReg; 727 MCOperand scaleAmount; 728 MCOperand indexReg; 729 MCOperand displacement; 730 MCOperand segmentReg; 731 uint64_t pcrel = 0; 732 733 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 734 if (insn.sibBase != SIB_BASE_NONE) { 735 switch (insn.sibBase) { 736 default: 737 debug("Unexpected sibBase"); 738 return true; 739 #define ENTRY(x) \ 740 case SIB_BASE_##x: \ 741 baseReg = MCOperand::createReg(X86::x); break; 742 ALL_SIB_BASES 743 #undef ENTRY 744 } 745 } else { 746 baseReg = MCOperand::createReg(0); 747 } 748 749 // Check whether we are handling VSIB addressing mode for GATHER. 750 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and 751 // we should use SIB_INDEX_XMM4|YMM4 for VSIB. 752 // I don't see a way to get the correct IndexReg in readSIB: 753 // We can tell whether it is VSIB or SIB after instruction ID is decoded, 754 // but instruction ID may not be decoded yet when calling readSIB. 755 uint32_t Opcode = mcInst.getOpcode(); 756 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm || 757 Opcode == X86::VGATHERDPDYrm || 758 Opcode == X86::VGATHERQPDrm || 759 Opcode == X86::VGATHERDPSrm || 760 Opcode == X86::VGATHERQPSrm || 761 Opcode == X86::VPGATHERDQrm || 762 Opcode == X86::VPGATHERDQYrm || 763 Opcode == X86::VPGATHERQQrm || 764 Opcode == X86::VPGATHERDDrm || 765 Opcode == X86::VPGATHERQDrm || 766 Opcode == X86::VGATHERDPDZ128rm || 767 Opcode == X86::VGATHERDPDZ256rm || 768 Opcode == X86::VGATHERDPSZ128rm || 769 Opcode == X86::VGATHERQPDZ128rm || 770 Opcode == X86::VGATHERQPSZ128rm || 771 Opcode == X86::VPGATHERDDZ128rm || 772 Opcode == X86::VPGATHERDQZ128rm || 773 Opcode == X86::VPGATHERDQZ256rm || 774 Opcode == X86::VPGATHERQDZ128rm || 775 Opcode == X86::VPGATHERQQZ128rm || 776 Opcode == X86::VSCATTERDPDZ128mr || 777 Opcode == X86::VSCATTERDPDZ256mr || 778 Opcode == X86::VSCATTERDPSZ128mr || 779 Opcode == X86::VSCATTERQPDZ128mr || 780 Opcode == X86::VSCATTERQPSZ128mr || 781 Opcode == X86::VPSCATTERDDZ128mr || 782 Opcode == X86::VPSCATTERDQZ128mr || 783 Opcode == X86::VPSCATTERDQZ256mr || 784 Opcode == X86::VPSCATTERQDZ128mr || 785 Opcode == X86::VPSCATTERQQZ128mr); 786 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm || 787 Opcode == X86::VGATHERDPSYrm || 788 Opcode == X86::VGATHERQPSYrm || 789 Opcode == X86::VGATHERDPDZrm || 790 Opcode == X86::VPGATHERDQZrm || 791 Opcode == X86::VPGATHERQQYrm || 792 Opcode == X86::VPGATHERDDYrm || 793 Opcode == X86::VPGATHERQDYrm || 794 Opcode == X86::VGATHERDPSZ256rm || 795 Opcode == X86::VGATHERQPDZ256rm || 796 Opcode == X86::VGATHERQPSZ256rm || 797 Opcode == X86::VPGATHERDDZ256rm || 798 Opcode == X86::VPGATHERQQZ256rm || 799 Opcode == X86::VPGATHERQDZ256rm || 800 Opcode == X86::VSCATTERDPDZmr || 801 Opcode == X86::VPSCATTERDQZmr || 802 Opcode == X86::VSCATTERDPSZ256mr || 803 Opcode == X86::VSCATTERQPDZ256mr || 804 Opcode == X86::VSCATTERQPSZ256mr || 805 Opcode == X86::VPSCATTERDDZ256mr || 806 Opcode == X86::VPSCATTERQQZ256mr || 807 Opcode == X86::VPSCATTERQDZ256mr || 808 Opcode == X86::VGATHERPF0DPDm || 809 Opcode == X86::VGATHERPF1DPDm || 810 Opcode == X86::VSCATTERPF0DPDm || 811 Opcode == X86::VSCATTERPF1DPDm); 812 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm || 813 Opcode == X86::VGATHERDPSZrm || 814 Opcode == X86::VGATHERQPSZrm || 815 Opcode == X86::VPGATHERQQZrm || 816 Opcode == X86::VPGATHERDDZrm || 817 Opcode == X86::VPGATHERQDZrm || 818 Opcode == X86::VSCATTERQPDZmr || 819 Opcode == X86::VSCATTERDPSZmr || 820 Opcode == X86::VSCATTERQPSZmr || 821 Opcode == X86::VPSCATTERQQZmr || 822 Opcode == X86::VPSCATTERDDZmr || 823 Opcode == X86::VPSCATTERQDZmr || 824 Opcode == X86::VGATHERPF0DPSm || 825 Opcode == X86::VGATHERPF0QPDm || 826 Opcode == X86::VGATHERPF0QPSm || 827 Opcode == X86::VGATHERPF1DPSm || 828 Opcode == X86::VGATHERPF1QPDm || 829 Opcode == X86::VGATHERPF1QPSm || 830 Opcode == X86::VSCATTERPF0DPSm || 831 Opcode == X86::VSCATTERPF0QPDm || 832 Opcode == X86::VSCATTERPF0QPSm || 833 Opcode == X86::VSCATTERPF1DPSm || 834 Opcode == X86::VSCATTERPF1QPDm || 835 Opcode == X86::VSCATTERPF1QPSm); 836 if (IndexIs128 || IndexIs256 || IndexIs512) { 837 unsigned IndexOffset = insn.sibIndex - 838 (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX); 839 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 : 840 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0; 841 insn.sibIndex = (SIBIndex)(IndexBase + 842 (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset)); 843 } 844 845 if (insn.sibIndex != SIB_INDEX_NONE) { 846 switch (insn.sibIndex) { 847 default: 848 debug("Unexpected sibIndex"); 849 return true; 850 #define ENTRY(x) \ 851 case SIB_INDEX_##x: \ 852 indexReg = MCOperand::createReg(X86::x); break; 853 EA_BASES_32BIT 854 EA_BASES_64BIT 855 REGS_XMM 856 REGS_YMM 857 REGS_ZMM 858 #undef ENTRY 859 } 860 } else { 861 indexReg = MCOperand::createReg(0); 862 } 863 864 scaleAmount = MCOperand::createImm(insn.sibScale); 865 } else { 866 switch (insn.eaBase) { 867 case EA_BASE_NONE: 868 if (insn.eaDisplacement == EA_DISP_NONE) { 869 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 870 return true; 871 } 872 if (insn.mode == MODE_64BIT){ 873 pcrel = insn.startLocation + 874 insn.displacementOffset + insn.displacementSize; 875 tryAddingPcLoadReferenceComment(insn.startLocation + 876 insn.displacementOffset, 877 insn.displacement + pcrel, Dis); 878 baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6 879 } 880 else 881 baseReg = MCOperand::createReg(0); 882 883 indexReg = MCOperand::createReg(0); 884 break; 885 case EA_BASE_BX_SI: 886 baseReg = MCOperand::createReg(X86::BX); 887 indexReg = MCOperand::createReg(X86::SI); 888 break; 889 case EA_BASE_BX_DI: 890 baseReg = MCOperand::createReg(X86::BX); 891 indexReg = MCOperand::createReg(X86::DI); 892 break; 893 case EA_BASE_BP_SI: 894 baseReg = MCOperand::createReg(X86::BP); 895 indexReg = MCOperand::createReg(X86::SI); 896 break; 897 case EA_BASE_BP_DI: 898 baseReg = MCOperand::createReg(X86::BP); 899 indexReg = MCOperand::createReg(X86::DI); 900 break; 901 default: 902 indexReg = MCOperand::createReg(0); 903 switch (insn.eaBase) { 904 default: 905 debug("Unexpected eaBase"); 906 return true; 907 // Here, we will use the fill-ins defined above. However, 908 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 909 // sib and sib64 were handled in the top-level if, so they're only 910 // placeholders to keep the compiler happy. 911 #define ENTRY(x) \ 912 case EA_BASE_##x: \ 913 baseReg = MCOperand::createReg(X86::x); break; 914 ALL_EA_BASES 915 #undef ENTRY 916 #define ENTRY(x) case EA_REG_##x: 917 ALL_REGS 918 #undef ENTRY 919 debug("A R/M memory operand may not be a register; " 920 "the base field must be a base."); 921 return true; 922 } 923 } 924 925 scaleAmount = MCOperand::createImm(1); 926 } 927 928 displacement = MCOperand::createImm(insn.displacement); 929 930 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 931 932 mcInst.addOperand(baseReg); 933 mcInst.addOperand(scaleAmount); 934 mcInst.addOperand(indexReg); 935 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false, 936 insn.startLocation, insn.displacementOffset, 937 insn.displacementSize, mcInst, Dis)) 938 mcInst.addOperand(displacement); 939 mcInst.addOperand(segmentReg); 940 return false; 941 } 942 943 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 944 /// byte of an instruction to LLVM form, and appends it to an MCInst. 945 /// 946 /// @param mcInst - The MCInst to append to. 947 /// @param operand - The operand, as stored in the descriptor table. 948 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 949 /// from. 950 /// @return - 0 on success; nonzero otherwise 951 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, 952 InternalInstruction &insn, const MCDisassembler *Dis) { 953 switch (operand.type) { 954 default: 955 debug("Unexpected type for a R/M operand"); 956 return true; 957 case TYPE_R8: 958 case TYPE_R16: 959 case TYPE_R32: 960 case TYPE_R64: 961 case TYPE_Rv: 962 case TYPE_MM64: 963 case TYPE_XMM: 964 case TYPE_YMM: 965 case TYPE_ZMM: 966 case TYPE_VK: 967 case TYPE_DEBUGREG: 968 case TYPE_CONTROLREG: 969 case TYPE_BNDR: 970 return translateRMRegister(mcInst, insn); 971 case TYPE_M: 972 return translateRMMemory(mcInst, insn, Dis); 973 } 974 } 975 976 /// translateFPRegister - Translates a stack position on the FPU stack to its 977 /// LLVM form, and appends it to an MCInst. 978 /// 979 /// @param mcInst - The MCInst to append to. 980 /// @param stackPos - The stack position to translate. 981 static void translateFPRegister(MCInst &mcInst, 982 uint8_t stackPos) { 983 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos)); 984 } 985 986 /// translateMaskRegister - Translates a 3-bit mask register number to 987 /// LLVM form, and appends it to an MCInst. 988 /// 989 /// @param mcInst - The MCInst to append to. 990 /// @param maskRegNum - Number of mask register from 0 to 7. 991 /// @return - false on success; true otherwise. 992 static bool translateMaskRegister(MCInst &mcInst, 993 uint8_t maskRegNum) { 994 if (maskRegNum >= 8) { 995 debug("Invalid mask register number"); 996 return true; 997 } 998 999 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum)); 1000 return false; 1001 } 1002 1003 /// translateOperand - Translates an operand stored in an internal instruction 1004 /// to LLVM's format and appends it to an MCInst. 1005 /// 1006 /// @param mcInst - The MCInst to append to. 1007 /// @param operand - The operand, as stored in the descriptor table. 1008 /// @param insn - The internal instruction. 1009 /// @return - false on success; true otherwise. 1010 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, 1011 InternalInstruction &insn, 1012 const MCDisassembler *Dis) { 1013 switch (operand.encoding) { 1014 default: 1015 debug("Unhandled operand encoding during translation"); 1016 return true; 1017 case ENCODING_REG: 1018 translateRegister(mcInst, insn.reg); 1019 return false; 1020 case ENCODING_WRITEMASK: 1021 return translateMaskRegister(mcInst, insn.writemask); 1022 CASE_ENCODING_RM: 1023 CASE_ENCODING_VSIB: 1024 return translateRM(mcInst, operand, insn, Dis); 1025 case ENCODING_IB: 1026 case ENCODING_IW: 1027 case ENCODING_ID: 1028 case ENCODING_IO: 1029 case ENCODING_Iv: 1030 case ENCODING_Ia: 1031 translateImmediate(mcInst, 1032 insn.immediates[insn.numImmediatesTranslated++], 1033 operand, 1034 insn, 1035 Dis); 1036 return false; 1037 case ENCODING_SI: 1038 return translateSrcIndex(mcInst, insn); 1039 case ENCODING_DI: 1040 return translateDstIndex(mcInst, insn); 1041 case ENCODING_RB: 1042 case ENCODING_RW: 1043 case ENCODING_RD: 1044 case ENCODING_RO: 1045 case ENCODING_Rv: 1046 translateRegister(mcInst, insn.opcodeRegister); 1047 return false; 1048 case ENCODING_FP: 1049 translateFPRegister(mcInst, insn.modRM & 7); 1050 return false; 1051 case ENCODING_VVVV: 1052 translateRegister(mcInst, insn.vvvv); 1053 return false; 1054 case ENCODING_DUP: 1055 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0], 1056 insn, Dis); 1057 } 1058 } 1059 1060 /// translateInstruction - Translates an internal instruction and all its 1061 /// operands to an MCInst. 1062 /// 1063 /// @param mcInst - The MCInst to populate with the instruction's data. 1064 /// @param insn - The internal instruction. 1065 /// @return - false on success; true otherwise. 1066 static bool translateInstruction(MCInst &mcInst, 1067 InternalInstruction &insn, 1068 const MCDisassembler *Dis) { 1069 if (!insn.spec) { 1070 debug("Instruction has no specification"); 1071 return true; 1072 } 1073 1074 mcInst.clear(); 1075 mcInst.setOpcode(insn.instructionID); 1076 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 1077 // prefix bytes should be disassembled as xrelease and xacquire then set the 1078 // opcode to those instead of the rep and repne opcodes. 1079 if (insn.xAcquireRelease) { 1080 if(mcInst.getOpcode() == X86::REP_PREFIX) 1081 mcInst.setOpcode(X86::XRELEASE_PREFIX); 1082 else if(mcInst.getOpcode() == X86::REPNE_PREFIX) 1083 mcInst.setOpcode(X86::XACQUIRE_PREFIX); 1084 } 1085 1086 insn.numImmediatesTranslated = 0; 1087 1088 for (const auto &Op : insn.operands) { 1089 if (Op.encoding != ENCODING_NONE) { 1090 if (translateOperand(mcInst, Op, insn, Dis)) { 1091 return true; 1092 } 1093 } 1094 } 1095 1096 return false; 1097 } 1098 1099 static MCDisassembler *createX86Disassembler(const Target &T, 1100 const MCSubtargetInfo &STI, 1101 MCContext &Ctx) { 1102 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); 1103 return new X86GenericDisassembler(STI, Ctx, std::move(MII)); 1104 } 1105 1106 extern "C" void LLVMInitializeX86Disassembler() { 1107 // Register the disassembler. 1108 TargetRegistry::RegisterMCDisassembler(getTheX86_32Target(), 1109 createX86Disassembler); 1110 TargetRegistry::RegisterMCDisassembler(getTheX86_64Target(), 1111 createX86Disassembler); 1112 } 1113