1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // 14 // 15 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and 16 // 64-bit X86 instruction sets. The main decode sequence for an assembly 17 // instruction in this disassembler is: 18 // 19 // 1. Read the prefix bytes and determine the attributes of the instruction. 20 // These attributes, recorded in enum attributeBits 21 // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM 22 // provides a mapping from bitmasks to contexts, which are represented by 23 // enum InstructionContext (ibid.). 24 // 25 // 2. Read the opcode, and determine what kind of opcode it is. The 26 // disassembler distinguishes four kinds of opcodes, which are enumerated in 27 // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte 28 // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a 29 // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. 30 // 31 // 3. Depending on the opcode type, look in one of four ClassDecision structures 32 // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which 33 // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get 34 // a ModRMDecision (ibid.). 35 // 36 // 4. Some instructions, such as escape opcodes or extended opcodes, or even 37 // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the 38 // ModR/M byte to complete decode. The ModRMDecision's type is an entry from 39 // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the 40 // ModR/M byte is required and how to interpret it. 41 // 42 // 5. After resolving the ModRMDecision, the disassembler has a unique ID 43 // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in 44 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and 45 // meanings of its operands. 46 // 47 // 6. For each operand, its encoding is an entry from OperandEncoding 48 // (X86DisassemblerDecoderCommon.h) and its type is an entry from 49 // OperandType (ibid.). The encoding indicates how to read it from the 50 // instruction; the type indicates how to interpret the value once it has 51 // been read. For example, a register operand could be stored in the R/M 52 // field of the ModR/M byte, the REG field of the ModR/M byte, or added to 53 // the main opcode. This is orthogonal from its meaning (an GPR or an XMM 54 // register, for instance). Given this information, the operands can be 55 // extracted and interpreted. 56 // 57 // 7. As the last step, the disassembler translates the instruction information 58 // and operands into a format understandable by the client - in this case, an 59 // MCInst for use by the MC infrastructure. 60 // 61 // The disassembler is broken broadly into two parts: the table emitter that 62 // emits the instruction decode tables discussed above during compilation, and 63 // the disassembler itself. The table emitter is documented in more detail in 64 // utils/TableGen/X86DisassemblerEmitter.h. 65 // 66 // X86Disassembler.cpp contains the code responsible for step 7, and for 67 // invoking the decoder to execute steps 1-6. 68 // X86DisassemblerDecoderCommon.h contains the definitions needed by both the 69 // table emitter and the disassembler. 70 // X86DisassemblerDecoder.h contains the public interface of the decoder, 71 // factored out into C for possible use by other projects. 72 // X86DisassemblerDecoder.c contains the source code of the decoder, which is 73 // responsible for steps 1-6. 74 // 75 //===----------------------------------------------------------------------===// 76 77 #include "MCTargetDesc/X86BaseInfo.h" 78 #include "MCTargetDesc/X86MCTargetDesc.h" 79 #include "X86DisassemblerDecoder.h" 80 #include "llvm/MC/MCContext.h" 81 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 82 #include "llvm/MC/MCExpr.h" 83 #include "llvm/MC/MCInst.h" 84 #include "llvm/MC/MCInstrInfo.h" 85 #include "llvm/MC/MCSubtargetInfo.h" 86 #include "llvm/Support/Debug.h" 87 #include "llvm/Support/TargetRegistry.h" 88 #include "llvm/Support/raw_ostream.h" 89 90 using namespace llvm; 91 using namespace llvm::X86Disassembler; 92 93 #define DEBUG_TYPE "x86-disassembler" 94 95 void llvm::X86Disassembler::Debug(const char *file, unsigned line, 96 const char *s) { 97 dbgs() << file << ":" << line << ": " << s; 98 } 99 100 StringRef llvm::X86Disassembler::GetInstrName(unsigned Opcode, 101 const void *mii) { 102 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii); 103 return MII->getName(Opcode); 104 } 105 106 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s)); 107 108 namespace llvm { 109 110 // Fill-ins to make the compiler happy. These constants are never actually 111 // assigned; they are just filler to make an automatically-generated switch 112 // statement work. 113 namespace X86 { 114 enum { 115 BX_SI = 500, 116 BX_DI = 501, 117 BP_SI = 502, 118 BP_DI = 503, 119 sib = 504, 120 sib64 = 505 121 }; 122 } 123 124 } 125 126 static bool translateInstruction(MCInst &target, 127 InternalInstruction &source, 128 const MCDisassembler *Dis); 129 130 namespace { 131 132 /// Generic disassembler for all X86 platforms. All each platform class should 133 /// have to do is subclass the constructor, and provide a different 134 /// disassemblerMode value. 135 class X86GenericDisassembler : public MCDisassembler { 136 std::unique_ptr<const MCInstrInfo> MII; 137 public: 138 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 139 std::unique_ptr<const MCInstrInfo> MII); 140 public: 141 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 142 ArrayRef<uint8_t> Bytes, uint64_t Address, 143 raw_ostream &vStream, 144 raw_ostream &cStream) const override; 145 146 private: 147 DisassemblerMode fMode; 148 }; 149 150 } 151 152 X86GenericDisassembler::X86GenericDisassembler( 153 const MCSubtargetInfo &STI, 154 MCContext &Ctx, 155 std::unique_ptr<const MCInstrInfo> MII) 156 : MCDisassembler(STI, Ctx), MII(std::move(MII)) { 157 const FeatureBitset &FB = STI.getFeatureBits(); 158 if (FB[X86::Mode16Bit]) { 159 fMode = MODE_16BIT; 160 return; 161 } else if (FB[X86::Mode32Bit]) { 162 fMode = MODE_32BIT; 163 return; 164 } else if (FB[X86::Mode64Bit]) { 165 fMode = MODE_64BIT; 166 return; 167 } 168 169 llvm_unreachable("Invalid CPU mode"); 170 } 171 172 namespace { 173 struct Region { 174 ArrayRef<uint8_t> Bytes; 175 uint64_t Base; 176 Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {} 177 }; 178 } // end anonymous namespace 179 180 /// A callback function that wraps the readByte method from Region. 181 /// 182 /// @param Arg - The generic callback parameter. In this case, this should 183 /// be a pointer to a Region. 184 /// @param Byte - A pointer to the byte to be read. 185 /// @param Address - The address to be read. 186 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) { 187 auto *R = static_cast<const Region *>(Arg); 188 ArrayRef<uint8_t> Bytes = R->Bytes; 189 unsigned Index = Address - R->Base; 190 if (Bytes.size() <= Index) 191 return -1; 192 *Byte = Bytes[Index]; 193 return 0; 194 } 195 196 /// logger - a callback function that wraps the operator<< method from 197 /// raw_ostream. 198 /// 199 /// @param arg - The generic callback parameter. This should be a pointe 200 /// to a raw_ostream. 201 /// @param log - A string to be logged. logger() adds a newline. 202 static void logger(void* arg, const char* log) { 203 if (!arg) 204 return; 205 206 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 207 vStream << log << "\n"; 208 } 209 210 // 211 // Public interface for the disassembler 212 // 213 214 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( 215 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, 216 raw_ostream &VStream, raw_ostream &CStream) const { 217 CommentStream = &CStream; 218 219 InternalInstruction InternalInstr; 220 221 dlog_t LoggerFn = logger; 222 if (&VStream == &nulls()) 223 LoggerFn = nullptr; // Disable logging completely if it's going to nulls(). 224 225 Region R(Bytes, Address); 226 227 int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R, 228 LoggerFn, (void *)&VStream, 229 (const void *)MII.get(), Address, fMode); 230 231 if (Ret) { 232 Size = InternalInstr.readerCursor - Address; 233 return Fail; 234 } else { 235 Size = InternalInstr.length; 236 bool Ret = translateInstruction(Instr, InternalInstr, this); 237 if (!Ret) { 238 unsigned Flags = X86::IP_NO_PREFIX; 239 if (InternalInstr.hasAdSize) 240 Flags |= X86::IP_HAS_AD_SIZE; 241 if (!InternalInstr.mandatoryPrefix) { 242 if (InternalInstr.hasOpSize) 243 Flags |= X86::IP_HAS_OP_SIZE; 244 if (InternalInstr.repeatPrefix == 0xf2) 245 Flags |= X86::IP_HAS_REPEAT_NE; 246 else if (InternalInstr.repeatPrefix == 0xf3 && 247 // It should not be 'pause' f3 90 248 InternalInstr.opcode != 0x90) 249 Flags |= X86::IP_HAS_REPEAT; 250 } 251 Instr.setFlags(Flags); 252 } 253 return (!Ret) ? Success : Fail; 254 } 255 } 256 257 // 258 // Private code that translates from struct InternalInstructions to MCInsts. 259 // 260 261 /// translateRegister - Translates an internal register to the appropriate LLVM 262 /// register, and appends it as an operand to an MCInst. 263 /// 264 /// @param mcInst - The MCInst to append to. 265 /// @param reg - The Reg to append. 266 static void translateRegister(MCInst &mcInst, Reg reg) { 267 #define ENTRY(x) X86::x, 268 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS}; 269 #undef ENTRY 270 271 MCPhysReg llvmRegnum = llvmRegnums[reg]; 272 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); 273 } 274 275 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 276 /// immediate Value in the MCInst. 277 /// 278 /// @param Value - The immediate Value, has had any PC adjustment made by 279 /// the caller. 280 /// @param isBranch - If the instruction is a branch instruction 281 /// @param Address - The starting address of the instruction 282 /// @param Offset - The byte offset to this immediate in the instruction 283 /// @param Width - The byte width of this immediate in the instruction 284 /// 285 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was 286 /// called then that function is called to get any symbolic information for the 287 /// immediate in the instruction using the Address, Offset and Width. If that 288 /// returns non-zero then the symbolic information it returns is used to create 289 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo() 290 /// returns zero and isBranch is true then a symbol look up for immediate Value 291 /// is done and if a symbol is found an MCExpr is created with that, else 292 /// an MCExpr with the immediate Value is created. This function returns true 293 /// if it adds an operand to the MCInst and false otherwise. 294 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 295 uint64_t Address, uint64_t Offset, 296 uint64_t Width, MCInst &MI, 297 const MCDisassembler *Dis) { 298 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 299 Offset, Width); 300 } 301 302 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 303 /// referenced by a load instruction with the base register that is the rip. 304 /// These can often be addresses in a literal pool. The Address of the 305 /// instruction and its immediate Value are used to determine the address 306 /// being referenced in the literal pool entry. The SymbolLookUp call back will 307 /// return a pointer to a literal 'C' string if the referenced address is an 308 /// address into a section with 'C' string literals. 309 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, 310 const void *Decoder) { 311 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 312 Dis->tryAddingPcLoadReferenceComment(Value, Address); 313 } 314 315 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 316 0, // SEG_OVERRIDE_NONE 317 X86::CS, 318 X86::SS, 319 X86::DS, 320 X86::ES, 321 X86::FS, 322 X86::GS 323 }; 324 325 /// translateSrcIndex - Appends a source index operand to an MCInst. 326 /// 327 /// @param mcInst - The MCInst to append to. 328 /// @param insn - The internal instruction. 329 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { 330 unsigned baseRegNo; 331 332 if (insn.mode == MODE_64BIT) 333 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI; 334 else if (insn.mode == MODE_32BIT) 335 baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI; 336 else { 337 assert(insn.mode == MODE_16BIT); 338 baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI; 339 } 340 MCOperand baseReg = MCOperand::createReg(baseRegNo); 341 mcInst.addOperand(baseReg); 342 343 MCOperand segmentReg; 344 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 345 mcInst.addOperand(segmentReg); 346 return false; 347 } 348 349 /// translateDstIndex - Appends a destination index operand to an MCInst. 350 /// 351 /// @param mcInst - The MCInst to append to. 352 /// @param insn - The internal instruction. 353 354 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { 355 unsigned baseRegNo; 356 357 if (insn.mode == MODE_64BIT) 358 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI; 359 else if (insn.mode == MODE_32BIT) 360 baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI; 361 else { 362 assert(insn.mode == MODE_16BIT); 363 baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI; 364 } 365 MCOperand baseReg = MCOperand::createReg(baseRegNo); 366 mcInst.addOperand(baseReg); 367 return false; 368 } 369 370 /// translateImmediate - Appends an immediate operand to an MCInst. 371 /// 372 /// @param mcInst - The MCInst to append to. 373 /// @param immediate - The immediate value to append. 374 /// @param operand - The operand, as stored in the descriptor table. 375 /// @param insn - The internal instruction. 376 static void translateImmediate(MCInst &mcInst, uint64_t immediate, 377 const OperandSpecifier &operand, 378 InternalInstruction &insn, 379 const MCDisassembler *Dis) { 380 // Sign-extend the immediate if necessary. 381 382 OperandType type = (OperandType)operand.type; 383 384 bool isBranch = false; 385 uint64_t pcrel = 0; 386 if (type == TYPE_REL) { 387 isBranch = true; 388 pcrel = insn.startLocation + 389 insn.immediateOffset + insn.immediateSize; 390 switch (operand.encoding) { 391 default: 392 break; 393 case ENCODING_Iv: 394 switch (insn.displacementSize) { 395 default: 396 break; 397 case 1: 398 if(immediate & 0x80) 399 immediate |= ~(0xffull); 400 break; 401 case 2: 402 if(immediate & 0x8000) 403 immediate |= ~(0xffffull); 404 break; 405 case 4: 406 if(immediate & 0x80000000) 407 immediate |= ~(0xffffffffull); 408 break; 409 case 8: 410 break; 411 } 412 break; 413 case ENCODING_IB: 414 if(immediate & 0x80) 415 immediate |= ~(0xffull); 416 break; 417 case ENCODING_IW: 418 if(immediate & 0x8000) 419 immediate |= ~(0xffffull); 420 break; 421 case ENCODING_ID: 422 if(immediate & 0x80000000) 423 immediate |= ~(0xffffffffull); 424 break; 425 } 426 } 427 // By default sign-extend all X86 immediates based on their encoding. 428 else if (type == TYPE_IMM) { 429 switch (operand.encoding) { 430 default: 431 break; 432 case ENCODING_IB: 433 if(immediate & 0x80) 434 immediate |= ~(0xffull); 435 break; 436 case ENCODING_IW: 437 if(immediate & 0x8000) 438 immediate |= ~(0xffffull); 439 break; 440 case ENCODING_ID: 441 if(immediate & 0x80000000) 442 immediate |= ~(0xffffffffull); 443 break; 444 case ENCODING_IO: 445 break; 446 } 447 } else if (type == TYPE_IMM3) { 448 // Check for immediates that printSSECC can't handle. 449 if (immediate >= 8) { 450 unsigned NewOpc; 451 switch (mcInst.getOpcode()) { 452 default: llvm_unreachable("unexpected opcode"); 453 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; 454 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; 455 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; 456 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; 457 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; 458 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; 459 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; 460 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; 461 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; 462 case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break; 463 case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break; 464 case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break; 465 case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break; 466 case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break; 467 case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break; 468 case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break; 469 case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break; 470 case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break; 471 case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break; 472 case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break; 473 case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break; 474 case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break; 475 case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break; 476 case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break; 477 } 478 // Switch opcode to the one that doesn't get special printing. 479 mcInst.setOpcode(NewOpc); 480 } 481 } else if (type == TYPE_IMM5) { 482 // Check for immediates that printAVXCC can't handle. 483 if (immediate >= 32) { 484 unsigned NewOpc; 485 switch (mcInst.getOpcode()) { 486 default: llvm_unreachable("unexpected opcode"); 487 case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break; 488 case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break; 489 case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break; 490 case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break; 491 case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break; 492 case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break; 493 case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break; 494 case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break; 495 case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break; 496 case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break; 497 case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break; 498 case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break; 499 case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break; 500 case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break; 501 case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break; 502 case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break; 503 case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break; 504 case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break; 505 case X86::VCMPPDZ128rmi: NewOpc = X86::VCMPPDZ128rmi_alt; break; 506 case X86::VCMPPDZ128rri: NewOpc = X86::VCMPPDZ128rri_alt; break; 507 case X86::VCMPPSZ128rmi: NewOpc = X86::VCMPPSZ128rmi_alt; break; 508 case X86::VCMPPSZ128rri: NewOpc = X86::VCMPPSZ128rri_alt; break; 509 case X86::VCMPPDZ256rmi: NewOpc = X86::VCMPPDZ256rmi_alt; break; 510 case X86::VCMPPDZ256rri: NewOpc = X86::VCMPPDZ256rri_alt; break; 511 case X86::VCMPPSZ256rmi: NewOpc = X86::VCMPPSZ256rmi_alt; break; 512 case X86::VCMPPSZ256rri: NewOpc = X86::VCMPPSZ256rri_alt; break; 513 case X86::VCMPSDZrm_Int: NewOpc = X86::VCMPSDZrmi_alt; break; 514 case X86::VCMPSDZrr_Int: NewOpc = X86::VCMPSDZrri_alt; break; 515 case X86::VCMPSDZrrb_Int: NewOpc = X86::VCMPSDZrrb_alt; break; 516 case X86::VCMPSSZrm_Int: NewOpc = X86::VCMPSSZrmi_alt; break; 517 case X86::VCMPSSZrr_Int: NewOpc = X86::VCMPSSZrri_alt; break; 518 case X86::VCMPSSZrrb_Int: NewOpc = X86::VCMPSSZrrb_alt; break; 519 } 520 // Switch opcode to the one that doesn't get special printing. 521 mcInst.setOpcode(NewOpc); 522 } 523 } else if (type == TYPE_AVX512ICC) { 524 if (immediate >= 8 || ((immediate & 0x3) == 3)) { 525 unsigned NewOpc; 526 switch (mcInst.getOpcode()) { 527 default: llvm_unreachable("unexpected opcode"); 528 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break; 529 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break; 530 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break; 531 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break; 532 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break; 533 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break; 534 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break; 535 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break; 536 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break; 537 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break; 538 case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break; 539 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break; 540 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break; 541 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break; 542 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break; 543 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break; 544 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break; 545 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break; 546 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break; 547 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break; 548 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break; 549 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break; 550 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break; 551 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break; 552 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break; 553 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break; 554 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break; 555 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break; 556 case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break; 557 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break; 558 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break; 559 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break; 560 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break; 561 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break; 562 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break; 563 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break; 564 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break; 565 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break; 566 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break; 567 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break; 568 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break; 569 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break; 570 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break; 571 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break; 572 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break; 573 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break; 574 case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break; 575 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break; 576 case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break; 577 case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break; 578 case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break; 579 case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break; 580 case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break; 581 case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break; 582 case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break; 583 case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break; 584 case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break; 585 case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break; 586 case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break; 587 case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break; 588 case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break; 589 case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break; 590 case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break; 591 case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break; 592 case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break; 593 case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break; 594 case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break; 595 case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break; 596 case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break; 597 case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break; 598 case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break; 599 case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break; 600 case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break; 601 case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break; 602 case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break; 603 case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break; 604 case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break; 605 case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break; 606 case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break; 607 case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break; 608 case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break; 609 case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break; 610 case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break; 611 case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break; 612 case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break; 613 case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break; 614 case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break; 615 case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break; 616 case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break; 617 case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break; 618 case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break; 619 case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break; 620 case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break; 621 case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break; 622 case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break; 623 case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break; 624 case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break; 625 case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break; 626 case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break; 627 case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break; 628 case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break; 629 case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break; 630 case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break; 631 case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break; 632 case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break; 633 case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break; 634 case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break; 635 case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break; 636 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break; 637 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break; 638 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break; 639 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break; 640 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break; 641 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break; 642 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break; 643 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break; 644 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break; 645 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break; 646 case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break; 647 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break; 648 } 649 // Switch opcode to the one that doesn't get special printing. 650 mcInst.setOpcode(NewOpc); 651 } 652 } 653 654 switch (type) { 655 case TYPE_XMM: 656 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); 657 return; 658 case TYPE_YMM: 659 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); 660 return; 661 case TYPE_ZMM: 662 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); 663 return; 664 case TYPE_BNDR: 665 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); 666 default: 667 // operand is 64 bits wide. Do nothing. 668 break; 669 } 670 671 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, 672 insn.immediateOffset, insn.immediateSize, 673 mcInst, Dis)) 674 mcInst.addOperand(MCOperand::createImm(immediate)); 675 676 if (type == TYPE_MOFFS) { 677 MCOperand segmentReg; 678 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 679 mcInst.addOperand(segmentReg); 680 } 681 } 682 683 /// translateRMRegister - Translates a register stored in the R/M field of the 684 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 685 /// @param mcInst - The MCInst to append to. 686 /// @param insn - The internal instruction to extract the R/M field 687 /// from. 688 /// @return - 0 on success; -1 otherwise 689 static bool translateRMRegister(MCInst &mcInst, 690 InternalInstruction &insn) { 691 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 692 debug("A R/M register operand may not have a SIB byte"); 693 return true; 694 } 695 696 switch (insn.eaBase) { 697 default: 698 debug("Unexpected EA base register"); 699 return true; 700 case EA_BASE_NONE: 701 debug("EA_BASE_NONE for ModR/M base"); 702 return true; 703 #define ENTRY(x) case EA_BASE_##x: 704 ALL_EA_BASES 705 #undef ENTRY 706 debug("A R/M register operand may not have a base; " 707 "the operand must be a register."); 708 return true; 709 #define ENTRY(x) \ 710 case EA_REG_##x: \ 711 mcInst.addOperand(MCOperand::createReg(X86::x)); break; 712 ALL_REGS 713 #undef ENTRY 714 } 715 716 return false; 717 } 718 719 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 720 /// fields of an internal instruction (and possibly its SIB byte) to a memory 721 /// operand in LLVM's format, and appends it to an MCInst. 722 /// 723 /// @param mcInst - The MCInst to append to. 724 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 725 /// from. 726 /// @return - 0 on success; nonzero otherwise 727 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, 728 const MCDisassembler *Dis) { 729 // Addresses in an MCInst are represented as five operands: 730 // 1. basereg (register) The R/M base, or (if there is a SIB) the 731 // SIB base 732 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 733 // scale amount 734 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 735 // the index (which is multiplied by the 736 // scale amount) 737 // 4. displacement (immediate) 0, or the displacement if there is one 738 // 5. segmentreg (register) x86_registerNONE for now, but could be set 739 // if we have segment overrides 740 741 MCOperand baseReg; 742 MCOperand scaleAmount; 743 MCOperand indexReg; 744 MCOperand displacement; 745 MCOperand segmentReg; 746 uint64_t pcrel = 0; 747 748 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 749 if (insn.sibBase != SIB_BASE_NONE) { 750 switch (insn.sibBase) { 751 default: 752 debug("Unexpected sibBase"); 753 return true; 754 #define ENTRY(x) \ 755 case SIB_BASE_##x: \ 756 baseReg = MCOperand::createReg(X86::x); break; 757 ALL_SIB_BASES 758 #undef ENTRY 759 } 760 } else { 761 baseReg = MCOperand::createReg(0); 762 } 763 764 if (insn.sibIndex != SIB_INDEX_NONE) { 765 switch (insn.sibIndex) { 766 default: 767 debug("Unexpected sibIndex"); 768 return true; 769 #define ENTRY(x) \ 770 case SIB_INDEX_##x: \ 771 indexReg = MCOperand::createReg(X86::x); break; 772 EA_BASES_32BIT 773 EA_BASES_64BIT 774 REGS_XMM 775 REGS_YMM 776 REGS_ZMM 777 #undef ENTRY 778 } 779 } else { 780 indexReg = MCOperand::createReg(0); 781 } 782 783 scaleAmount = MCOperand::createImm(insn.sibScale); 784 } else { 785 switch (insn.eaBase) { 786 case EA_BASE_NONE: 787 if (insn.eaDisplacement == EA_DISP_NONE) { 788 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 789 return true; 790 } 791 if (insn.mode == MODE_64BIT){ 792 pcrel = insn.startLocation + 793 insn.displacementOffset + insn.displacementSize; 794 tryAddingPcLoadReferenceComment(insn.startLocation + 795 insn.displacementOffset, 796 insn.displacement + pcrel, Dis); 797 baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6 798 } 799 else 800 baseReg = MCOperand::createReg(0); 801 802 indexReg = MCOperand::createReg(0); 803 break; 804 case EA_BASE_BX_SI: 805 baseReg = MCOperand::createReg(X86::BX); 806 indexReg = MCOperand::createReg(X86::SI); 807 break; 808 case EA_BASE_BX_DI: 809 baseReg = MCOperand::createReg(X86::BX); 810 indexReg = MCOperand::createReg(X86::DI); 811 break; 812 case EA_BASE_BP_SI: 813 baseReg = MCOperand::createReg(X86::BP); 814 indexReg = MCOperand::createReg(X86::SI); 815 break; 816 case EA_BASE_BP_DI: 817 baseReg = MCOperand::createReg(X86::BP); 818 indexReg = MCOperand::createReg(X86::DI); 819 break; 820 default: 821 indexReg = MCOperand::createReg(0); 822 switch (insn.eaBase) { 823 default: 824 debug("Unexpected eaBase"); 825 return true; 826 // Here, we will use the fill-ins defined above. However, 827 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 828 // sib and sib64 were handled in the top-level if, so they're only 829 // placeholders to keep the compiler happy. 830 #define ENTRY(x) \ 831 case EA_BASE_##x: \ 832 baseReg = MCOperand::createReg(X86::x); break; 833 ALL_EA_BASES 834 #undef ENTRY 835 #define ENTRY(x) case EA_REG_##x: 836 ALL_REGS 837 #undef ENTRY 838 debug("A R/M memory operand may not be a register; " 839 "the base field must be a base."); 840 return true; 841 } 842 } 843 844 scaleAmount = MCOperand::createImm(1); 845 } 846 847 displacement = MCOperand::createImm(insn.displacement); 848 849 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 850 851 mcInst.addOperand(baseReg); 852 mcInst.addOperand(scaleAmount); 853 mcInst.addOperand(indexReg); 854 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false, 855 insn.startLocation, insn.displacementOffset, 856 insn.displacementSize, mcInst, Dis)) 857 mcInst.addOperand(displacement); 858 mcInst.addOperand(segmentReg); 859 return false; 860 } 861 862 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 863 /// byte of an instruction to LLVM form, and appends it to an MCInst. 864 /// 865 /// @param mcInst - The MCInst to append to. 866 /// @param operand - The operand, as stored in the descriptor table. 867 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 868 /// from. 869 /// @return - 0 on success; nonzero otherwise 870 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, 871 InternalInstruction &insn, const MCDisassembler *Dis) { 872 switch (operand.type) { 873 default: 874 debug("Unexpected type for a R/M operand"); 875 return true; 876 case TYPE_R8: 877 case TYPE_R16: 878 case TYPE_R32: 879 case TYPE_R64: 880 case TYPE_Rv: 881 case TYPE_MM64: 882 case TYPE_XMM: 883 case TYPE_YMM: 884 case TYPE_ZMM: 885 case TYPE_VK: 886 case TYPE_DEBUGREG: 887 case TYPE_CONTROLREG: 888 case TYPE_BNDR: 889 return translateRMRegister(mcInst, insn); 890 case TYPE_M: 891 case TYPE_MVSIBX: 892 case TYPE_MVSIBY: 893 case TYPE_MVSIBZ: 894 return translateRMMemory(mcInst, insn, Dis); 895 } 896 } 897 898 /// translateFPRegister - Translates a stack position on the FPU stack to its 899 /// LLVM form, and appends it to an MCInst. 900 /// 901 /// @param mcInst - The MCInst to append to. 902 /// @param stackPos - The stack position to translate. 903 static void translateFPRegister(MCInst &mcInst, 904 uint8_t stackPos) { 905 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos)); 906 } 907 908 /// translateMaskRegister - Translates a 3-bit mask register number to 909 /// LLVM form, and appends it to an MCInst. 910 /// 911 /// @param mcInst - The MCInst to append to. 912 /// @param maskRegNum - Number of mask register from 0 to 7. 913 /// @return - false on success; true otherwise. 914 static bool translateMaskRegister(MCInst &mcInst, 915 uint8_t maskRegNum) { 916 if (maskRegNum >= 8) { 917 debug("Invalid mask register number"); 918 return true; 919 } 920 921 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum)); 922 return false; 923 } 924 925 /// translateOperand - Translates an operand stored in an internal instruction 926 /// to LLVM's format and appends it to an MCInst. 927 /// 928 /// @param mcInst - The MCInst to append to. 929 /// @param operand - The operand, as stored in the descriptor table. 930 /// @param insn - The internal instruction. 931 /// @return - false on success; true otherwise. 932 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, 933 InternalInstruction &insn, 934 const MCDisassembler *Dis) { 935 switch (operand.encoding) { 936 default: 937 debug("Unhandled operand encoding during translation"); 938 return true; 939 case ENCODING_REG: 940 translateRegister(mcInst, insn.reg); 941 return false; 942 case ENCODING_WRITEMASK: 943 return translateMaskRegister(mcInst, insn.writemask); 944 CASE_ENCODING_RM: 945 CASE_ENCODING_VSIB: 946 return translateRM(mcInst, operand, insn, Dis); 947 case ENCODING_IB: 948 case ENCODING_IW: 949 case ENCODING_ID: 950 case ENCODING_IO: 951 case ENCODING_Iv: 952 case ENCODING_Ia: 953 translateImmediate(mcInst, 954 insn.immediates[insn.numImmediatesTranslated++], 955 operand, 956 insn, 957 Dis); 958 return false; 959 case ENCODING_IRC: 960 mcInst.addOperand(MCOperand::createImm(insn.RC)); 961 return false; 962 case ENCODING_SI: 963 return translateSrcIndex(mcInst, insn); 964 case ENCODING_DI: 965 return translateDstIndex(mcInst, insn); 966 case ENCODING_RB: 967 case ENCODING_RW: 968 case ENCODING_RD: 969 case ENCODING_RO: 970 case ENCODING_Rv: 971 translateRegister(mcInst, insn.opcodeRegister); 972 return false; 973 case ENCODING_FP: 974 translateFPRegister(mcInst, insn.modRM & 7); 975 return false; 976 case ENCODING_VVVV: 977 translateRegister(mcInst, insn.vvvv); 978 return false; 979 case ENCODING_DUP: 980 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0], 981 insn, Dis); 982 } 983 } 984 985 /// translateInstruction - Translates an internal instruction and all its 986 /// operands to an MCInst. 987 /// 988 /// @param mcInst - The MCInst to populate with the instruction's data. 989 /// @param insn - The internal instruction. 990 /// @return - false on success; true otherwise. 991 static bool translateInstruction(MCInst &mcInst, 992 InternalInstruction &insn, 993 const MCDisassembler *Dis) { 994 if (!insn.spec) { 995 debug("Instruction has no specification"); 996 return true; 997 } 998 999 mcInst.clear(); 1000 mcInst.setOpcode(insn.instructionID); 1001 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 1002 // prefix bytes should be disassembled as xrelease and xacquire then set the 1003 // opcode to those instead of the rep and repne opcodes. 1004 if (insn.xAcquireRelease) { 1005 if(mcInst.getOpcode() == X86::REP_PREFIX) 1006 mcInst.setOpcode(X86::XRELEASE_PREFIX); 1007 else if(mcInst.getOpcode() == X86::REPNE_PREFIX) 1008 mcInst.setOpcode(X86::XACQUIRE_PREFIX); 1009 } 1010 1011 insn.numImmediatesTranslated = 0; 1012 1013 for (const auto &Op : insn.operands) { 1014 if (Op.encoding != ENCODING_NONE) { 1015 if (translateOperand(mcInst, Op, insn, Dis)) { 1016 return true; 1017 } 1018 } 1019 } 1020 1021 return false; 1022 } 1023 1024 static MCDisassembler *createX86Disassembler(const Target &T, 1025 const MCSubtargetInfo &STI, 1026 MCContext &Ctx) { 1027 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); 1028 return new X86GenericDisassembler(STI, Ctx, std::move(MII)); 1029 } 1030 1031 extern "C" void LLVMInitializeX86Disassembler() { 1032 // Register the disassembler. 1033 TargetRegistry::RegisterMCDisassembler(getTheX86_32Target(), 1034 createX86Disassembler); 1035 TargetRegistry::RegisterMCDisassembler(getTheX86_64Target(), 1036 createX86Disassembler); 1037 } 1038