1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler. 11 // It contains code to translate the data produced by the decoder into 12 // MCInsts. 13 // Documentation for the disassembler can be found in X86Disassembler.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86Disassembler.h" 18 #include "X86DisassemblerDecoder.h" 19 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Target/TargetRegistry.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 #include "X86GenRegisterNames.inc" 29 30 using namespace llvm; 31 using namespace llvm::X86Disassembler; 32 33 namespace llvm { 34 35 // Fill-ins to make the compiler happy. These constants are never actually 36 // assigned; they are just filler to make an automatically-generated switch 37 // statement work. 38 namespace X86 { 39 enum { 40 BX_SI = 500, 41 BX_DI = 501, 42 BP_SI = 502, 43 BP_DI = 503, 44 sib = 504, 45 sib64 = 505 46 }; 47 } 48 49 extern Target TheX86_32Target, TheX86_64Target; 50 51 } 52 53 static void translateInstruction(MCInst &target, 54 InternalInstruction &source); 55 56 X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) : 57 MCDisassembler(), 58 fMode(mode) { 59 } 60 61 X86GenericDisassembler::~X86GenericDisassembler() { 62 } 63 64 /// regionReader - a callback function that wraps the readByte method from 65 /// MemoryObject. 66 /// 67 /// @param arg - The generic callback parameter. In this case, this should 68 /// be a pointer to a MemoryObject. 69 /// @param byte - A pointer to the byte to be read. 70 /// @param address - The address to be read. 71 static int regionReader(void* arg, uint8_t* byte, uint64_t address) { 72 MemoryObject* region = static_cast<MemoryObject*>(arg); 73 return region->readByte(address, byte); 74 } 75 76 /// logger - a callback function that wraps the operator<< method from 77 /// raw_ostream. 78 /// 79 /// @param arg - The generic callback parameter. This should be a pointe 80 /// to a raw_ostream. 81 /// @param log - A string to be logged. logger() adds a newline. 82 static void logger(void* arg, const char* log) { 83 if (!arg) 84 return; 85 86 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg)); 87 vStream << log << "\n"; 88 } 89 90 // 91 // Public interface for the disassembler 92 // 93 94 bool X86GenericDisassembler::getInstruction(MCInst &instr, 95 uint64_t &size, 96 const MemoryObject ®ion, 97 uint64_t address, 98 raw_ostream &vStream) const { 99 InternalInstruction internalInstr; 100 101 int ret = decodeInstruction(&internalInstr, 102 regionReader, 103 (void*)®ion, 104 logger, 105 (void*)&vStream, 106 address, 107 fMode); 108 109 if(ret) { 110 size = internalInstr.readerCursor - address; 111 return false; 112 } 113 else { 114 size = internalInstr.length; 115 translateInstruction(instr, internalInstr); 116 return true; 117 } 118 } 119 120 // 121 // Private code that translates from struct InternalInstructions to MCInsts. 122 // 123 124 /// translateRegister - Translates an internal register to the appropriate LLVM 125 /// register, and appends it as an operand to an MCInst. 126 /// 127 /// @param mcInst - The MCInst to append to. 128 /// @param reg - The Reg to append. 129 static void translateRegister(MCInst &mcInst, Reg reg) { 130 #define ENTRY(x) X86::x, 131 uint8_t llvmRegnums[] = { 132 ALL_REGS 133 0 134 }; 135 #undef ENTRY 136 137 uint8_t llvmRegnum = llvmRegnums[reg]; 138 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 139 } 140 141 /// translateImmediate - Appends an immediate operand to an MCInst. 142 /// 143 /// @param mcInst - The MCInst to append to. 144 /// @param immediate - The immediate value to append. 145 static void translateImmediate(MCInst &mcInst, uint64_t immediate) { 146 mcInst.addOperand(MCOperand::CreateImm(immediate)); 147 } 148 149 /// translateRMRegister - Translates a register stored in the R/M field of the 150 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. 151 /// @param mcInst - The MCInst to append to. 152 /// @param insn - The internal instruction to extract the R/M field 153 /// from. 154 static void translateRMRegister(MCInst &mcInst, 155 InternalInstruction &insn) { 156 assert(insn.eaBase != EA_BASE_sib && insn.eaBase != EA_BASE_sib64 && 157 "A R/M register operand may not have a SIB byte"); 158 159 switch (insn.eaBase) { 160 case EA_BASE_NONE: 161 llvm_unreachable("EA_BASE_NONE for ModR/M base"); 162 break; 163 #define ENTRY(x) case EA_BASE_##x: 164 ALL_EA_BASES 165 #undef ENTRY 166 llvm_unreachable("A R/M register operand may not have a base; " 167 "the operand must be a register."); 168 break; 169 #define ENTRY(x) \ 170 case EA_REG_##x: \ 171 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 172 ALL_REGS 173 #undef ENTRY 174 default: 175 llvm_unreachable("Unexpected EA base register"); 176 } 177 } 178 179 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M 180 /// fields of an internal instruction (and possibly its SIB byte) to a memory 181 /// operand in LLVM's format, and appends it to an MCInst. 182 /// 183 /// @param mcInst - The MCInst to append to. 184 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 185 /// from. 186 /// @param sr - Whether or not to emit the segment register. The 187 /// LEA instruction does not expect a segment-register 188 /// operand. 189 static void translateRMMemory(MCInst &mcInst, 190 InternalInstruction &insn, 191 bool sr) { 192 // Addresses in an MCInst are represented as five operands: 193 // 1. basereg (register) The R/M base, or (if there is a SIB) the 194 // SIB base 195 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified 196 // scale amount 197 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) 198 // the index (which is multiplied by the 199 // scale amount) 200 // 4. displacement (immediate) 0, or the displacement if there is one 201 // 5. segmentreg (register) x86_registerNONE for now, but could be set 202 // if we have segment overrides 203 204 MCOperand baseReg; 205 MCOperand scaleAmount; 206 MCOperand indexReg; 207 MCOperand displacement; 208 MCOperand segmentReg; 209 210 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { 211 if (insn.sibBase != SIB_BASE_NONE) { 212 switch (insn.sibBase) { 213 default: 214 llvm_unreachable("Unexpected sibBase"); 215 #define ENTRY(x) \ 216 case SIB_BASE_##x: \ 217 baseReg = MCOperand::CreateReg(X86::x); break; 218 ALL_SIB_BASES 219 #undef ENTRY 220 } 221 } else { 222 baseReg = MCOperand::CreateReg(0); 223 } 224 225 if (insn.sibIndex != SIB_INDEX_NONE) { 226 switch (insn.sibIndex) { 227 default: 228 llvm_unreachable("Unexpected sibIndex"); 229 #define ENTRY(x) \ 230 case SIB_INDEX_##x: \ 231 indexReg = MCOperand::CreateReg(X86::x); break; 232 EA_BASES_32BIT 233 EA_BASES_64BIT 234 #undef ENTRY 235 } 236 } else { 237 indexReg = MCOperand::CreateReg(0); 238 } 239 240 scaleAmount = MCOperand::CreateImm(insn.sibScale); 241 } else { 242 switch (insn.eaBase) { 243 case EA_BASE_NONE: 244 assert(insn.eaDisplacement != EA_DISP_NONE && 245 "EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); 246 247 if (insn.mode == MODE_64BIT) 248 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6 249 else 250 baseReg = MCOperand::CreateReg(0); 251 252 indexReg = MCOperand::CreateReg(0); 253 break; 254 case EA_BASE_BX_SI: 255 baseReg = MCOperand::CreateReg(X86::BX); 256 indexReg = MCOperand::CreateReg(X86::SI); 257 break; 258 case EA_BASE_BX_DI: 259 baseReg = MCOperand::CreateReg(X86::BX); 260 indexReg = MCOperand::CreateReg(X86::DI); 261 break; 262 case EA_BASE_BP_SI: 263 baseReg = MCOperand::CreateReg(X86::BP); 264 indexReg = MCOperand::CreateReg(X86::SI); 265 break; 266 case EA_BASE_BP_DI: 267 baseReg = MCOperand::CreateReg(X86::BP); 268 indexReg = MCOperand::CreateReg(X86::DI); 269 break; 270 default: 271 indexReg = MCOperand::CreateReg(0); 272 switch (insn.eaBase) { 273 default: 274 llvm_unreachable("Unexpected eaBase"); 275 break; 276 // Here, we will use the fill-ins defined above. However, 277 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and 278 // sib and sib64 were handled in the top-level if, so they're only 279 // placeholders to keep the compiler happy. 280 #define ENTRY(x) \ 281 case EA_BASE_##x: \ 282 baseReg = MCOperand::CreateReg(X86::x); break; 283 ALL_EA_BASES 284 #undef ENTRY 285 #define ENTRY(x) case EA_REG_##x: 286 ALL_REGS 287 #undef ENTRY 288 llvm_unreachable("A R/M memory operand may not be a register; " 289 "the base field must be a base."); 290 break; 291 } 292 } 293 294 scaleAmount = MCOperand::CreateImm(1); 295 } 296 297 displacement = MCOperand::CreateImm(insn.displacement); 298 299 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 300 0, // SEG_OVERRIDE_NONE 301 X86::CS, 302 X86::SS, 303 X86::DS, 304 X86::ES, 305 X86::FS, 306 X86::GS 307 }; 308 309 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); 310 311 mcInst.addOperand(baseReg); 312 mcInst.addOperand(scaleAmount); 313 mcInst.addOperand(indexReg); 314 mcInst.addOperand(displacement); 315 316 if (sr) 317 mcInst.addOperand(segmentReg); 318 } 319 320 /// translateRM - Translates an operand stored in the R/M (and possibly SIB) 321 /// byte of an instruction to LLVM form, and appends it to an MCInst. 322 /// 323 /// @param mcInst - The MCInst to append to. 324 /// @param operand - The operand, as stored in the descriptor table. 325 /// @param insn - The instruction to extract Mod, R/M, and SIB fields 326 /// from. 327 static void translateRM(MCInst &mcInst, 328 OperandSpecifier &operand, 329 InternalInstruction &insn) { 330 switch (operand.type) { 331 default: 332 llvm_unreachable("Unexpected type for a R/M operand"); 333 case TYPE_R8: 334 case TYPE_R16: 335 case TYPE_R32: 336 case TYPE_R64: 337 case TYPE_Rv: 338 case TYPE_MM: 339 case TYPE_MM32: 340 case TYPE_MM64: 341 case TYPE_XMM: 342 case TYPE_XMM32: 343 case TYPE_XMM64: 344 case TYPE_XMM128: 345 case TYPE_DEBUGREG: 346 case TYPE_CR32: 347 case TYPE_CR64: 348 translateRMRegister(mcInst, insn); 349 break; 350 case TYPE_M: 351 case TYPE_M8: 352 case TYPE_M16: 353 case TYPE_M32: 354 case TYPE_M64: 355 case TYPE_M128: 356 case TYPE_M512: 357 case TYPE_Mv: 358 case TYPE_M32FP: 359 case TYPE_M64FP: 360 case TYPE_M80FP: 361 case TYPE_M16INT: 362 case TYPE_M32INT: 363 case TYPE_M64INT: 364 case TYPE_M1616: 365 case TYPE_M1632: 366 case TYPE_M1664: 367 translateRMMemory(mcInst, insn, true); 368 break; 369 case TYPE_LEA: 370 translateRMMemory(mcInst, insn, false); 371 break; 372 } 373 } 374 375 /// translateFPRegister - Translates a stack position on the FPU stack to its 376 /// LLVM form, and appends it to an MCInst. 377 /// 378 /// @param mcInst - The MCInst to append to. 379 /// @param stackPos - The stack position to translate. 380 static void translateFPRegister(MCInst &mcInst, 381 uint8_t stackPos) { 382 assert(stackPos < 8 && "Invalid FP stack position"); 383 384 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos)); 385 } 386 387 /// translateOperand - Translates an operand stored in an internal instruction 388 /// to LLVM's format and appends it to an MCInst. 389 /// 390 /// @param mcInst - The MCInst to append to. 391 /// @param operand - The operand, as stored in the descriptor table. 392 /// @param insn - The internal instruction. 393 static void translateOperand(MCInst &mcInst, 394 OperandSpecifier &operand, 395 InternalInstruction &insn) { 396 switch (operand.encoding) { 397 default: 398 llvm_unreachable("Unhandled operand encoding during translation"); 399 case ENCODING_REG: 400 translateRegister(mcInst, insn.reg); 401 break; 402 case ENCODING_RM: 403 translateRM(mcInst, operand, insn); 404 break; 405 case ENCODING_CB: 406 case ENCODING_CW: 407 case ENCODING_CD: 408 case ENCODING_CP: 409 case ENCODING_CO: 410 case ENCODING_CT: 411 llvm_unreachable("Translation of code offsets isn't supported."); 412 case ENCODING_IB: 413 case ENCODING_IW: 414 case ENCODING_ID: 415 case ENCODING_IO: 416 case ENCODING_Iv: 417 case ENCODING_Ia: 418 translateImmediate(mcInst, 419 insn.immediates[insn.numImmediatesTranslated++]); 420 break; 421 case ENCODING_RB: 422 case ENCODING_RW: 423 case ENCODING_RD: 424 case ENCODING_RO: 425 translateRegister(mcInst, insn.opcodeRegister); 426 break; 427 case ENCODING_I: 428 translateFPRegister(mcInst, insn.opcodeModifier); 429 break; 430 case ENCODING_Rv: 431 translateRegister(mcInst, insn.opcodeRegister); 432 break; 433 case ENCODING_DUP: 434 translateOperand(mcInst, 435 insn.spec->operands[operand.type - TYPE_DUP0], 436 insn); 437 break; 438 } 439 } 440 441 /// translateInstruction - Translates an internal instruction and all its 442 /// operands to an MCInst. 443 /// 444 /// @param mcInst - The MCInst to populate with the instruction's data. 445 /// @param insn - The internal instruction. 446 static void translateInstruction(MCInst &mcInst, 447 InternalInstruction &insn) { 448 assert(insn.spec); 449 450 mcInst.setOpcode(insn.instructionID); 451 452 int index; 453 454 insn.numImmediatesTranslated = 0; 455 456 for (index = 0; index < X86_MAX_OPERANDS; ++index) { 457 if (insn.spec->operands[index].encoding != ENCODING_NONE) 458 translateOperand(mcInst, insn.spec->operands[index], insn); 459 } 460 } 461 462 static const MCDisassembler *createX86_32Disassembler(const Target &T) { 463 return new X86Disassembler::X86_32Disassembler; 464 } 465 466 static const MCDisassembler *createX86_64Disassembler(const Target &T) { 467 return new X86Disassembler::X86_64Disassembler; 468 } 469 470 extern "C" void LLVMInitializeX86Disassembler() { 471 // Register the disassembler. 472 TargetRegistry::RegisterMCDisassembler(TheX86_32Target, 473 createX86_32Disassembler); 474 TargetRegistry::RegisterMCDisassembler(TheX86_64Target, 475 createX86_64Disassembler); 476 } 477