1 //===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific TargetTransformInfo
11 /// implementation.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyTargetTransformInfo.h"
16 #include "llvm/CodeGen/CostTable.h"
17 #include "llvm/Support/Debug.h"
18 using namespace llvm;
19 
20 #define DEBUG_TYPE "wasmtti"
21 
22 TargetTransformInfo::PopcntSupportKind
23 WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
24   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
25   return TargetTransformInfo::PSK_FastHardware;
26 }
27 
28 unsigned WebAssemblyTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
29   unsigned Result = BaseT::getNumberOfRegisters(ClassID);
30 
31   // For SIMD, use at least 16 registers, as a rough guess.
32   bool Vector = (ClassID == 1);
33   if (Vector)
34     Result = std::max(Result, 16u);
35 
36   return Result;
37 }
38 
39 TypeSize WebAssemblyTTIImpl::getRegisterBitWidth(
40     TargetTransformInfo::RegisterKind K) const {
41   switch (K) {
42   case TargetTransformInfo::RGK_Scalar:
43     return TypeSize::getFixed(64);
44   case TargetTransformInfo::RGK_FixedWidthVector:
45     return TypeSize::getFixed(getST()->hasSIMD128() ? 128 : 64);
46   case TargetTransformInfo::RGK_ScalableVector:
47     return TypeSize::getScalable(0);
48   }
49 
50   llvm_unreachable("Unsupported register kind");
51 }
52 
53 unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
54     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
55     TTI::OperandValueKind Opd1Info,
56     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
57     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
58     const Instruction *CxtI) {
59 
60   unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
61       Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
62 
63   if (auto *VTy = dyn_cast<VectorType>(Ty)) {
64     switch (Opcode) {
65     case Instruction::LShr:
66     case Instruction::AShr:
67     case Instruction::Shl:
68       // SIMD128's shifts currently only accept a scalar shift count. For each
69       // element, we'll need to extract, op, insert. The following is a rough
70       // approxmation.
71       if (Opd2Info != TTI::OK_UniformValue &&
72           Opd2Info != TTI::OK_UniformConstantValue)
73         Cost =
74             cast<FixedVectorType>(VTy)->getNumElements() *
75             (TargetTransformInfo::TCC_Basic +
76              getArithmeticInstrCost(Opcode, VTy->getElementType(), CostKind) +
77              TargetTransformInfo::TCC_Basic);
78       break;
79     }
80   }
81   return Cost;
82 }
83 
84 unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
85                                                 unsigned Index) {
86   unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
87 
88   // SIMD128's insert/extract currently only take constant indices.
89   if (Index == -1u)
90     return Cost + 25 * TargetTransformInfo::TCC_Expensive;
91 
92   return Cost;
93 }
94 
95 bool WebAssemblyTTIImpl::areInlineCompatible(const Function *Caller,
96                                              const Function *Callee) const {
97   // Allow inlining only when the Callee has a subset of the Caller's
98   // features. In principle, we should be able to inline regardless of any
99   // features because WebAssembly supports features at module granularity, not
100   // function granularity, but without this restriction it would be possible for
101   // a module to "forget" about features if all the functions that used them
102   // were inlined.
103   const TargetMachine &TM = getTLI()->getTargetMachine();
104 
105   const FeatureBitset &CallerBits =
106       TM.getSubtargetImpl(*Caller)->getFeatureBits();
107   const FeatureBitset &CalleeBits =
108       TM.getSubtargetImpl(*Callee)->getFeatureBits();
109 
110   return (CallerBits & CalleeBits) == CalleeBits;
111 }
112 
113 void WebAssemblyTTIImpl::getUnrollingPreferences(
114   Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP) const {
115   // Scan the loop: don't unroll loops with calls. This is a standard approach
116   // for most (all?) targets.
117   for (BasicBlock *BB : L->blocks())
118     for (Instruction &I : *BB)
119       if (isa<CallInst>(I) || isa<InvokeInst>(I))
120         if (const Function *F = cast<CallBase>(I).getCalledFunction())
121           if (isLoweredToCall(F))
122             return;
123 
124   // The chosen threshold is within the range of 'LoopMicroOpBufferSize' of
125   // the various microarchitectures that use the BasicTTI implementation and
126   // has been selected through heuristics across multiple cores and runtimes.
127   UP.Partial = UP.Runtime = UP.UpperBound = true;
128   UP.PartialThreshold = 30;
129 
130   // Avoid unrolling when optimizing for size.
131   UP.OptSizeThreshold = 0;
132   UP.PartialOptSizeThreshold = 0;
133 
134   // Set number of instructions optimized when "back edge"
135   // becomes "fall through" to default value of 2.
136   UP.BEInsns = 2;
137 }
138